US20050098812A1 - Semiconductor device having a capacitor and method for the manufacture thereof - Google Patents
Semiconductor device having a capacitor and method for the manufacture thereof Download PDFInfo
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- US20050098812A1 US20050098812A1 US10/632,956 US63295603A US2005098812A1 US 20050098812 A1 US20050098812 A1 US 20050098812A1 US 63295603 A US63295603 A US 63295603A US 2005098812 A1 US2005098812 A1 US 2005098812A1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L28/40—Capacitors
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/314—Inorganic layers
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
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- Formation Of Insulating Films (AREA)
Abstract
A semiconductor device for use in a memory cell includes an active matrix provided with a silicon substrate, a transistor formed on the silicon substrate, a capacitor structure formed over the transistor, a metal interconnection for electrically connecting the capacitor structure to the transistor, a barrier layer formed on top of the metal interconnection and an inter-metal dielectric (IMD) layer formed on top of the barrier layer, wherein the barrier layer is made of a material such as Al2O3 or the like. The IMD layer is formed by using a plasma chemical vapor deposition (CVD) in a hydrogen rich atmosphere, wherein the barrier layer is used for preventing the capacitor structure from the hydrogen.
Description
- The present invention relates to a semiconductor device; and, more particularly, to a semiconductor device having a capacitor structure for use in a memory cell and a method for the manufacture thereof.
- As is well known, a dynamic random access memory (DRAM) with a memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by down-sizing through micronization. However, there is still a demand for downsizing the area of the memory cell.
- To meet the demand, therefore, there have been proposed several methods, such as a trench type or a stack type capacitor, which is arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing three-dimensionally arranged capacitor is a long and tedious one and consequently involves high manufacturing cost. Therefore, there is a strong demand for a new memory device that can reduce the cell area with securing a requisite volume of information without requiring complex manufacturing steps.
- In attempt to meet the demand, there have been proposed a ferroelectric random access memory (FeRAM) where a capacitor thin film with ferroelectric properties such as strontium bithmuth tantalate (SBT) is used for a capacitor in place of a conventional silicon oxide film or a silicon nitride film.
- In
FIG. 1 , there is shown a cross sectional view setting forth a conventionalsemiconductor memory device 100 for use as FeRAM, disclosed in U.S. Pat. No. 5,864,153, entitled “CAPACITOR STRUCTURE OF SEMICONDUCTOR MEMORY CELL AND FABRICATION PROCESS THEREOF”. Thesemiconductor memory device 100 includes anactive matrix 10 incorporating a metal oxide semiconductor (MOS) transistor therein, acapacitor structure 23 formed on top of theactive matrix 10, abit line 34, ametal interconnection 36 and aplate line 38. - In
FIGS. 2A to 2E, there are illustrated manufacturing steps involved in manufacturing a conventionalsemiconductor memory device 100. - The process for manufacturing the conventional
semiconductor memory device 100 begins with the preparation of anactive matrix 10 having asilicon substrate 2, a MOS transistor formed thereon as a selective transistor, anisolation region 4 and afirst insulating layer 16 formed on the MOS transistor and theisolation region 4. The firstinsulating layer 16, e.g., made of boron-phosphor-silicate glass (BPSG), is formed over the entire surface by chemical vapor deposition (CVD). The MOS transistor includes a pair ofdiffusion regions 6 serving as a source and a drain, agate oxide 8, aspacer 14 and agate line 12. - In a subsequent step, there is formed on top of the active matrix 10 a
buffer layer 18, afirst metal layer 20, adielectric layer 22 and asecond metal layer 24, sequentially, as shown inFIG. 2A . Thebuffer layer 18 is made of titanium (Ti) and thefirst metal layer 20 is made of platinum (Pt) Thedielectric layer 22 is made of a ferroelectric material. The buffer, the first and thesecond metal layers dielectric layer 20 is spin-on coated. - Thereafter, the
second metal layer 24 and thedielectric layer 22 are patterned into a predetermined configuration. And then, thefirst metal layer 20 and thebuffer layer 18 are patterned into a second predetermined configuration by using a photolithography method to thereby obtain acapacitor structure 23 having abuffer 18A, abottom electrode 20A, a capacitorthin film 22A and atop electrode 24A, as shown inFIG. 2B . Thebuffer layer 18A is used for ensuring reliable adhesion between thebottom electrode 20A and thefirst insulating layer 16. - In a next step, a second
insulating layer 26, e.g., made of silicon dioxide (SiO2), is formed on top of theactive matrix 10 and thecapacitor structure 23 by using a plasma CVD, as shown inFIG. 2C . - In an ensuing step, a first and a
second openings insulating layers diffusion regions 6, respectively. A third and afourth openings capacitor structure 23 through the secondinsulating layer 26, thereby exposing portions of the bottom and thetop electrodes FIG. 2D . - Thereafter, an interconnection layer, e.g., made of a conducting material such as aluminum (Al), is formed over the entire surface including the interiors of the
openings bit line 34, ametal interconnection 36 and aplate line 38, thereby obtaining thesemiconductor memory device 100, as shown inFIG. 2E . - In case when a multi-level process (not shown) is applied to the above-described
semiconductor device 100, an inter-metal dielectric (IMD) layer, e.g., made of SiO2, must be formed on top of thebit line 34, themetal interconnection 36 and theplate line 38 by using a plasma CVD for the purpose of the insulation between each metal layer. Since the plasma CVD utilizes silane (SiH4) as a source gas, the atmosphere for forming the IMD layer becomes a hydrogen rich atmosphere, and in this step, thesilicon substrate 2 is annealed at 400° C. - Therefore, the hydrogen gas generated by the plasma CVD process damages the capacitor
thin film 22A and thetop electrode 24A during the annealing process. That is, the hydrogen gas penetrates to thetop electrode 24A, further reaches to the capacitorthin film 22A and reacts with oxygen atoms constituting the ferroelectric material of the capacitorthin film 22A. - Furthermore, after the multi-level process, a passivation layer (not shown), e.g., made of SiO2, is formed thereon by using a plasma CVD. This process also has a hydrogen rich atmosphere. Therefore, the hydrogen gas generated by the passivation process also damages the
capacitor structure 23. - These problems, therefore, tend to make it difficult to obtain the desired reproducibility, reliability and yield.
- It is, therefore, an object of the present invention to provide a semiconductor device incorporating hydrogen barrier layers therein to prevent a capacitor thin film, e.g., made of a ferroelectric material, from a hydrogen damage which is caused by a plasma chemical vapor deposition (CVD) during the formation of an inter-metal dielectric layer or a passivation layer.
- It is another object of the present invention to provide a method for manufacturing a semiconductor device incorporating hydrogen barrier layers therein to prevent a capacitor thin film from a hydrogen damage which is generated by a plasma CVD during the formation of an inter-metal dielectric layer or a passivation layer.
- In accordance with one aspect of the present invention, there is provided a semiconductor device for use in a memory cell, including: an active matrix provided with a semiconductor substrate, a transistor formed on the semiconductor substrate, an isolation region for isolating the transistor and a first insulating layer formed on top of the transistor and the isolation region; a capacitor structure, formed on top of the first insulating layer, composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film; a second insulating layer formed on top of the transistor and the capacitor structure; a metal interconnection formed on top of the second insulating layer to electrically connect the transistor to the capacitor structure; a barrier layer formed on top of the metal connection; and an inter-metal dielectric (IMD) layer formed on top of the barrier layer by using a plasma chemical vapor deposition (CVD) in a hydrogen rich atmosphere, wherein the barrier layer is used for preventing the capacitor structure from the hydrogen.
- In accordance with another aspect of the present invention, there is provided a method for manufacturing a semiconductor device for use in a memory cell, the method comprising the steps of: a) preparing an active matrix provided with a transistor and a first insulating layer formed around the transistor; b) forming a capacitor structure on top of the first insulating layer, wherein the capacitor structure includes a capacitor thin film made of a ferroelectric material; c) forming a first metal layer and patterning a first metal layer into a first predetermined configuration to electrically connect the transistor to the capacitor structure; d) a first barrier layer on top of the patterned first metal layer; and e) an inter-metal dielectric (IMD) layer formed on top of the first barrier layer by using a plasma chemical vapor deposition (CVD) in a hydrogen rich atmosphere, wherein the barrier layer is used for preventing the capacitor structure from the hydrogen.
- The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:
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FIG. 1 shows a cross sectional view representing a prior art semiconductor memory device having a capacitor structure; -
FIGS. 2A to 2E are schematic cross sectional views illustrating a prior art method for the manufacture of a semiconductor memory device; -
FIG. 3 is a cross sectional view setting forth a semiconductor device in accordance with the present invention; and -
FIGS. 4A to 4H are schematic cross sectional views setting forth a method for the manufacture of the semiconductor memory device in accordance with the present invention. - There are provided in
FIGS. 3 and 4 A to 4H a cross sectional view of asemiconductor device 200 for use in a memory cell and cross sectional views setting forth a method for the manufacture thereof in accordance with preferred embodiments of the present invention. It should be noted that like parts appearing inFIGS. 3 and 4 A to 4H are represented by like reference numerals. - In
FIG. 3 , there is provided a cross sectional view of theinventive semiconductor device 200 comprising anactive matrix 210, a secondinsulating layer 226, abit line 234, ametal interconnection 236, afirst barrier layer 238, an inter-metal dielectric (IMD)layer 240 and acapacitor structure 250. TheIMD layer 240, e.g., made of SiOx, is disposed between thefirst barrier layer 238 and thebit line 234 and themetal interconnection 236, wherein theIMD layer 240 is formed by using a plasma chemical vapor depodition (CVD) in a hydrogen rich atmosphere. The plasma CVD is carried out at a low temperature by using silane (SiH4) as a source gas. It is preferable that thefirst barrier layer 238 is made of a material such as Al2O3and has a thickness ranging from approximately 50 Å to approximately 150 Å. In the preferred embodiment, thefirst barrier layer 238 is formed by using a method such as an atomic layer deposition (ALD) method. Specifically, the ALD method is carried out as follows: a layer of trimethyl aluminum (TMA) is formed on top of thebit line 234, ametal interconnection 236 and the secondinsulating layer 226 in a low temperature, e.g., approximately 350° C.; and the layer is oxidized by using H2O as a source gas and using N2 as a purge gas, thereby obtaining a layer of Al2O3. - In addition, the
semiconductor device 200 further includes athird metal layer 242 formed on top of theIMD layer 240, asecond barrier layer 244 formed on top of thethird metal layer 242 and apassivation layer 246 formed on top of thesecond barrier layer 244. Thepassivation layer 246 is formed by using a plasma CVD in a hydrogen rich atmosphere. In the preferred embodiment, thesecond barrier layer 244, e.g., made of a material such as Al2O3, is formed by using a method such as an ALD method to prevent thecapacitor structure 250 from the hydrogen. - In the
semiconductor device 200, thebit line 234 is electrically connected to one of thediffusion regions 206 and thetop electrode 224A is electrically connected to theother diffusion region 206 through themetal interconnection 236, wherein thebit line 234 and themetal interconnection 236 are electrically disconnected each other. Thebottom electrode 220A may be connected to a plate line (not shown) to apply a common constant potential thereto. -
FIGS. 4A to 4H are schematic cross sectional views setting forth the method for manufacture of asemiconductor memory device 200 in accordance with the present invention. - The process for manufacturing the
semiconductor device 200 begins with the preparation of anactive matrix 210 including asemiconductor substrate 202, anisolation region 204,diffusion regions 206, agate oxide 208, agate line 212, aspacer 214 and a first insulatinglayer 216, as shown inFIG. 4A . One of thediffusion regions 206 serves as a source and theother diffusion region 206 serves as a drain. The first insulatinglayer 216 is made of a material, e.g., boron-phosphor-silicate glass (BPSG). - Thereafter, a
buffer layer 218, e.g., made of Ti or TiOx, is formed on top of the first insulatinglayer 216. And, afirst metal layer 220, adielectric layer 222 and asecond metal layer 224 are formed on top of thebuffer layer 218, subsequently. In the preferred embodiment, the metal layers 220, 224 can be made of a material including, but not limited to: platinum (Pt), IrOx, RuOx or the like. Thedielectric layer 222 is made of a ferroelectric material such as SBT, PZT or the like and formed by using a method such as a spin coating, a chemical vapor deposition (CVD) or the like. - As shown in
FIG. 4B , thesecond metal layer 224 and thedielectric layer 222 are patterned into a first predetermined configuration to obtain atop electrode 224A and a capacitorthin film 222A. And then, thefirst metal layer 220 and thebuffer layer 218 are patterned into a second predetermined configuration to obtain a bottom electrode structure, thereby forming acapacitor structure 250 having abuffer 218A, abottom electrode 220A, a capacitorthin film 222A and atop electrode 224A. It is preferable that thebottom electrode 220A has a size different from that of the top electrode 228A in order to form a plate line (not shown) during the following processes. - Thereafter, a second insulating
layer 226, e.g., made of a material, e.g., BPSG, is formed on top of thecapacitor structure 250 and the first insulatinglayer 216 by using a method such as CVD and made flat by means of chemical mechanical polishing (CMP), as shown inFIG. 4C . - As shown in
FIG. 4D , a first and asecond openings diffusion regions 206 through the second and the first insulatinglayers third opening 232 is formed at a position over thecapacitor structure 250 through the second insulatinglayer 226 by using a method such as a photolithography or a plasma etching. - As shown in
FIG. 4E , an interconnection metal layer, e.g., made of Al, is formed over the entire surface including the interiors of theopenings bit line 234 and ametal interconnection 236. - In a following step, a
first barrier layer 238, e.g., made of Al2O3, is formed on top of thebit line 234, themetal interconnection 236 and the second insulatinglayer 226 by using a method such as a ALD method, as shown inFIG. 4F . The ALD method is carried out as follows: a layer of TMA is formed on top of thebit line 234, themetal interconnection 236 and the second insulatinglayer 226 in a low temperature, e.g., approximately 350° C.; and the layer of TMA is oxidized by using H2O as a source gas and N2 as a purge gas, thereby obtaining a layer of Al2O3. The ALD method can be carried out by using a four cyclic deposition, which includes the steps of: flowing TMA gas in a first predetermined time; flowing N2 purge gas in a second predetermined time; flowing H2O oxidation gas in a third predetermined time; and flowing N2 purge gas in a fourth predetermined time. It is preferable that the first barrier layer has a thickness ranging from approximately 50 Å to approximately 150 Å. - In an ensuing step, as shown in
FIG. 4G , an inter-metal dielectric layer (IMD) 240, e.g., made of a oxide material such as SiO2, is formed on top of thefirst barrier layer 238 by using a method such as a plasma CVD. The plasma CVD is carried out at a low temperature by using SiH4 as a source gas. And then, athird metal layer 242, e.g., made of Al, is formed on top of theIMD layer 240 to apply a multi-level process. In the figures, each of thelayers - Thereafter, as shown in
FIG. 4H , asecond barrier layer 244, e.g., made of Al2O3, is formed on top of thethird metal layer 242 by using a method such as an ALD method. The ALD method of thesecond barrier layer 244 is similar to that of thefirst barrier layer 238. It is preferable that thesecond barrier layer 244 has a thickness ranging from approximately 50 Å to approximately 150 Å. - In an ensuing step, a
passivation layer 246, e.g., made of Si3N4, is formed on top of thesecond barrier layer 244 by using a method such as a plasma CVD to protect thesemiconductor device 200 from an external detrimental envelopment such as moisture, particles or the like. - In comparison with the prior art, the present invention prevents a
capacitor structure 250 from hydrogen damages caused by the formations of an IMD and a passivation layers. This is achieved by utilizing barrier layers, which will not penetrate a hydrogen gas into thecapacitor structure 250. - While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.
Claims (22)
1. A semiconductor device for use in a memory cell, comprising:
an active matrix provided with a semiconductor substrate, a transistor formed on the semiconductor substrate, an isolation region for isolating the transistor and a first insulating layer formed on top of the transistor and the isolation region;
a capacitor structure, formed on top of the first insulating layer, composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film;
a second insulating layer formed on top of the transistor and the capacitor structure;
a metal interconnection formed on top of the second insulating layer to electrically connect the transistor to the capacitor structure;
a barrier layer formed on top of the metal interconnection; and
an inter-metal dielectric (IMD) layer formed on top of the barrier layer by using a plasma chemical vapor deposition (CVD) in a hydrogen rich atmosphere, wherein the barrier layer is used for preventing the capacitor structure from the hydrogen.
2. The semiconductor device of claim 1 , wherein the capacitor thin film is made of a ferroelectric material selected from a group consisting of SBT (SrBiTaOx), PZT (PbZrTiOx) or the like.
3. The semiconductor device of claim 2 , wherein the IMD layer is made of a oxide material such as SiO2.
4. The semiconductor device of claim 3 , wherein the plasma CVD is carried out at a low temperature by using silane (SiH4) as a source gas.
5. The semiconductor device of claim 1 , wherein the barrier layer is made of a material such as Al2O3.
6. The semiconductor device of claim 5 , wherein the barrier layer has a thickness ranging from approximately 50 Å to approximately 150 Å.
7. The semiconductor device of claim 6 , wherein the barrier layer is formed by using an atomic layer deposition (ALD) method.
8. The semiconductor device of claim 7 , wherein the ALD method is carried out by using trimethyl aluminum (TMA) and H2O as a source gas and using N2 as a purge gas.
9. The semiconductor device of claim 1 , further comprising:
a metal line formed on top of the IMD layer;
an additional barrier layer formed on top of the metal line;
a passivation layer formed on top of the additional barrier layer by using a plasma CVD in a hydrogen rich atmosphere, wherein the additional barrier layer is used for preventing the capacitor structure from the hydrogen.
10. The semiconductor device of claim 9 , wherein the additional barrier layer is made of a material such as Al2O3.
11. The semiconductor device of claim 10 , wherein the additional barrier layer is formed by using an ALD method.
12. A method for manufacturing a semiconductor device for use in a memory cell, the method comprising the steps of:
a) preparing an active matrix provided with a transistor and a first insulating layer formed around the transistor;
b) forming a capacitor structure on top of the first insulating layer, wherein the capacitor structure includes a capacitor thin film made of a ferroelectric material;
c) forming a first metal layer and patterning a first metal layer into a first predetermined configuration to electrically connect the transistor to the capacitor structure;
d) forming a first barrier layer on top of the patterned first metal layer; and
e) forming an inter-metal dielectric (IMD) layer formed on top of the first barrier layer by using a plasma chemical vapor deposition (CVD) in a hydrogen rich atmosphere, wherein the barrier layer is used for preventing the capacitor structure from the hydrogen.
13. The method of claim 12 , wherein the capacitor thin film is made of a material selected from a group consisting of SBT, PZT or the like.
14. The method of claim 13 , wherein the IMD layer is made of a oxide material such as SiO2.
15. The method of claim 14 , wherein the plasma CVD is carried out at a low temperature by using SiH4 as a source gas.
16. The method of claim 15 , wherein the first barrier layer is made of a material such as Al2O3.
17. The method of claim 16 , wherein the first barrier layer has a thickness ranging from approximately 50 Å to approximately 150 Å.
18. The method of claim 17 , wherein the first barrier layer is formed by using an ALD method.
19. The method of claim 18 , wherein the ALD method is carried out by using TMA and H2O as a source gas and using N2 as a purge gas.
20. The method of claim 12 , after the step e), further comprising the steps of:
f) a second metal layer formed on top of the IMD layer;
g) a second barrier layer formed on top of the second metal layer; and
h) a passivation layer formed on top of the additional barrier layer by using a plasma CVD in a hydrogen rich atmosphere, wherein the additional barrier layer is used for preventing the capacitor structure from the hydrogen.
21. The method of claim 20 , wherein the second barrier layer is made of a material such as Al2O3.
22. The semiconductor device of claim 21 , wherein the step g) is carried out by using an ALD method.
Priority Applications (1)
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US10/632,956 US20050098812A1 (en) | 1999-06-28 | 2003-08-04 | Semiconductor device having a capacitor and method for the manufacture thereof |
Applications Claiming Priority (4)
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KR1999-25003 | 1999-06-28 | ||
KR1019990025003A KR100329781B1 (en) | 1999-06-28 | 1999-06-28 | Method for forming feram capable of preventing hydrogen diffusion |
US09/605,758 US6627462B1 (en) | 1999-06-28 | 2000-06-28 | Semiconductor device having a capacitor and method for the manufacture thereof |
US10/632,956 US20050098812A1 (en) | 1999-06-28 | 2003-08-04 | Semiconductor device having a capacitor and method for the manufacture thereof |
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US09/605,758 Division US6627462B1 (en) | 1999-06-28 | 2000-06-28 | Semiconductor device having a capacitor and method for the manufacture thereof |
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US09/605,758 Expired - Lifetime US6627462B1 (en) | 1999-06-28 | 2000-06-28 | Semiconductor device having a capacitor and method for the manufacture thereof |
US10/632,956 Abandoned US20050098812A1 (en) | 1999-06-28 | 2003-08-04 | Semiconductor device having a capacitor and method for the manufacture thereof |
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US (2) | US6627462B1 (en) |
JP (1) | JP2001068639A (en) |
KR (1) | KR100329781B1 (en) |
TW (1) | TW503559B (en) |
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Also Published As
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KR20010004372A (en) | 2001-01-15 |
US6627462B1 (en) | 2003-09-30 |
TW503559B (en) | 2002-09-21 |
KR100329781B1 (en) | 2002-03-25 |
JP2001068639A (en) | 2001-03-16 |
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