US20050029617A1 - Semiconductor module - Google Patents
Semiconductor module Download PDFInfo
- Publication number
- US20050029617A1 US20050029617A1 US10/934,451 US93445104A US2005029617A1 US 20050029617 A1 US20050029617 A1 US 20050029617A1 US 93445104 A US93445104 A US 93445104A US 2005029617 A1 US2005029617 A1 US 2005029617A1
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- Prior art keywords
- semiconductor chip
- mis transistor
- semiconductor
- chip
- semiconductor module
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 214
- 239000002184 metal Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 22
- 239000010410 layer Substances 0.000 description 32
- 230000004048 modification Effects 0.000 description 18
- 238000012986 modification Methods 0.000 description 18
- 230000008901 benefit Effects 0.000 description 7
- 230000003247 decreasing effect Effects 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000000191 radiation effect Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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Definitions
- the present invention relates to a semiconductor module. Specifically, the invention relates to a semiconductor module including a plurality of semiconductor chips.
- a DC-DC converter for use in synchronous rectification or the like is known.
- FIG. 14 schematically shows a commonly-used circuit of the above DC-DC converter.
- a capacitor Cin is connected between an input terminal Vin to which an input voltage is applied and a ground.
- the input terminal Vin is connected to the drain of an N-type MIS (metal insulator semiconductor) transistor Q 1 whose channel (current path) is of an N type.
- the MIS transistor includes a MOS (metal oxide semiconductor) transistor.
- the gate of the MIS transistor Q 1 is connected to an IC for DC-DC conversion.
- the MIS transistor Q 1 functions as a switching device.
- the source of the MIS transistor Q 1 is connected to the drain of an N-type MIS transistor Q 2 .
- the source of the MIS transistor Q 2 is connected to the ground and the gate thereof is connected to the IC.
- a connection node N 1 between the source of the MIS transistor Q 1 and the drain of the MIS transistor Q 2 is connected to the cathode of a diode D 1 .
- the anode of the diode D 1 is connected to the ground.
- the connection node N 1 is connected to an output terminal Vout via an inductance L.
- a capacitor Cout is connected in parallel between the output terminal Vout and the ground.
- R L indicates a load resistance.
- the MIS transistor Q 1 is implemented by a single semiconductor chip 41 and the MIS transistor Q 2 is done by a single semiconductor chip 42 .
- Each of the MIS transistors has a known vertical structure as shown in FIG. 15 .
- a drain electrode is formed on the bottom of each of the semiconductor chips 41 and 42 .
- reference symbols S, D and G denote a source, a drain and a gate, respectively.
- FIG. 16A schematically shows an outward appearance of a semiconductor module having semiconductor chips 41 and 42 according to first prior art
- FIG. 16B schematically shows an internal structure of the semiconductor module.
- the first prior is shown taking a known SOP-8 package as an example.
- reference numeral 43 indicates a package (envelope)
- reference numeral 44 denotes an external connecting terminal part of which is exposed to the semiconductor module.
- the semiconductor chip 41 or 42 which has the transistor structure as shown in FIG. 15 , is mounted on a conductive frame 45 such that the bottom of the chip 41 or 42 contacts the frame 45 .
- the frame 45 is connected to the external connecting terminal 44
- the semiconductor chip 41 or 42 is connected to the external connecting terminal 44 through a wire 46 .
- the bottom of the semiconductor chip 41 or 42 serves as a drain electrode.
- the source of the MIS transistor Q 1 and the drain of the MIS transistor Q 2 are connected to each other in the DC-DC converter shown in FIG. 14 .
- the semiconductor chips 41 and 42 are separately sealed with their respective semiconductor modules, and these modules are connected to each other by a wire or the like on a mounting substrate.
- FIG. 17 schematically shows the interior of a semiconductor module according to second prior art in order to describe a method of packaging semiconductor chips.
- two frames 45 are provided and semiconductor chips 41 and 42 are mounted on the frames 45 , respectively.
- the frames 45 are connected to the semiconductor chips 41 and 42 appropriately by wires so as to achieve the circuit arrangement shown in FIG. 14 .
- a single semiconductor module can be obtained; however, given wiring is required inside or outside the semiconductor module and the semiconductor module cannot operate at high speed. Since, moreover, an interval Z between the frames 45 depends upon the power supply voltage or the potential of each of the frames, it cannot be set to not larger than a given value, thus imposing restrictions on miniaturization of the semiconductor module.
- a semiconductor module comprising: a supporting substrate having a first major surface and a conductive connecting section, the connecting section being formed on the first major surface; a first semiconductor chip including a first MIS transistor of a first conductivity type and provided on the supporting substrate, a source of the first MIS transistor being formed on a bottom of the first MIS transistor and connected to the connecting section; a second semiconductor chip including a second MIS transistor of the first conductivity type and provided on the supporting substrate, a drain of the second transistor being formed on a bottom of the second MIS transistor and connected to the connecting section, and the drain of the second MIS transistor being electrically connected to the source of the first MIS transistor through the connecting section; an IC chip provided on the first major surface of the supporting substrate, the IC chip being connected to both a gate of the first MIS transistor and a gate of the second MIS transistor; an insulative envelope which covers the supporting substrate, the first semiconductor chip, the second semiconductor chip, and the IC chip; and connecting terminal
- a semiconductor module comprising: a supporting substrate having a first major surface and a second major surface opposed to the first major surface and including a conductive connecting section, the connecting section being formed on the first major surface; a first semiconductor chip including a first MIS transistor of a first conductivity type and provided on the supporting substrate, a source of the first MIS transistor being formed on a bottom of the first MIS transistor and connected to the connecting section; a second semiconductor chip including a second MIS transistor of the first conductivity type and provided on the supporting substrate, a drain of the second MIS transistor being formed on a bottom of the second MIS transistor and connected to the connecting section, and the drain of the second MIS transistor being electrically connected to the source of the first MIS transistor through the connecting section; an insulative envelope which covers the supporting substrate, the first semiconductor chip, and the second semiconductor chip, the envelope having an opening through which the second major surface is partly exposed; and a connecting terminals electrically connected to the connecting section, the first semiconductor chip, and the
- FIG. 1 is a cross-sectional view schematically showing an example of a lateral MIS transistor structure
- FIG. 2 is a schematic view of the interior of a semiconductor module according to a first embodiment of the present invention
- FIG. 3 is a cross-sectional view schematically showing a semiconductor chip of a semiconductor module according to a first modification to the first embodiment of the present invention
- FIG. 4 is a cross-sectional view schematically showing a semiconductor chip of a semiconductor module according to a second modification to the first embodiment of the present invention
- FIG. 5 is a schematic view of the interior of a semiconductor module according to a third modification to the first embodiment of the present invention.
- FIG. 6 is a schematic view of the underside of a semiconductor module according to second prior art
- FIGS. 7A and 7B are schematic views of the underside of a semiconductor module according to a second embodiment of the present invention.
- FIG. 8 is a schematic view of the interior of a semiconductor module according to a third embodiment of the present invention.
- FIG. 9 is a schematic view of the interior of a semiconductor module according to a modification to the third embodiment of the present invention.
- FIG. 10 is a circuit diagram showing a multi-phased circuit of a DC-DC converter as shown in FIG. 14 ;
- FIG. 11 is a schematic view of the interior of a semiconductor module according to a fourth embodiment of the present invention.
- FIG. 12 is a schematic view of the interior of a semiconductor module according to a modification to the fourth embodiment of the present invention.
- FIG. 13 is a circuit diagram showing an example of a DC-DC converter
- FIG. 14 is a circuit diagram of a commonly-used DC-DC converter
- FIG. 15 is a cross-sectional view schematically showing an example of a vertical MIS transistor structure
- FIGS. 16A and 16B are schematic views of a semiconductor module according to first prior art.
- FIG. 17 is a schematic view of a semiconductor module according to second prior art to describe a method of packaging semiconductor chips.
- FIG. 1 schematically shows a section of an example of the lateral structure.
- a p-type epitaxial layer 2 is formed on a p-type semiconductor substrate 1 by, e.g., epitaxial growth.
- An n-type layer 3 is formed on the surface of the p-type epitaxial layer 2 by, e.g., ion implantation and an n + -type layer 4 is formed in the n-type layer 3 .
- the concentration of the n + -type layer 4 is higher than that of the n-type layer 3 .
- a p-type layer 5 is formed at either end of the n-type layer 3 in the p-type epitaxial layer 2 , and n + -type layers 6 are formed in the p-type layer 5 at a given interval.
- a p + -type layer 7 is formed so as to reach the semiconductor substrate 1 from the n + -type layers 6 .
- a wiring layer 11 made of conductive materials is formed on the p-type epitaxial layer 2 and over the n + -type layer 4 .
- a drain electrode 12 is formed above the n + -type layer 4 .
- the wiring layer 11 connects the drain electrode 12 and the n + -type layer 4 .
- a gate electrode 13 is formed on the p-type epitaxial layer 2 and between the n-type layer 3 and one of the n + -type layers 6 .
- the wiring layer 11 and gate electrode 13 are insulated from each other by an interlayer insulation film 14 .
- a contact layer 15 is formed on the p-type epitaxial layer 2 and between the n + -type layers 6 in the p-type layer 5 .
- the contact layer 15 is electrically connected to a source electrode 16 , which is formed on the entire bottom of the semiconductor substrate 1 , through the p + -type layer 7 .
- the above MIS transistor structure is taken as one example. Another type of MIS transistor can be provided if it has only to be so configured that a source electrode is formed on the bottom of the semiconductor substrate.
- FIG. 2 schematically shows the interior of a semiconductor module according to a first embodiment of the present invention. Since the outward appearance of the semiconductor module is the same as that of the module shown in FIG. 16A , its descriptions are omitted.
- reference numeral 21 indicates a frame (supporting substrate) of given size.
- the frame 21 is made of, e.g., conductive materials.
- a connecting section 21 a such as a conductive wiring pattern can be formed on an insulative substrate having good thermal conduction. In this case, semiconductor chips (described later) are connected to each other through the connecting section 21 a , and the connecting section 21 a is electrically connected to an external connecting terminal.
- the connecting section 21 a can be provided on the entire surface of the frame 21 .
- a semiconductor chip 22 is mounted on the frame 21 and has an N-type lateral MIS transistor structure as shown in FIG. 1 .
- a source is formed on the bottom of the semiconductor chip 22 and contacts the frame 21 .
- the semiconductor chip 22 has a function of the MIS transistor Q 1 as a switching device of the DC-DC converter illustrated in FIG. 14 .
- a semiconductor chip 23 is mounted on the frame 21 at a given distance from the semiconductor chip 22 .
- the semiconductor chip 23 has a diode structure whose bottom serves as a cathode that contacts the frame 21 .
- the semiconductor chip 23 has a function of the diode D 1 of the DC-DC converter shown in FIG. 14 .
- a semiconductor chip 24 is mounted on the frame 21 at a given distance from the semiconductor chip 23 .
- the semiconductor chip 23 has an N-type vertical MIS transistor structure as shown in FIG. 15 .
- a drain is formed on the bottom of the semiconductor chip 24 and contacts the frame 21 .
- the terminal of the semiconductor chip 23 which serves as an anode, is connected to an external connecting terminal 44 of the chip 24 , which corresponds to that shown in FIG. 16A , through a wire 31 .
- the semiconductor chip 22 , semiconductor substrate 23 and semiconductor chip 24 are electrically connected to each other with the frame 21 as a common potential. Both a drain and a gate provided on the top of the semiconductor chip 22 are connected to given external connecting terminals 44 through wires 31 , as are both a source and a gate provided on the top of the semiconductor chip 24 .
- the frame 21 is connected to the external connecting terminals 44 .
- the frame 21 , semiconductor chips 22 , 23 and 24 and some of the external connecting terminals 44 are sealed with a package to form a semiconductor module.
- the diode D 1 of the circuit shown in FIG. 14 is arranged on the frame 21 as an independent semiconductor chip.
- the first embodiment is not limited to this arrangement.
- the diode D 1 can be formed within the semiconductor chip 24 of the vertical MIS transistor structure.
- FIG. 3 schematically shows a section of a semiconductor chip according to a first modification to the first embodiment of the present invention.
- the semiconductor chip shown in FIG. 3 includes a diode 33 such as a Schottky barrier diode as well as an MIS transistor 34 .
- reference numeral 35 denotes barrier metal.
- the cathode C of the diode 33 serves as the drain D of the MIS transistor 34 , too.
- the number of semiconductor chips can be decreased more than when the diode D 1 serves as an independent semiconductor chip.
- the diode D 1 can also be formed within the semiconductor chip 22 of the lateral MIS transistor structure.
- FIG. 4 schematically shows a section of a semiconductor chip according to a second modification to the first embodiment of the present invention.
- a diode-forming region (diode) 37 an anode electrode A is formed on an n-type well layer 36 with the barrier metal 35 interposed therebetween.
- a cathode 15 of the diode 37 is provided so that an oxide silicon film 38 is provided between the anode electrode A and the cathode 15 .
- the cathode 15 also serves as the source S of the MIS transistor 34 .
- This cathode/source 15 is connected to a cathode/source electrode 16 through a connecting layer 39 .
- the number of semiconductor chips can be reduced further as in the first modification.
- FIG. 5 schematically shows the interior of a semiconductor module according to a third modification to the first embodiment of the present invention.
- an IC chip 40 can be mounted on the frame 21 with insulating materials (not shown) interposed therebetween.
- the IC chip is connected to the external connecting terminals and semiconductor chips 22 to 24 through the wires 31 .
- the number of semiconductor modules can be decreased more than when the IC chip 40 serves as an independent semiconductor module.
- the semiconductor chips 22 and 23 are arranged on the left side of the frame 21 and the semiconductor chip 24 is arranged on the right side thereof.
- the first embodiment is not limited to this arrangement. These semiconductor chips have only to be arranged such that the frame 21 serves as their common potential. It is needless to say that the position of the IC chip 40 is not limited to that shown in FIG. 5 .
- the first embodiment of the present invention is directed to a semiconductor module used for composing a circuit having two MIS transistors and using a source of one of the MIS transistors and a drain of the other as potentials common to the MIS transistors.
- this semiconductor module both the semiconductor chip 22 of an MIS transistor structure whose bottom serves as a source and the semiconductor chip 24 of an MIS transistor structure whose bottom serves as a drain are arranged on the single frame 21 .
- the total number of semiconductor modules is therefore smaller than that in the first prior art.
- Electronic equipment including such a semiconductor module can be decreased in size. Since the space, which would be necessary between frames in the second prior art, need not be formed, the semiconductor module can be decreased in size more than that of the second prior art.
- a semiconductor module need not be provided for each MIS transistor.
- the semiconductor modules need not be connected by, e.g., a wire unlike in the first prior art or the frames need not be connected by, e.g., a wire inside or outside a semiconductor module unlike in the second prior art. Resistance and inductance caused by the wire can thus be eliminated; accordingly, the semiconductor modules can be operated with stability and at high speed.
- a plurality of semiconductor chips can be mounted on a single frame. It is thus unnecessary to take into consideration the coplanarity of the frame when the semiconductor chips are mounted on the frame.
- the area of the frame 21 can be increased. Heat can thus be dispersed more effectively than that in the second prior art. Since heat moves through the frame 21 , it can be uniformed on the frame. Assume that the maximum assurance temperature of one of the semiconductor chips (e.g., semiconductor chip 22 ) is 150° C. If, in this case, the power loss of the semiconductor chip 22 increases and the temperatures of the semiconductor chips 22 and 24 reach 160° C. and 110° C., respectively, then the semiconductor module becomes unworkable. According to the first embodiment, however, heat generated from the semiconductor chip 22 can be moved to the semiconductor chip 24 and uniformed on the frame 21 . Consequently, the possibility that the temperature of each of the semiconductor chips exceeds the maximum assurance temperature can be decreased.
- the maximum assurance temperature of one of the semiconductor chips e.g., semiconductor chip 22
- the second embodiment is a modification to the first embodiment.
- a radiation effect can be improved by exposing each of frames 45 to the underside of a package as shown in FIG. 6 . Since, however, the number of frames 45 is two or more, the coplanarity of each of the frames 45 has to be considered in the manufacturing process of the semiconductor module. Poor coplanarity decreases the radiation effect of each of the frames 45 and causes trouble when the semiconductor module is mounted on a mounting substrate or the like. In the second embodiment, therefore, a frame, which is common to the two semiconductor chips in the semiconductor module of the first embodiment, is exposed to the underside of the package.
- FIGS. 7A and 7B are plan views schematically showing the underside of a semiconductor module according to the second embodiment of the present invention.
- an opening is formed in the underside of a package 43 and part of a frame 21 is exposed through the opening.
- the frame 21 can be formed integrally with external connecting terminals 44 as one component and exposed to the package 43 . In this case, the area of the exposed part of the frame 21 can be increased.
- the frame 21 and external connecting terminals 44 can be connected inside the package 43 as shown in FIG. 7A or outside the package 43 as shown in FIG. 7B . Since the other structure is the same as that of the first embodiment, its descriptions are omitted.
- the semiconductor module according to the second embodiment produces the same advantage as that of the semiconductor module according to the first embodiment. Further, since part of the frame 21 common to the semiconductor chips is exposed to the underside of the package 43 , the area of the exposed part can be increased; accordingly, the radiation effect can be made greater than that in the second prior art.
- a semiconductor module can be formed without considering any coplanarity of two frames. It is thus possible to prevent trouble from occurring when such a semiconductor module is mounted on a mounting substrate. Consequently, the yield of semiconductor modules can be improved and the manufacturing costs thereof can be lowered.
- the semiconductor chips in the semiconductor module and external connecting terminals are connected by wires, respectively.
- some of these connections are implemented by a strap structure.
- FIG. 8 is a plan view schematically showing the interior of a package 43 of a semiconductor module according to the third embodiment of the present invention.
- a semiconductor chip 22 and an external connecting terminal 44 are connected to each other by a conductive member 32 of a planar structure or a strap structure having a given width, as are a semiconductor chip 24 and an external connecting terminal 44 . Since the other structure is the same as that of the first embodiment, its descriptions are omitted.
- the semiconductor module according to the third embodiment produces the same advantage as that of the first embodiment. Further, since the semiconductor chips 22 and 24 are connected to the external connecting terminals 44 by the conductive members 32 of the strap structure, more heat can radiate from the semiconductor chips 22 and 24 . Furthermore, wiring resistance and inductance can be lowered more than when they are connected by wires 31 .
- FIG. 9 schematically shows the interior of a semiconductor module according to a modification to the third embodiment.
- An IC chip 40 is provided in a semiconductor module.
- the modification produces the same advantage as that of the first embodiment.
- the first to third embodiments are directed to two semiconductor chips.
- the fourth embodiment is directed to three or more semiconductor chips.
- FIG. 10 shows a multi-phased circuit, e.g., a three-phased circuit of a DC-DC converter as shown in FIG. 14 .
- one master clock is divided into three to alternately operate three DC-DC converters and increase the operating frequency of the entire DC-DC converters.
- One DC-DC converter is made up of a transistor Q 1 , a transistor Q 2 and a diode D 1
- another DC-DC converter is made up of a transistor Q 3 , a transistor Q 4 and a diode D 2
- the other DC-DC converter is made up of a transistor Q 5 , a transistor Q 6 and a diode D 3 .
- the transistors and diodes of these DC-DC converters are connected to each other as those of the DC-DC converter shown in FIG. 14 .
- the other circuit arrangement is the same as that shown in FIG. 14 .
- FIG. 11 schematically shows the interior of a semiconductor module according to the fourth embodiment of the present invention.
- each phase requires semiconductor chips 22 and 24 each serving as a switching device and a semiconductor chip 23 having a diode function.
- a single semiconductor module therefore includes the semiconductor chips 22 , 23 and 24 .
- semiconductor chips by the required number are arranged on a frame 21 .
- a semiconductor chip 22 having a lateral MIS transistor structure is used as a chip whose source needs to be connected to the frame 21 .
- a vertical semiconductor chip 24 is used as a chip whose drain needs to be connected to the frame 21 .
- Each semiconductor chip is connected to given external connecting terminals 44 by wires 31 . Since the other structure is the same as that of the first embodiment, its descriptions are omitted.
- the semiconductor module according to the fourth embodiment produces the same advantage as that of the first embodiment.
- a plurality of semiconductor chips can be provided in a single module by appropriately selecting them as ones having a lateral or vertical MIS transistor structure and using the frame 21 as a common potential. For this reason, a switching device required for, e.g., a multi-phased DC-DC converter can be provided in a single semiconductor module.
- FIG. 12 schematically shows the interior of a semiconductor module according to a modification to the fourth embodiment. Since the semiconductor module includes an IC chip 40 , the modification produces the same advantage as that of the first embodiment.
- an N-type MIS transistor is used as a switching device of the circuit shown in FIG. 14 .
- the present invention is not limited to this use, but a P-type MIS transistor can be used.
- the first to third embodiments can be employed if the conductivity types of two MIS transistors are the same.
- FIG. 13 shows an example of a DC-DC converter using a P-type MIS transistor as a switching device.
- reference numerals Q 3 and Q 4 indicate P-type MIS transistors.
- the source of the MIS transistor Q 3 is connected to an input terminal Vin and the drain thereof is connected to a connection node N 1 .
- the source of the MIS transistor Q 4 is connected to the connection node N 1 and the drain thereof is grounded.
- the other circuit arrangement is the same as that shown in FIG. 14 .
- a semiconductor chip of a vertical MIS transistor structure whose bottom serves as a drain is used as a semiconductor chip 51 including the MIS transistor Q 3 .
- Such a semiconductor chip has a structure in which the conductivity types of the semiconductor chip shown in FIG. 15 are inverted.
- a semiconductor chip of a lateral MIS transistor structure whose bottom serves as a source is used as a semiconductor chip 52 including the MIS transistor Q 4 .
- Such a semiconductor chip has a structure in which the conductivity types of the semiconductor chip shown in FIG. 1 are inverted.
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Abstract
A semiconductor module includes a supporting substrate having a connecting section on a first major surface thereof. A first semiconductor chip includes a first MIS transistor a source of which is formed on the bottom thereof. A second semiconductor chip includes a second MIS transistor a drain of which is formed on the bottom thereof. The first and second semiconductor chips are on the supporting substrate such that the source of the first MIS transistor and the drain of the second MIS transistor are connected to the connecting section and connected each other through the connecting section. An IC chip is provided on the first major surface and connected to gates of the first and second MIS transistors. An insulative envelope covers the supporting substrate, first and second semiconductor chips and IC chip. Partly exposed connecting terminals are electrically connected to the connecting section and first and second semiconductor chips.
Description
- This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-140293, filed May 15, 2002, the entire contents of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a semiconductor module. Specifically, the invention relates to a semiconductor module including a plurality of semiconductor chips.
- 2. Description of the Related Art
- A DC-DC converter for use in synchronous rectification or the like is known.
-
FIG. 14 schematically shows a commonly-used circuit of the above DC-DC converter. As shown inFIG. 14 , a capacitor Cin is connected between an input terminal Vin to which an input voltage is applied and a ground. The input terminal Vin is connected to the drain of an N-type MIS (metal insulator semiconductor) transistor Q1 whose channel (current path) is of an N type. The MIS transistor includes a MOS (metal oxide semiconductor) transistor. The gate of the MIS transistor Q1 is connected to an IC for DC-DC conversion. The MIS transistor Q1 functions as a switching device. - The source of the MIS transistor Q1 is connected to the drain of an N-type MIS transistor Q2. The source of the MIS transistor Q2 is connected to the ground and the gate thereof is connected to the IC.
- A connection node N1 between the source of the MIS transistor Q1 and the drain of the MIS transistor Q2 is connected to the cathode of a diode D1. The anode of the diode D1 is connected to the ground. The connection node N1 is connected to an output terminal Vout via an inductance L. A capacitor Cout is connected in parallel between the output terminal Vout and the ground. RL indicates a load resistance.
- In the foregoing circuit, the MIS transistor Q1 is implemented by a
single semiconductor chip 41 and the MIS transistor Q2 is done by asingle semiconductor chip 42. Each of the MIS transistors has a known vertical structure as shown inFIG. 15 . In this structure, a drain electrode is formed on the bottom of each of the semiconductor chips 41 and 42. InFIG. 15 , reference symbols S, D and G denote a source, a drain and a gate, respectively. -
FIG. 16A schematically shows an outward appearance of a semiconductor module havingsemiconductor chips FIG. 16B schematically shows an internal structure of the semiconductor module. The first prior is shown taking a known SOP-8 package as an example. InFIG. 16A ,reference numeral 43 indicates a package (envelope) andreference numeral 44 denotes an external connecting terminal part of which is exposed to the semiconductor module. Referring toFIG. 16B , thesemiconductor chip FIG. 15 , is mounted on aconductive frame 45 such that the bottom of thechip frame 45. Theframe 45 is connected to theexternal connecting terminal 44, and thesemiconductor chip external connecting terminal 44 through awire 46. - As described above, the bottom of the
semiconductor chip FIG. 14 . For this reason, it is impossible to mount thesemiconductor chips frame 45 with the frame serving as a common potential. Under present circumstances, thesemiconductor chips - It has recently been desired that electronic components such as semiconductor modules be decreased in number and size and increased in operation speed in accordance with miniaturization and high-speed operation of electronic equipment using the above semiconductor modules. To seal the semiconductor chips with separate packages as in the first prior art described above is however contrary to a reduction in component count. The number of wires should be decreased to operate the electronic equipment at high speed. In the first prior art, however, the two semiconductor modules have to be connected to each other by a wire, which prevents the high-speed operation.
-
FIG. 17 schematically shows the interior of a semiconductor module according to second prior art in order to describe a method of packaging semiconductor chips. Referring toFIG. 17 , in the second prior art, twoframes 45 are provided andsemiconductor chips frames 45, respectively. Theframes 45 are connected to thesemiconductor chips FIG. 14 . By doing so, a single semiconductor module can be obtained; however, given wiring is required inside or outside the semiconductor module and the semiconductor module cannot operate at high speed. Since, moreover, an interval Z between theframes 45 depends upon the power supply voltage or the potential of each of the frames, it cannot be set to not larger than a given value, thus imposing restrictions on miniaturization of the semiconductor module. - According to a first aspect of the present invention, there is provided a semiconductor module comprising: a supporting substrate having a first major surface and a conductive connecting section, the connecting section being formed on the first major surface; a first semiconductor chip including a first MIS transistor of a first conductivity type and provided on the supporting substrate, a source of the first MIS transistor being formed on a bottom of the first MIS transistor and connected to the connecting section; a second semiconductor chip including a second MIS transistor of the first conductivity type and provided on the supporting substrate, a drain of the second transistor being formed on a bottom of the second MIS transistor and connected to the connecting section, and the drain of the second MIS transistor being electrically connected to the source of the first MIS transistor through the connecting section; an IC chip provided on the first major surface of the supporting substrate, the IC chip being connected to both a gate of the first MIS transistor and a gate of the second MIS transistor; an insulative envelope which covers the supporting substrate, the first semiconductor chip, the second semiconductor chip, and the IC chip; and connecting terminals electrically connected to the connecting section, the first semiconductor chip, and the second semiconductor chip, connecting terminals being partly exposed from the envelope.
- According to a second aspect of the present invention, there is provided a semiconductor module comprising: a supporting substrate having a first major surface and a second major surface opposed to the first major surface and including a conductive connecting section, the connecting section being formed on the first major surface; a first semiconductor chip including a first MIS transistor of a first conductivity type and provided on the supporting substrate, a source of the first MIS transistor being formed on a bottom of the first MIS transistor and connected to the connecting section; a second semiconductor chip including a second MIS transistor of the first conductivity type and provided on the supporting substrate, a drain of the second MIS transistor being formed on a bottom of the second MIS transistor and connected to the connecting section, and the drain of the second MIS transistor being electrically connected to the source of the first MIS transistor through the connecting section; an insulative envelope which covers the supporting substrate, the first semiconductor chip, and the second semiconductor chip, the envelope having an opening through which the second major surface is partly exposed; and a connecting terminals electrically connected to the connecting section, the first semiconductor chip, and the second semiconductor chip, connecting terminals being partly exposed from the envelope.
-
FIG. 1 is a cross-sectional view schematically showing an example of a lateral MIS transistor structure; -
FIG. 2 is a schematic view of the interior of a semiconductor module according to a first embodiment of the present invention; -
FIG. 3 is a cross-sectional view schematically showing a semiconductor chip of a semiconductor module according to a first modification to the first embodiment of the present invention; -
FIG. 4 is a cross-sectional view schematically showing a semiconductor chip of a semiconductor module according to a second modification to the first embodiment of the present invention; -
FIG. 5 is a schematic view of the interior of a semiconductor module according to a third modification to the first embodiment of the present invention; -
FIG. 6 is a schematic view of the underside of a semiconductor module according to second prior art; -
FIGS. 7A and 7B are schematic views of the underside of a semiconductor module according to a second embodiment of the present invention; -
FIG. 8 is a schematic view of the interior of a semiconductor module according to a third embodiment of the present invention; -
FIG. 9 is a schematic view of the interior of a semiconductor module according to a modification to the third embodiment of the present invention; -
FIG. 10 is a circuit diagram showing a multi-phased circuit of a DC-DC converter as shown inFIG. 14 ; -
FIG. 11 is a schematic view of the interior of a semiconductor module according to a fourth embodiment of the present invention; -
FIG. 12 is a schematic view of the interior of a semiconductor module according to a modification to the fourth embodiment of the present invention; -
FIG. 13 is a circuit diagram showing an example of a DC-DC converter; -
FIG. 14 is a circuit diagram of a commonly-used DC-DC converter; -
FIG. 15 is a cross-sectional view schematically showing an example of a vertical MIS transistor structure; -
FIGS. 16A and 16B are schematic views of a semiconductor module according to first prior art; and -
FIG. 17 is a schematic view of a semiconductor module according to second prior art to describe a method of packaging semiconductor chips. - An MIS transistor having a so-called lateral structure is known.
FIG. 1 schematically shows a section of an example of the lateral structure. Referring toFIG. 1 , a p-type epitaxial layer 2 is formed on a p-type semiconductor substrate 1 by, e.g., epitaxial growth. An n-type layer 3 is formed on the surface of the p-type epitaxial layer 2 by, e.g., ion implantation and an n+-type layer 4 is formed in the n-type layer 3. The concentration of the n+-type layer 4 is higher than that of the n-type layer 3. A p-type layer 5 is formed at either end of the n-type layer 3 in the p-type epitaxial layer 2, and n+-type layers 6 are formed in the p-type layer 5 at a given interval. A p+-type layer 7 is formed so as to reach thesemiconductor substrate 1 from the n+-type layers 6. - A
wiring layer 11 made of conductive materials is formed on the p-type epitaxial layer 2 and over the n+-type layer 4. Adrain electrode 12 is formed above the n+-type layer 4. Thewiring layer 11 connects thedrain electrode 12 and the n+-type layer 4. Agate electrode 13 is formed on the p-type epitaxial layer 2 and between the n-type layer 3 and one of the n+-type layers 6. Thewiring layer 11 andgate electrode 13 are insulated from each other by aninterlayer insulation film 14. Acontact layer 15 is formed on the p-type epitaxial layer 2 and between the n+-type layers 6 in the p-type layer 5. Thecontact layer 15 is electrically connected to asource electrode 16, which is formed on the entire bottom of thesemiconductor substrate 1, through the p+-type layer 7. The above MIS transistor structure is taken as one example. Another type of MIS transistor can be provided if it has only to be so configured that a source electrode is formed on the bottom of the semiconductor substrate. - Embodiments of the present invention, which employ the above-described lateral MIS transistor, will now be described with reference to the accompanying drawings. The components having substantially the same function and structure are denoted by the same reference numerals and they will be described only when the need arises.
- (First Embodiment)
-
FIG. 2 schematically shows the interior of a semiconductor module according to a first embodiment of the present invention. Since the outward appearance of the semiconductor module is the same as that of the module shown inFIG. 16A , its descriptions are omitted. InFIG. 2 ,reference numeral 21 indicates a frame (supporting substrate) of given size. Theframe 21 is made of, e.g., conductive materials. A connectingsection 21 a such as a conductive wiring pattern can be formed on an insulative substrate having good thermal conduction. In this case, semiconductor chips (described later) are connected to each other through the connectingsection 21 a, and the connectingsection 21 a is electrically connected to an external connecting terminal. The connectingsection 21 a can be provided on the entire surface of theframe 21. - A
semiconductor chip 22 is mounted on theframe 21 and has an N-type lateral MIS transistor structure as shown inFIG. 1 . In other words, a source is formed on the bottom of thesemiconductor chip 22 and contacts theframe 21. Thesemiconductor chip 22 has a function of the MIS transistor Q1 as a switching device of the DC-DC converter illustrated inFIG. 14 . - A
semiconductor chip 23 is mounted on theframe 21 at a given distance from thesemiconductor chip 22. Thesemiconductor chip 23 has a diode structure whose bottom serves as a cathode that contacts theframe 21. Thesemiconductor chip 23 has a function of the diode D1 of the DC-DC converter shown inFIG. 14 . - A
semiconductor chip 24 is mounted on theframe 21 at a given distance from thesemiconductor chip 23. Thesemiconductor chip 23 has an N-type vertical MIS transistor structure as shown inFIG. 15 . In other words, a drain is formed on the bottom of thesemiconductor chip 24 and contacts theframe 21. - The terminal of the
semiconductor chip 23, which serves as an anode, is connected to an external connectingterminal 44 of thechip 24, which corresponds to that shown inFIG. 16A , through awire 31. Thesemiconductor chip 22,semiconductor substrate 23 andsemiconductor chip 24 are electrically connected to each other with theframe 21 as a common potential. Both a drain and a gate provided on the top of thesemiconductor chip 22 are connected to given external connectingterminals 44 throughwires 31, as are both a source and a gate provided on the top of thesemiconductor chip 24. - The
frame 21 is connected to the external connectingterminals 44. Theframe 21,semiconductor chips terminals 44 are sealed with a package to form a semiconductor module. - In the first embodiment, the diode D1 of the circuit shown in
FIG. 14 is arranged on theframe 21 as an independent semiconductor chip. However, the first embodiment is not limited to this arrangement. For example, the diode D1 can be formed within thesemiconductor chip 24 of the vertical MIS transistor structure.FIG. 3 schematically shows a section of a semiconductor chip according to a first modification to the first embodiment of the present invention. The semiconductor chip shown inFIG. 3 includes adiode 33 such as a Schottky barrier diode as well as anMIS transistor 34. InFIG. 3 ,reference numeral 35 denotes barrier metal. The cathode C of thediode 33 serves as the drain D of theMIS transistor 34, too. Using a semiconductor chip of such a structure, the number of semiconductor chips can be decreased more than when the diode D1 serves as an independent semiconductor chip. - The diode D1 can also be formed within the
semiconductor chip 22 of the lateral MIS transistor structure.FIG. 4 schematically shows a section of a semiconductor chip according to a second modification to the first embodiment of the present invention. Referring toFIG. 4 , in a diode-forming region (diode) 37, an anode electrode A is formed on an n-type well layer 36 with thebarrier metal 35 interposed therebetween. Acathode 15 of thediode 37 is provided so that an oxide silicon film 38 is provided between the anode electrode A and thecathode 15. Thecathode 15 also serves as the source S of theMIS transistor 34. This cathode/source 15 is connected to a cathode/source electrode 16 through a connectinglayer 39. Using a semiconductor chip of such a structure, the number of semiconductor chips can be reduced further as in the first modification. - An IC chip of the DC-DC converter shown in
FIG. 14 can be included in the semiconductor module.FIG. 5 schematically shows the interior of a semiconductor module according to a third modification to the first embodiment of the present invention. Referring toFIG. 5 , anIC chip 40 can be mounted on theframe 21 with insulating materials (not shown) interposed therebetween. The IC chip is connected to the external connecting terminals andsemiconductor chips 22 to 24 through thewires 31. With such a semiconductor module, the number of semiconductor modules can be decreased more than when theIC chip 40 serves as an independent semiconductor module. - In
FIG. 2 , the semiconductor chips 22 and 23 are arranged on the left side of theframe 21 and thesemiconductor chip 24 is arranged on the right side thereof. The first embodiment is not limited to this arrangement. These semiconductor chips have only to be arranged such that theframe 21 serves as their common potential. It is needless to say that the position of theIC chip 40 is not limited to that shown inFIG. 5 . - The first embodiment of the present invention is directed to a semiconductor module used for composing a circuit having two MIS transistors and using a source of one of the MIS transistors and a drain of the other as potentials common to the MIS transistors. In this semiconductor module, both the
semiconductor chip 22 of an MIS transistor structure whose bottom serves as a source and thesemiconductor chip 24 of an MIS transistor structure whose bottom serves as a drain are arranged on thesingle frame 21. The total number of semiconductor modules is therefore smaller than that in the first prior art. Electronic equipment including such a semiconductor module can be decreased in size. Since the space, which would be necessary between frames in the second prior art, need not be formed, the semiconductor module can be decreased in size more than that of the second prior art. - In the first embodiment, a semiconductor module need not be provided for each MIS transistor. The semiconductor modules need not be connected by, e.g., a wire unlike in the first prior art or the frames need not be connected by, e.g., a wire inside or outside a semiconductor module unlike in the second prior art. Resistance and inductance caused by the wire can thus be eliminated; accordingly, the semiconductor modules can be operated with stability and at high speed.
- A plurality of semiconductor chips can be mounted on a single frame. It is thus unnecessary to take into consideration the coplanarity of the frame when the semiconductor chips are mounted on the frame.
- Since two frames need not be provided within a semiconductor module unlike in the second prior art, the area of the
frame 21 can be increased. Heat can thus be dispersed more effectively than that in the second prior art. Since heat moves through theframe 21, it can be uniformed on the frame. Assume that the maximum assurance temperature of one of the semiconductor chips (e.g., semiconductor chip 22) is 150° C. If, in this case, the power loss of thesemiconductor chip 22 increases and the temperatures of the semiconductor chips 22 and 24 reach 160° C. and 110° C., respectively, then the semiconductor module becomes unworkable. According to the first embodiment, however, heat generated from thesemiconductor chip 22 can be moved to thesemiconductor chip 24 and uniformed on theframe 21. Consequently, the possibility that the temperature of each of the semiconductor chips exceeds the maximum assurance temperature can be decreased. - (Second Embodiment)
- The second embodiment is a modification to the first embodiment. In the semiconductor module of the second prior art, too, a radiation effect can be improved by exposing each of
frames 45 to the underside of a package as shown inFIG. 6 . Since, however, the number offrames 45 is two or more, the coplanarity of each of theframes 45 has to be considered in the manufacturing process of the semiconductor module. Poor coplanarity decreases the radiation effect of each of theframes 45 and causes trouble when the semiconductor module is mounted on a mounting substrate or the like. In the second embodiment, therefore, a frame, which is common to the two semiconductor chips in the semiconductor module of the first embodiment, is exposed to the underside of the package. -
FIGS. 7A and 7B are plan views schematically showing the underside of a semiconductor module according to the second embodiment of the present invention. Referring toFIG. 7A , an opening is formed in the underside of apackage 43 and part of aframe 21 is exposed through the opening. Referring toFIG. 7B , theframe 21 can be formed integrally with external connectingterminals 44 as one component and exposed to thepackage 43. In this case, the area of the exposed part of theframe 21 can be increased. Theframe 21 and external connectingterminals 44 can be connected inside thepackage 43 as shown inFIG. 7A or outside thepackage 43 as shown inFIG. 7B . Since the other structure is the same as that of the first embodiment, its descriptions are omitted. - The semiconductor module according to the second embodiment produces the same advantage as that of the semiconductor module according to the first embodiment. Further, since part of the
frame 21 common to the semiconductor chips is exposed to the underside of thepackage 43, the area of the exposed part can be increased; accordingly, the radiation effect can be made greater than that in the second prior art. - Moreover, unlike in the second prior art, a semiconductor module can be formed without considering any coplanarity of two frames. It is thus possible to prevent trouble from occurring when such a semiconductor module is mounted on a mounting substrate. Consequently, the yield of semiconductor modules can be improved and the manufacturing costs thereof can be lowered.
- (Third Embodiment)
- In the foregoing first and second embodiments, the semiconductor chips in the semiconductor module and external connecting terminals are connected by wires, respectively. In the third embodiment, some of these connections are implemented by a strap structure.
-
FIG. 8 is a plan view schematically showing the interior of apackage 43 of a semiconductor module according to the third embodiment of the present invention. Referring toFIG. 8 , asemiconductor chip 22 and an external connectingterminal 44 are connected to each other by aconductive member 32 of a planar structure or a strap structure having a given width, as are asemiconductor chip 24 and an external connectingterminal 44. Since the other structure is the same as that of the first embodiment, its descriptions are omitted. - The semiconductor module according to the third embodiment produces the same advantage as that of the first embodiment. Further, since the semiconductor chips 22 and 24 are connected to the external connecting
terminals 44 by theconductive members 32 of the strap structure, more heat can radiate from the semiconductor chips 22 and 24. Furthermore, wiring resistance and inductance can be lowered more than when they are connected bywires 31. -
FIG. 9 schematically shows the interior of a semiconductor module according to a modification to the third embodiment. AnIC chip 40 is provided in a semiconductor module. The modification produces the same advantage as that of the first embodiment. - (Fourth Embodiment)
- The first to third embodiments are directed to two semiconductor chips. In contrast, the fourth embodiment is directed to three or more semiconductor chips.
-
FIG. 10 shows a multi-phased circuit, e.g., a three-phased circuit of a DC-DC converter as shown inFIG. 14 . In the circuit shown inFIG. 10 , one master clock is divided into three to alternately operate three DC-DC converters and increase the operating frequency of the entire DC-DC converters. One DC-DC converter is made up of a transistor Q1, a transistor Q2 and a diode D1, another DC-DC converter is made up of a transistor Q3, a transistor Q4 and a diode D2, and the other DC-DC converter is made up of a transistor Q5, a transistor Q6 and a diode D3. The transistors and diodes of these DC-DC converters are connected to each other as those of the DC-DC converter shown inFIG. 14 . The other circuit arrangement is the same as that shown inFIG. 14 . -
FIG. 11 schematically shows the interior of a semiconductor module according to the fourth embodiment of the present invention. For example, in the three-phased DC-DC converter, each phase requiressemiconductor chips semiconductor chip 23 having a diode function. A single semiconductor module therefore includes the semiconductor chips 22, 23 and 24. - As illustrated in
FIG. 11 , semiconductor chips by the required number are arranged on aframe 21. Asemiconductor chip 22 having a lateral MIS transistor structure is used as a chip whose source needs to be connected to theframe 21. Avertical semiconductor chip 24 is used as a chip whose drain needs to be connected to theframe 21. Each semiconductor chip is connected to given external connectingterminals 44 bywires 31. Since the other structure is the same as that of the first embodiment, its descriptions are omitted. - The semiconductor module according to the fourth embodiment produces the same advantage as that of the first embodiment. A plurality of semiconductor chips can be provided in a single module by appropriately selecting them as ones having a lateral or vertical MIS transistor structure and using the
frame 21 as a common potential. For this reason, a switching device required for, e.g., a multi-phased DC-DC converter can be provided in a single semiconductor module. -
FIG. 12 schematically shows the interior of a semiconductor module according to a modification to the fourth embodiment. Since the semiconductor module includes anIC chip 40, the modification produces the same advantage as that of the first embodiment. - Needless to say, the techniques of the modifications to the first embodiment and those of the second and third embodiments can be applied to the modification to the fourth embodiment.
- In the first to fourth embodiments, an N-type MIS transistor is used as a switching device of the circuit shown in
FIG. 14 . The present invention is not limited to this use, but a P-type MIS transistor can be used. In other words, the first to third embodiments can be employed if the conductivity types of two MIS transistors are the same.FIG. 13 shows an example of a DC-DC converter using a P-type MIS transistor as a switching device. InFIG. 13 , reference numerals Q3 and Q4 indicate P-type MIS transistors. The source of the MIS transistor Q3 is connected to an input terminal Vin and the drain thereof is connected to a connection node N1. The source of the MIS transistor Q4 is connected to the connection node N1 and the drain thereof is grounded. The other circuit arrangement is the same as that shown inFIG. 14 . - When a P-type MIS transistor is used for a switching device, the positions of the source and drain of each of the MIS transistors Q3 and Q4 differ from those in an N-type MIS transistor. Thus, a semiconductor chip of a vertical MIS transistor structure whose bottom serves as a drain is used as a
semiconductor chip 51 including the MIS transistor Q3. Such a semiconductor chip has a structure in which the conductivity types of the semiconductor chip shown inFIG. 15 are inverted. Similarly, a semiconductor chip of a lateral MIS transistor structure whose bottom serves as a source is used as asemiconductor chip 52 including the MIS transistor Q4. Such a semiconductor chip has a structure in which the conductivity types of the semiconductor chip shown inFIG. 1 are inverted. - Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
Claims (13)
1-15. (Canceled).
16. A semiconductor module comprising:
a conductive plate having a first surface;
a first semiconductor chip including a first MIS transistor, a source electrode of the first MIS transistor being formed on a bottom of the first semiconductor chip and connected to the first surface of the conductive plate;
a second semiconductor chip including a second MIS transistor, a drain electrode of the second MIS transistor being formed on a bottom of the second semiconductor chip and connected to the first surface of the conductive plate, and the drain electrode of the second MIS transistor being electrically connected to the source electrode of the first MIS transistor through the conductive plate;
an IC chip electrically connected to both a gate electrode of the first MIS transistor formed on a top of the first semiconductor chip and a gate electrode of the second MIS transistor formed on a top of the second semiconductor chip;
an insulative envelope covering the conductive plate, the first semiconductor chip, the second semiconductor chip, and the IC chip; and
connecting terminals electrically connected to the conductive plate, the first semiconductor chip, and the second semiconductor chip, the connecting terminals being partly exposed from the envelope.
17. The semiconductor module according to claim 16 , wherein the conductive plate is a frame made of conductive material.
18. The semiconductor module according to claim 16 , wherein the IC chip makes up a DC-DC converter.
19. The semiconductor module according to claim 16 , wherein one of the connecting terminals is connected to a drain electrode which is formed on a top of the first semiconductor chip.
20. The semiconductor module according to claim 16 , wherein one of the connecting terminals is connected to a source electrode which is formed on a top of the second semiconductor chip.
21. The semiconductor module according to claim 16 , wherein the envelope has an opening through which a second surface of the conductive plate, which is opposite to the first surface, is partly exposed.
22. The semiconductor module according to claim 21 , wherein the connecting terminals are part of the conductive plate.
23. The semiconductor module according to claim 16 , wherein the connecting terminals are connected to the first semiconductor chip and the second semiconductor chip by wires.
24. The semiconductor module according to claim 23 , wherein at least one of the wires is a metal plate.
25. A DC-DC converter, comprising:
a semiconductor module, comprising:
a conductive plate having a first surface;
a first semiconductor chip including a first MIS transistor, a source electrode of the first MIS transistor being formed on a bottom of the first semiconductor chip and connected to the first surface of the conductive plate;
a second semiconductor chip including a second MIS transistor, a drain electrode of the second MIS transistor being formed on a bottom of the second semiconductor chip and connected to the first surface of the conductive plate, and the drain electrode of the second MIS transistor being electrically connected to the source electrode of the first MIS transistor through the conductive plate;
an IC chip electrically connected to both a gate electrode of the first MIS transistor formed on a top of the first semiconductor chip and a gate electrode of the second MIS transistor formed on a top of the second semiconductor chip;
an insulative envelope covering the conductive plate, the first semiconductor chip, the second semiconductor chip, and the IC chip; and
connecting terminals electrically connected to the conductive plate, the first semiconductor chip, and the second semiconductor chip, the connecting terminals being partly exposed from the envelope,
wherein a drain electrode of the first MIS transistor is provided with an input voltage of the DC-DC converter.
26. The DC-DC converter according to claim 25 , wherein a source electrode of the second MIS transistor is connected to a ground.
27. The DC-DC converter according to claim 25 , wherein the conductive plate is connected to an output terminal of the DC-DC converter via an inductance.
Priority Applications (1)
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US10/934,451 US7259459B2 (en) | 2002-05-15 | 2004-09-07 | Semiconductor module and DC-DC converter |
Applications Claiming Priority (4)
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JP2002140293A JP3993461B2 (en) | 2002-05-15 | 2002-05-15 | Semiconductor module |
JP2002-140293 | 2002-05-15 | ||
US10/438,106 US6867494B2 (en) | 2002-05-15 | 2003-05-15 | Semiconductor module |
US10/934,451 US7259459B2 (en) | 2002-05-15 | 2004-09-07 | Semiconductor module and DC-DC converter |
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US10/438,106 Continuation US6867494B2 (en) | 2002-05-15 | 2003-05-15 | Semiconductor module |
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US20050029617A1 true US20050029617A1 (en) | 2005-02-10 |
US7259459B2 US7259459B2 (en) | 2007-08-21 |
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US10/934,451 Expired - Lifetime US7259459B2 (en) | 2002-05-15 | 2004-09-07 | Semiconductor module and DC-DC converter |
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US20070063341A1 (en) * | 2005-07-01 | 2007-03-22 | King Owyang | Complete power management system implemented in a single surface mount package |
US20090174055A1 (en) * | 2000-06-09 | 2009-07-09 | Vishay-Siliconix | Leadless Semiconductor Packages |
AP2600A (en) * | 2008-07-16 | 2013-02-25 | Anadarko Petroleum Corp | Water current power generation system |
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JP3993461B2 (en) * | 2002-05-15 | 2007-10-17 | 株式会社東芝 | Semiconductor module |
JP3809168B2 (en) * | 2004-02-03 | 2006-08-16 | 株式会社東芝 | Semiconductor module |
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US20070063341A1 (en) * | 2005-07-01 | 2007-03-22 | King Owyang | Complete power management system implemented in a single surface mount package |
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AP2600A (en) * | 2008-07-16 | 2013-02-25 | Anadarko Petroleum Corp | Water current power generation system |
Also Published As
Publication number | Publication date |
---|---|
US20040026744A1 (en) | 2004-02-12 |
JP3993461B2 (en) | 2007-10-17 |
US7259459B2 (en) | 2007-08-21 |
JP2003332518A (en) | 2003-11-21 |
US6867494B2 (en) | 2005-03-15 |
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