JP2704342B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2704342B2 JP2704342B2 JP8193492A JP8193492A JP2704342B2 JP 2704342 B2 JP2704342 B2 JP 2704342B2 JP 8193492 A JP8193492 A JP 8193492A JP 8193492 A JP8193492 A JP 8193492A JP 2704342 B2 JP2704342 B2 JP 2704342B2
- Authority
- JP
- Japan
- Prior art keywords
- power semiconductor
- semiconductor device
- insulating material
- control element
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
【0001】[0001]
【産業上の利用分野】本発明は、リードフレーム上に、
電力半導体素子と制御素子とを有する半導体装置および
その製造方法に関する。BACKGROUND OF THE INVENTION The present invention relates to a lead frame,
The present invention relates to a semiconductor device having a power semiconductor element and a control element and a method for manufacturing the same.
【0002】[0002]
【従来の技術】従来、集積回路を含む半導体制御素子
(以下、制御素子という)と電力半導体素子とを組み合
わせた複合素子を有する電力半導体装置は、次のような
ものがあつた。2. Description of the Related Art Heretofore, there have been the following power semiconductor devices having a composite element in which a semiconductor control element including an integrated circuit (hereinafter, referred to as a control element) and a power semiconductor element are combined.
【0003】(従来例1)図4,5の如く、加熱したリ
ードフレーム1上にリボン状の半田5を切断したものを
付着させ、その上に電力半導体素子2を搭載し電気的に
接続する。(Conventional Example 1) As shown in FIGS. 4 and 5, a ribbon-shaped solder 5 cut on a heated lead frame 1 is adhered, and a power semiconductor element 2 is mounted thereon for electrical connection. .
【0004】その後、リードフレーム1の電力半導体素
子2に隣接して、絶縁ペースト4を塗布し、その上に制
御素子3を搭載し高温硬化させる。Thereafter, an insulating paste 4 is applied to the lead frame 1 adjacent to the power semiconductor element 2, and the control element 3 is mounted thereon and cured at a high temperature.
【0005】(従来例2)図6,7のように、半田5で
電力半導体素子2を搭載した後、片面に接着層8aの付
いた絶縁フイルム6をリードフレーム1上に付着させ、
その上に絶縁ペースト4を塗布し制御素子3をボンデイ
ングする。(Conventional example 2) As shown in FIGS. 6 and 7, after the power semiconductor element 2 is mounted with the solder 5, an insulating film 6 having an adhesive layer 8a on one side is adhered to the lead frame 1.
An insulating paste 4 is applied thereon and the control element 3 is bonded.
【0006】[0006]
【発明が解決しようとする課題】従来例1では、リード
フレーム1と制御素子3との距離が短いため、この間に
十分な絶縁が得られない。In the conventional example 1, since the distance between the lead frame 1 and the control element 3 is short, sufficient insulation cannot be obtained between them.
【0007】従来例2では、リードフレーム1と制御素
子3との間に絶縁フイルム6の厚さ分だけ距離があるた
め、高い絶縁性が得られるが、従来例1に比べ絶縁フイ
ルム6を貼り付ける工程が増える。In the conventional example 2, since the distance between the lead frame 1 and the control element 3 is equal to the thickness of the insulating film 6, a high insulating property is obtained. The number of attaching steps increases.
【0008】また、絶縁ペースト4の量により、絶縁ペ
ースト4が制御素子3の側面から上部ワイヤーボンデイ
ングエリアまではい上がつたり、制御素子3が傾いたり
してワイヤーが打てなくなる不良が発生し歩留りが低下
する。Further, depending on the amount of the insulating paste 4, the insulating paste 4 may fall from the side surface of the control element 3 to the upper wire bonding area, or the control element 3 may be inclined, and the wire may not be hit. Yield decreases.
【0009】さらに、絶縁ペースト4の厚さが一定でな
いため、制御素子3に過熱保護回路等がある場合に熱の
伝導が一定でなくなり、過熱保護温度が変動する。Further, since the thickness of the insulating paste 4 is not constant, when the control element 3 has an overheat protection circuit or the like, heat conduction is not constant, and the overheat protection temperature fluctuates.
【0010】本発明は、上記課題に鑑み、十分な絶縁を
得、製造工程数を抑え、かつ品質をよくして歩留りを向
上させ得る半導体装置およびその製造方法の提供を目的
とする。In view of the above problems, an object of the present invention is to provide a semiconductor device capable of obtaining sufficient insulation, suppressing the number of manufacturing steps, improving the quality and improving the yield, and a method of manufacturing the same.
【0011】[0011]
【課題を解決するための手段】本発明請求項1による課
題解決手段は、図1,2の如く、リードフレーム1上
に、半田5を介して電力半導体素子2が搭載され、絶縁
材7を介して制御素子3が搭載された半導体装置におい
て、前記絶縁材7は、絶縁フイルム6と、該絶縁フイル
ム6の両面に形成された樹脂接着層8a,8bとから三
層構造とされ、該樹脂接着層8a,8bは、電力半導体
素子2の半田付け時の熱によつて可塑化するよう構成さ
れたものである。According to a first aspect of the present invention, a power semiconductor element 2 is mounted on a lead frame 1 via a solder 5 as shown in FIGS. In a semiconductor device having the control element 3 mounted thereon, the insulating material 7 has a three-layer structure including an insulating film 6 and resin adhesive layers 8a and 8b formed on both surfaces of the insulating film 6. The adhesive layers 8a and 8b are configured to be plasticized by heat at the time of soldering the power semiconductor element 2.
【0012】本発明請求項2による課題解決手段は、リ
ードフレーム1上に、半田5を介して電力半導体素子2
を搭載し、絶縁材7を介して制御素子3を搭載する半導
体装置の製造方法において、前記絶縁材7として、絶縁
フイルム6と、該絶縁フイルム6の両面に形成された熱
可塑型樹脂接着層8a,8bとから三層構造のものを使
用し、該絶縁材7による制御素子3の搭載を電力半導体
素子2の搭載時の半田付けと同一工程で行なうものであ
る。According to a second aspect of the present invention, there is provided a power semiconductor element on a lead frame via a solder.
In the method of manufacturing a semiconductor device in which the control element 3 is mounted via the insulating material 7, the insulating film 6 is used as the insulating material 7 and a thermoplastic resin adhesive layer formed on both surfaces of the insulating film 6. 8a and 8b, a three-layer structure is used, and mounting of the control element 3 by the insulating material 7 is performed in the same step as soldering when mounting the power semiconductor element 2.
【0013】[0013]
【作用】上記課題解決手段において加熱したリードフレ
ーム1上に絶縁材7を付着すると、熱で絶縁材7の両面
の樹脂接着層8a,8bが溶融する。その溶融した樹脂
接着層8a,8bの上に制御素子3を搭載し、常温に冷
却して硬化し接着する。When the insulating material 7 is attached to the heated lead frame 1 in the above means for solving the problems, the resin adhesive layers 8a and 8b on both surfaces of the insulating material 7 are melted by heat. The control element 3 is mounted on the melted resin adhesive layers 8a and 8b, cooled to room temperature, cured, and adhered.
【0014】そうすると、絶縁材7の両面が高耐熱の熱
可塑型樹脂8a,8bであるため、半田5と同一工程で
行うことができる。Then, since both surfaces of the insulating material 7 are thermoplastic resins 8a and 8b having high heat resistance, the process can be performed in the same process as the solder 5.
【0015】[0015]
【実施例】図1は本発明の一実施例による電力半導体装
置の断面図、図2は電力半導体装置の平面図、図3は絶
縁テープの断面図である。1 is a sectional view of a power semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view of the power semiconductor device, and FIG. 3 is a sectional view of an insulating tape.
【0016】図示の如く、本実施例の半導体装置は、リ
ードフレーム1上に、半田5を介して搭載される電力半
導体素子2と、絶縁材7(樹脂テープ)を介して搭載さ
れる制御素子3とを備えてなる。As shown in the figure, the semiconductor device of the present embodiment has a power semiconductor element 2 mounted on a lead frame 1 via solder 5 and a control element mounted on an insulating material 7 (resin tape). 3 is provided.
【0017】前記リードフレーム1は、図2の如く、一
枚の金属板が打ち抜き加工されて、所望の配線パターン
が形成されてなる。図2中、1aはクレードル、1bは
タイバー、1cは搬送時等にリードフレーム1を支援す
るスプロケツト孔、1dは外部実装基板の実装する際の
ピン孔である。As shown in FIG. 2, the lead frame 1 is formed by stamping a single metal plate to form a desired wiring pattern. In FIG. 2, 1a is a cradle, 1b is a tie bar, 1c is a sprocket hole for supporting the lead frame 1 at the time of transportation or the like, and 1d is a pin hole for mounting an external mounting board.
【0018】前記絶縁材7は、図1の如く、ベースとな
る耐熱樹脂製の絶縁フイルム6と、該絶縁フイルム6の
両面に形成された熱可塑性樹脂接着層8a,8bとから
三層構造とされ、供給前はテープ状に巻き取られ、供給
時に必要な寸法だけ切断される。As shown in FIG. 1, the insulating material 7 has a three-layer structure comprising an insulating film 6 made of a heat-resistant resin serving as a base and thermoplastic resin adhesive layers 8a and 8b formed on both surfaces of the insulating film 6. Before supply, the tape is wound into a tape shape and cut to a required size at the time of supply.
【0019】上記構成の半導体装置は、次のように製造
される。The semiconductor device having the above configuration is manufactured as follows.
【0020】まず、リードフレーム1を半田5および樹
脂接着層8a,8bが溶融する温度に加熱する。First, the lead frame 1 is heated to a temperature at which the solder 5 and the resin adhesive layers 8a and 8b melt.
【0021】次に、半田5および絶縁材7を、対応する
素子2,3の大きさに併せて切断し、リードフレーム1
上の所定の場所に付着させる。Next, the solder 5 and the insulating material 7 are cut in accordance with the sizes of the corresponding elements 2 and 3, and the lead frame 1 is cut.
Attach it to the specified place above.
【0022】そして、半田5および絶縁材7の両面の樹
脂接着層8a,8bを溶融させた後、電力半導体素子2
および制御素子3を半田5および絶縁材7上に夫々搭載
する。Then, after melting the resin adhesive layers 8a and 8b on both sides of the solder 5 and the insulating material 7, the power semiconductor element 2
The control element 3 is mounted on the solder 5 and the insulating material 7, respectively.
【0023】しかる後、リードフレーム1を常温に冷却
し、半田5および樹脂接着層8a,8bを硬化接着させ
る。Thereafter, the lead frame 1 is cooled to room temperature, and the solder 5 and the resin adhesive layers 8a and 8b are cured and bonded.
【0024】これによつて、半田5および絶縁材7を同
一工程でボンデイングできる。Thus, the solder 5 and the insulating material 7 can be bonded in the same step.
【0025】しかも、絶縁材7および樹脂厚が一定であ
るためにリードフレーム1と制御素子3との間の絶縁距
離が一定となる。Moreover, since the insulating material 7 and the resin thickness are constant, the insulating distance between the lead frame 1 and the control element 3 is constant.
【0026】さらに、制御素子3上部のボンデイングエ
リアまで樹脂接着層8a,8bがはい上がるのを考慮す
る必要がない。Further, it is not necessary to consider that the resin adhesive layers 8a and 8b go up to the bonding area above the control element 3.
【0027】なお、本発明は、上記実施例に限定される
ものではなく、本発明の範囲内で上記実施例に多くの修
正および変更を加え得ることは勿論である。It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that many modifications and changes can be made to the above-described embodiment within the scope of the present invention.
【0028】[0028]
【発明の効果】以上の説明から明らかな通り、本発明に
よると、絶縁材を、絶縁フイルムとその両面の熱可塑型
樹脂接着層とから三層構造としているので、電力半導体
装置と制御素子とを同一工程にてボンデイングできるの
で工程短縮になる。As is apparent from the above description, according to the present invention, the insulating material has a three-layer structure composed of the insulating film and the thermoplastic resin adhesive layers on both surfaces thereof, so that the power semiconductor device and the control element can be used. Can be bonded in the same process, so that the process can be shortened.
【0029】また、絶縁材の厚みが一定であるため、こ
の厚みを適正に設定しておきさえすれば、制御素子の傾
きや樹脂のはい上がりなどでワイヤーボンデイングがで
きなくなるのを防止できる。Further, since the thickness of the insulating material is constant, it is possible to prevent the wire bonding from being disabled due to the inclination of the control element or the rising of the resin, if the thickness is properly set.
【0030】さらに、制御素子とリードフレームとの距
離のばらつきによる加熱保護温度のばらつきがなくなり
信頼性の高い半導体装置を提供できるといつた優れた効
果がある。Further, there is an excellent effect that a semiconductor device having high reliability can be provided without the variation in the heating protection temperature due to the variation in the distance between the control element and the lead frame.
【図1】本発明の一実施例による電力半導体装置の断面
図FIG. 1 is a sectional view of a power semiconductor device according to an embodiment of the present invention.
【図2】電力半導体装置の平面図FIG. 2 is a plan view of a power semiconductor device.
【図3】絶縁テープの断面図FIG. 3 is a sectional view of an insulating tape.
【図4】従来例1の電力半導体装置の断面図FIG. 4 is a cross-sectional view of a power semiconductor device of Conventional Example 1.
【図5】従来例1の電力半導体装置の平面図FIG. 5 is a plan view of a power semiconductor device of Conventional Example 1.
【図6】従来例2の電力半導体装置の断面図FIG. 6 is a cross-sectional view of a power semiconductor device of Conventional Example 2.
【図7】従来例2の電力半導体装置の平面図FIG. 7 is a plan view of a power semiconductor device of Conventional Example 2.
1 リードフレーム 2 電力半導体装置 3 制御素子 4 絶縁ペースト 5 半田 6 絶縁フイルム 7 絶縁材 8 熱可塑型樹脂接着層 DESCRIPTION OF SYMBOLS 1 Lead frame 2 Power semiconductor device 3 Control element 4 Insulating paste 5 Solder 6 Insulating film 7 Insulating material 8 Thermoplastic resin adhesive layer
Claims (2)
半導体素子が搭載され、絶縁材を介して制御素子が搭載
された半導体装置において、前記絶縁材は、絶縁フイル
ムと、該絶縁フイルムの両面に形成された樹脂接着層と
から三層構造とされ、該樹脂接着層は、電力半導体素子
の半田付け時の熱によつて可塑化するよう構成されたこ
とを特徴とする半導体装置。1. A semiconductor device in which a power semiconductor element is mounted on a lead frame via solder and a control element is mounted via an insulating material, wherein the insulating material includes an insulating film and both surfaces of the insulating film. And a resin adhesive layer formed on the power semiconductor element, the resin adhesive layer being plasticized by heat during soldering of the power semiconductor element.
半導体素子を搭載し、絶縁材を介して制御素子を搭載す
る半導体装置の製造方法において、前記絶縁材として、
絶縁フイルムと、該絶縁フイルムの両面に形成された熱
可塑型樹脂接着層とから三層構造のものを使用し、該絶
縁材による制御素子の搭載を電力半導体素子の搭載時の
半田付けと同一工程で行なうことを特徴とする半導体装
置の製造方法。2. A method of manufacturing a semiconductor device in which a power semiconductor element is mounted on a lead frame via solder and a control element is mounted via an insulating material, wherein the insulating material is
Using a three-layer structure of an insulating film and a thermoplastic resin adhesive layer formed on both sides of the insulating film, mounting the control element using the insulating material is the same as soldering when mounting the power semiconductor element. A method of manufacturing a semiconductor device, which is performed in a process.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8193492A JP2704342B2 (en) | 1992-04-03 | 1992-04-03 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8193492A JP2704342B2 (en) | 1992-04-03 | 1992-04-03 | Semiconductor device and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05283448A JPH05283448A (en) | 1993-10-29 |
JP2704342B2 true JP2704342B2 (en) | 1998-01-26 |
Family
ID=13760316
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8193492A Expired - Fee Related JP2704342B2 (en) | 1992-04-03 | 1992-04-03 | Semiconductor device and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2704342B2 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100335481B1 (en) * | 1999-09-13 | 2002-05-04 | 김덕중 | Power device having multi-chip package structure |
JP3993461B2 (en) | 2002-05-15 | 2007-10-17 | 株式会社東芝 | Semiconductor module |
JP5132407B2 (en) * | 2008-04-25 | 2013-01-30 | オンセミコンダクター・トレーディング・リミテッド | Semiconductor device |
JP2013214596A (en) * | 2012-04-02 | 2013-10-17 | Sumitomo Electric Ind Ltd | Semiconductor device |
JP6538396B2 (en) * | 2015-03-27 | 2019-07-03 | 株式会社ジェイデバイス | Semiconductor device |
DE112021004644T5 (en) * | 2020-10-02 | 2023-06-29 | Rohm Co., Ltd. | SEMICONDUCTOR COMPONENT |
WO2023095745A1 (en) * | 2021-11-25 | 2023-06-01 | ローム株式会社 | Semiconductor device |
-
1992
- 1992-04-03 JP JP8193492A patent/JP2704342B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH05283448A (en) | 1993-10-29 |
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