CN102447383B - Semiconductor component of integration converter and packaging structure thereof - Google Patents

Semiconductor component of integration converter and packaging structure thereof Download PDF

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Publication number
CN102447383B
CN102447383B CN201010509457.7A CN201010509457A CN102447383B CN 102447383 B CN102447383 B CN 102447383B CN 201010509457 A CN201010509457 A CN 201010509457A CN 102447383 B CN102447383 B CN 102447383B
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assembly
high side
lead foot
semiconductor
doping region
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CN102447383A (en
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林伟捷
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Sinopower Semiconductor Inc
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Sinopower Semiconductor Inc
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a semiconductor component which comprises a semiconductor substrate with a first conduction type, at least one high side transistor component and at least one low side transistor component. The high side transistor component comprises a high side substrate doping region with a second conduction type, a high side source electrode doping region with the first conduction type and a drain electrode doping region with the first conduction type. The high side substrate doping region is arranged in the semiconductor substrate, and the high side source electrode doping region and the drain electrode doping region are arranged in the high side substrate doping region. The high side source electrode doping region is electrically connected with the semiconductor substrate, and the semiconductor substrate serves as a drain electrode of the low side transistor component. Therefore, the size of the high side transistor component and the low side transistor component can be increased, and further the power consumption of power conversion is reduced.

Description

Integrate semiconductor subassembly and the encapsulating structure thereof of transducer
Technical field
The present invention relates to a kind of semiconductor subassembly and encapsulating structure thereof, espespecially a kind of semiconductor subassembly and encapsulating structure thereof of integrating transducer.
Background technology
Electronic installation includes different assemblies conventionally, and the required operating voltage of each assembly may be all different.Therefore, in electronic installation, need to be by direct current to DC voltage converting circuit, reach the adjusting (boosting or step-down) of voltage quasi position, and make it to be stabilized in the voltage value setting.According to different power supply requirements, can be extended out the DC-DC voltage converter of many different kenels, but it all stems from buck-converter (Buck/Step Down Converter) and voltage-boosting converter (Boost/Step Up Converter).
Known step-down controller is made up of high side N-type metal oxide semiconductcor field effect transistor (high side NMOSFET) assembly and a downside N-type metal oxide semiconductcor field effect transistor (low side NMOSFET) assembly.And, for high side NMOSFET assembly and downside NMOSFET assembly can be electrically connected on circuit board, generally need be packaged in same encapsulating structure.
Please refer to Fig. 1, Fig. 1 is known step-down controller encapsulating structure schematic diagram.As shown in Figure 1, known step-down controller encapsulating structure 10 comprises a lead frame 12, a high side NMOSFET assembly 14, a downside NMOSFET assembly 16, a Schottky diode (Schottky diode) 18 and a packing colloid 20.Lead frame 12 comprises one first lead foot 12a, one second lead foot 12b, one the 3rd lead foot 12c, one the 4th lead foot 12d, one the 5th lead foot 12e, one the 6th lead foot 12f, one the 7th lead foot 12g, one the 8th lead foot 12h, one first chip bearing 12i and one second chip bearing 12j.The first lead foot 12a and the second lead foot 12b and the first chip bearing 12i link together, and the 5th lead foot 12e, the 6th lead foot 12f and the 7th lead foot 12g and the second chip bearing 12j link together.High side NMOSFET assembly 14 is located on the first chip bearing 12i, make the drain electrode of high side NMOSFET assembly 14 be electrically connected to the first chip bearing 12i, and the source electrode 14b of high side NMOSFET assembly 14 and grid 14c are electrically connected to the 7th lead foot 12g and the 8th lead foot 12h by gold thread 22 respectively.In addition, downside NMOSFET assembly 16 is located on the second chip bearing 12j with Schottky diode 18, make the drain electrode of downside NMOSFET assembly 16 and the N-type end of Schottky diode 18 be electrically connected to the second chip bearing 12j, and the source electrode 16b of downside NMOSFET assembly 16 is electrically connected P type end and the 4th lead foot 12d of Schottky diode 18 by gold thread 22, the grid 16c of downside NMOSFET assembly 16 is electrically connected to the 3rd lead foot 12c by gold thread 22.Therefore, the first lead foot 12a and the second lead foot 12b represent the drain electrode of high side NMOSFET assembly 14, and the 3rd lead foot 12c represents the grid 16c of downside NMOSFET assembly 16.The 4th lead foot 12d represents the source electrode 16b of downside NMOSFET assembly 16, and the 5th lead foot 12e, the 6th lead foot 12f and the 7th lead foot 12g represent the drain electrode of source electrode 14b and the downside NMOSFET assembly 16 of high side NMOSFET assembly 14.The 8th lead foot 12h represents the grid 14c of high side NMOSFET assembly 14.
In known step-down controller encapsulating structure 10, because the drain electrode of high side NMOSFET assembly 14 and the drain electrode of downside NMOSFET assembly 16 are all positioned at the lower surface of assembly chip, therefore lead frame 12 need have the first chip bearing 12i and the second chip bearing 12j of electrical isolation each other, in order to high side NMOSFET assembly 14 and downside NMOSFET assembly 16 to be set respectively, just can avoid the drain electrode of high side NMOSFET assembly 14 and the drain electrode of downside NMOSFET assembly 16 to be electrically connected.Thus, between the first chip bearing 12i and the second chip bearing 12j, need to have the gap of certain distance, be generally 250 microns, and the width at high side NMOSFET assembly 14 distance the first chip bearing 12i edges and the width at downside NMOSFET assembly 16 distance the second chip bearing 12j edges all also must be approximately slightly 250 microns, to avoid in the time that high side NMOSFET assembly 14 is set with downside NMOSFET assembly 16, high side NMOSFET assembly 14 exceeds respectively the first chip bearing 12i and the second chip bearing 12j with the position of downside NMOSFET assembly 16.
Hence one can see that, and high side NMOSFET assembly 14 at least needs 750 microns with the spacing of downside NMOSFET assembly 16.In the time of fixing encapsulating structure big or small, the size of high side NMOSFET assembly 14 and downside NMOSFET assembly 16 thereby can thereupon be locked.Whereby, the opening resistor between the drain electrode of high side NMOSFET assembly 14 and source electrode 14b and between drain electrode and the source electrode 16b of downside NMOSFET assembly 16 can be subject to dwindling and corresponding increase of assembly chip, and then increases the power loss of voltage transitions.
And, in known step-down controller encapsulating structure 10, the source electrode 14b of high side NMOSFET assembly 14 is electrically connected to the drain electrode of downside NMOSFET assembly 16, therefore in order to reach this object, known step-down controller encapsulating structure 10 must utilize gold thread that the source electrode 14b of high side NMOSFET assembly 14 is electrically connected to the 7th lead foot 12g, and link together by the 7th lead foot 12g and the second chip bearing 12j, just can make the source electrode 14b of high side NMOSFET assembly 14 be electrically connected to the drain electrode of downside NMOSFET assembly 16.Therefore, the resistance between the source electrode 14b of high side NMOSFET assembly 14 and the drain electrode of downside NMOSFET assembly 16 also can be subject to the restriction of bang path, thereby also causes the power loss of voltage transitions.
Therefore, reduce the power loss producing in the encapsulating structure of known step-down controller in fact for industry is done one's utmost the target of improving.
Summary of the invention
Main purpose of the present invention is to provide a kind of semiconductor subassembly and encapsulating structure thereof of integrating transducer, to reduce the power loss being produced in the encapsulating structure of transducer.
In order to achieve the above object, the invention provides a kind of semiconductor subassembly of integrating transducer.Semiconductor subassembly comprises semiconductor substrate, at least one high-side transistor assembly, a high side drain metal layer, a high side gate metal layer, a common metal level, at least one low side transistors assembly, a downside source metal, a lowside gate metal level and one first interlayer dielectric layer.Semiconductor base definition has a high-side transistor assembly district and a low side transistors assembly district, and semiconductor base has one first conduction type.High-side transistor assembly is located in high-side transistor assembly district, and high-side transistor assembly comprises a high side group body doped region, a light drain doping region, a drain doping region, a high side source doping region and a high side grid conducting layer.High side group body doped region is located in the semiconductor base in high-side transistor assembly district, and high side group body doped region has one second conduction type.Light drain doping region is located in high side group body doped region, and light drain doping region has the first conduction type.Drain doping region is located in light drain doping region, and drain doping region has the first conduction type.High side source doping region is located in the high side group body doped region of light drain doping region one side, and high side source doping region has the first conduction type.High side grid conducting layer is located on the high side group body doped region between light drain doping region and high side source doping region.High side drain metal layer is located on the semiconductor base in high-side transistor assembly district, and is electrically connected drain doping region.High side gate metal layer is located on the semiconductor base in high-side transistor assembly district, and is electrically connected paramount side grid conducting layer.Common metal level be located at semiconductor-based under, and be electrically connected high side source doping region and semiconductor base.Low side transistors assembly is located in low side transistors assembly district, and low side transistors assembly has a grid, one source pole and a drain electrode, and wherein semiconductor base is as the drain electrode of low side transistors assembly.Downside source metal is located on the semiconductor base in low side transistors assembly district, and is electrically connected the source electrode of low side transistors assembly.Lowside gate metal level is located on the semiconductor base of low side transistors assembly, and is electrically connected the grid of low side transistors assembly.The first interlayer dielectric layer is located between semiconductor base and high side drain metal layer and downside source metal.
In order to achieve the above object, the invention provides a kind of emitted semiconductor assembly package structure of integrating transducer.Emitted semiconductor assembly package structure comprises a lead frame, semiconductor assembly and a packaging body.Lead frame comprises a chip bearing, one first lead foot, one second lead foot, one the 3rd lead foot, one the 4th lead foot, one the 5th lead foot, one the 6th lead foot, one the 7th lead foot and one the 8th lead foot.Chip bearing has one first side and second side with respect to the first side.The first lead foot, the second lead foot, the 3rd lead foot and the 4th lead foot are located at the first side of chip bearing, and the 3rd lead foot and the 4th lead foot electric connection chip bearing.The 5th lead foot, the 6th lead foot, the 7th lead foot and the 8th lead foot are located at the second side of chip bearing, and the 6th lead foot is connected with the 5th lead foot, and the 8th lead foot is connected with the 7th lead foot.Semiconductor subassembly is located in chip bearing, and semiconductor subassembly comprises semiconductor substrate, at least one high-side transistor assembly, a high side drain metal layer, a high side gate metal layer, a common metal level, at least one low side transistors assembly, a downside source metal, a lowside gate metal level and one first interlayer dielectric layer.Semiconductor base definition has a high-side transistor assembly district and a low side transistors assembly district, and semiconductor base has one first conduction type.High-side transistor assembly is located in high-side transistor assembly district, and high-side transistor assembly comprises a high side group body doped region, a light drain doping region, a drain doping region, a high side source doping region and a high side grid conducting layer.High side group body doped region is located in the semiconductor base in high-side transistor assembly district, and high side group body doped region has one second conduction type.Light drain doping region is located in high side group body doped region, and light drain doping region has the first conduction type.Drain doping region is located in light drain doping region, and drain doping region has the first conduction type.High side source doping region is located in the high side group body doped region of light drain doping region one side, and high side source doping region has the first conduction type.High side grid conducting layer is located on the high side group body doped region between light drain doping region and high side source doping region.High side drain metal layer is located on the semiconductor base in high-side transistor assembly district, and is electrically connected drain doping region.High side gate metal layer is located on the semiconductor base in high-side transistor assembly district, and is electrically connected paramount side grid conducting layer.Common metal level be located at semiconductor-based under, and be electrically connected high side source doping region and semiconductor base.Low side transistors assembly is located in low side transistors assembly district, and low side transistors assembly has a grid, one source pole and a drain electrode, and wherein semiconductor base is as the drain electrode of low side transistors assembly.Downside source metal is located on the semiconductor base in low side transistors assembly district, and is electrically connected the source electrode of low side transistors assembly.Lowside gate metal level is located on the semiconductor base of low side transistors assembly, and is electrically connected the grid of low side transistors assembly.The first interlayer dielectric layer is located between semiconductor base and high side drain metal layer and downside source metal.Packaging body coats semiconductor subassembly and part lead frame.
In sum, semiconductor subassembly of the present invention is on same semiconductor base, to produce high-side transistor assembly and low side transistors assembly, make emitted semiconductor assembly package structure only need to utilize a chip bearing that semiconductor assembly is set, and the semiconductor subassembly that is arranged at chip bearing can increase the area of semiconductor base or increase the size of high-side transistor assembly and low side transistors assembly, opening resistor between the drain electrode of high-side transistor assembly and source electrode and between drain electrode and the source electrode of low side transistors assembly can be lowered whereby, and then the power loss of reduction power supply conversion.
Brief description of the drawings
Fig. 1 is the encapsulating structure schematic diagram of known step-down controller.
Fig. 2 be the semiconductor subassembly of the integration transducer of first embodiment of the invention encapsulating structure on look schematic diagram.
Fig. 3 to Fig. 7 is the manufacture method schematic diagram that first embodiment of the invention is integrated the semiconductor subassembly of transducer.
Fig. 8 is the circuit diagram of the transducer that utilizes semiconductor subassembly of the present invention to do to switch.
Fig. 9 is another enforcement aspect of the emitted semiconductor assembly package structure of first embodiment of the invention.
Figure 10 is the another enforcement aspect of the emitted semiconductor assembly package structure of first embodiment of the invention.
Figure 11 is the generalized section of the semiconductor subassembly of second embodiment of the invention.
Figure 12 be second embodiment of the invention emitted semiconductor assembly package structure on look schematic diagram.
Figure 13 be third embodiment of the invention semiconductor subassembly with and encapsulating structure on look schematic diagram.
Figure 14 be fourth embodiment of the invention emitted semiconductor assembly package structure on look schematic diagram.
Wherein, description of reference numerals is as follows:
10 step-down controller encapsulating structure 12 lead frames
12a first lead foot 12b the second lead foot
12c the 3rd lead foot 12d the 4th lead foot
12e the 5th lead foot 12f the 6th lead foot
12g the 7th lead foot 12h the 8th lead foot
12i first chip bearing 12j the second chip bearing
14 high side NMOSFET assembly 14b source electrodes
14c grid 16 downside NMOSFET assemblies
16b source electrode 16c grid
18 Schottky diode 20 packing colloids
22 gold thread 100 semiconductor subassemblies
102 semiconductor base 104 high-side transistor assemblies
106 low side transistors assembly 108 upper surfaces
110 lower surface 112 high-side transistor assembly districts
114 low side transistors assembly district 116 base materials
The high side group body of 118 epitaxial loayer 120 doped region
122 light drain doping region 124 drain doping region
126 high side source doping region 128 first insulating barriers
130 high side grid conducting layer 132 first interlayer dielectric layers
134 first contact doping district 136 first contact plungers
138 second contact plunger 140 the 3rd contact plungers
142 second contact doping district 144 grooves
146 second insulating barrier 148 lowside gate conductive layers
150 downside matrix doped region 152 downside source doping region
154 the 3rd contact doping district 156 the 4th contact plungers
The high side drain metal layer of 158 second interlayer dielectric layer 160
The high side gate metal layer of 162 high side source metal 164
166 common metal level 168 downside source metal
170 lowside gate metal level 172 matrix doped regions
174 first 176 second contact holes, contact holes
178 the 3rd the 4th contact hole, contact holes 180
182 the 5th contact the 4th contact doping districts, hole 184
186 the 5th contact plunger 200 emitted semiconductor assembly package structures
202 lead frame 202a chip bearings
202b first lead foot 202c the second lead foot
202d the 3rd lead foot 202e the 4th lead foot
202f the 5th lead foot 202g the 6th lead foot
202h the 7th lead foot 202i the 8th lead foot
204 packaging body 206 first conductive components
208 second conductive component 210 the 3rd conductive components
212 the 4th conductive component 214 the 5th conductive components
216 control assembly 218 directions
300 semiconductor subassembly 302 second interlayer dielectric layers
The high side drain metal layer of 304 second contact plunger 306
350 emitted semiconductor assembly package structures 352 the 4th conductive component
400 semiconductor subassembly 450 emitted semiconductor assembly package structures
500 semiconductor subassembly 550 emitted semiconductor assembly package structures
Vin input Vout output
L inductance D Schottky diode
C electric capacity R load resistance
Embodiment
Please refer to Fig. 2 to Fig. 4, on the encapsulating structure of the semiconductor subassembly of the integration transducer that Fig. 2 is first embodiment of the invention, look schematic diagram, Fig. 3 is the generalized section of Fig. 2 along AA ' line, and Fig. 4 is the generalized section of Fig. 2 along BB ' line.As shown in Figures 2 to 4, the semiconductor subassembly 100 of the present embodiment comprises semiconductor substrate 102, at least one high-side transistor assembly 104 and at least one low side transistors assembly 106.Semiconductor base 102 has a upper surface 108 and a lower surface 110, and upper surface 108 definition of semiconductor base 102 have a high-side transistor assembly district 112 and a low side transistors assembly district 114, wherein high-side transistor assembly 104 is arranged in high-side transistor assembly district 112, and low side transistors assembly 106 is arranged in low side transistors assembly district 114.In addition, semiconductor base 102 has one first conduction type, and first conduction type of the present embodiment is taking N-type as example, but not as limit.Semiconductor base 102 comprises a base material 116 and an epitaxial loayer 118, and wherein epitaxial loayer 118 is located on base material 116.Base material 116 can comprise the material of for example silicon substrate, and the doping content of base material 116 is higher than the doping content of epitaxial loayer 118.Because the voltage endurance capability of semiconductor subassembly 100 is along with the thickness of epitaxial loayer 118 increases and doping content reduces and increases, therefore the visual withstand voltage demand of the thickness of epitaxial loayer 118 is adjusted.
In the present embodiment, high-side transistor assembly 104 comprises a high side group body doped region 120, light drain electrode doping (light-doped drain, a LDD) district 122, a drain doping region 124, at least one high side source doping region 126, one first insulating barrier 128 and at least one high side grid conducting layer 130.High side group body doped region 120 is located in the semiconductor base 102 in high-side transistor assembly district 112, and high side group body doped region 120 has one second conduction type.Second conduction type of the present embodiment is taking P type as example, but not as limit.The first conduction type of the present invention and the second conduction type are not limit and are respectively N-type and P type, also interchangeable.Light drain doping region 122 is located in high side group body doped region 120, and light drain doping region 122 has the first conduction type.Drain doping region 124 is located in light drain doping region 122, and drain doping region 124 has the first conduction type.And light drain doping region 122 and drain doping region 124 can be used as the drain electrode of high-side transistor assembly 104.High side source doping region 126 is located in the high side group body doped region 120 of light drain doping region 122 1 sides, and high side source doping region 126 has the first conduction type.High side source doping region 126 can be used as the source electrode of high-side transistor assembly 104, and high side group body doped region 120 between light drain doping region 122 and high side source doping region 126 can be used as the channel region of high-side transistor assembly 104.The high side source doping region 126 of the present embodiment and the doping content of the doping content of drain doping region 124 higher than light drain doping region 122, and light drain doping region 122 is the high voltages that transmit from drain doping region 124 for bearing, to avoid high voltage to destroy the structure of high-side transistor assembly 104.Hence one can see that, and high-side transistor assembly 104 is a Laterally Diffused Metal Oxide Semiconductor (laterally diffused metal-oxide-semiconductor, LDMOS) assembly.In addition, the first insulating barrier 128 is covered in the upper surface 108 of semiconductor base 102, and high side grid conducting layer 130 is located on the high side group body doped region 120 between light drain doping region 122 and high side source doping region 126, using the grid as high-side transistor assembly 104.High-side transistor assembly 104 of the present invention is not limited to only have single high side source doping region 126 and single high side grid conducting layer 130, can according to the wish quantity that forms high-side transistor assembly 104 adjust the quantity of high side source doping region 126 and high side grid conducting layer 130, that is high-side transistor assembly 104 can comprise two high side source doping region 126, be located at respectively in the high side group body doped region 120 of light drain doping region 122 both sides, the present invention is not as limit.
Moreover, the semiconductor subassembly 100 of the present embodiment separately comprises one first interlayer dielectric layer 132, one first contact doping district 134, one first contact plunger 136, at least one the second contact plunger 138 and one the 3rd contact plunger 140, and high-side transistor assembly 104 separately comprises one second contact doping district 142.The first interlayer dielectric layer 132 is covered on the first insulating barrier 128.The first contact doping district 134 is located in the semiconductor base 102 of high side group body doped region 120 1 sides in high-side transistor assembly district 112, and the first contact doping district 134 has the second conduction type.The first contact plunger 136 is located in the first contact doping district 134, and runs through the first insulating barrier 128 and the first interlayer dielectric layer 132.The second contact doping district 142 is located in the high side group body doped region 120 under high side source doping region 126, and the second contact doping district 142 has the second conduction type.The second contact plunger 138 is located in the second contact doping district 142, and runs through high side source doping region 126, the first insulating barrier 128 and the first interlayer dielectric layer 132.The 3rd contact plunger 140 is positioned in light drain doping region 122, and runs through drain doping region 124, the first insulating barrier 128 and the first interlayer dielectric layer 132.
In the present embodiment, the semiconductor base 102 in low side transistors assembly district 114 has at least one groove 144.Low side transistors assembly 106 comprises one second insulating barrier 146, a lowside gate conductive layer 148, a downside matrix doped region 150, a downside source doping region 152, one the 3rd contact doping district 154 and one the 4th contact plunger 156.The second insulating barrier 146 is covered on the semiconductor base 102 in groove 144, and first insulating barrier 128 of the present embodiment and the material of the second insulating barrier 146 can comprise the dielectric layer that the materials such as such as boron-phosphorosilicate glass (BPSG) or other Si oxide form, but are not limited to this.Lowside gate conductive layer 148 is located in groove 144, and as the grid of low side transistors assembly 106.The high side grid conducting layer 130 of the present embodiment can comprise for example polycrystalline silicon material of doping with the material of lowside gate conductive layer 148, but is not limited to this.Downside matrix doped region 150 is located in the semiconductor base 102 of groove 144 1 sides in low side transistors assembly district 114, and downside matrix doped region 150 has the second conduction type.Downside source doping region 152 is located in downside matrix doped region 150, and downside source doping region 152 has the first conduction type, and as the source electrode of low side transistors assembly 106.The 3rd contact doping district 154 is located in the downside matrix doped region 150 under downside source doping region 152, and has the second conduction type.The 4th contact plunger 156 is located in the 3rd contact doping district 154, and runs through downside source doping region 152, the first insulating barrier 128 and the first interlayer dielectric layer 132.In addition, the semiconductor base 102 that is positioned at low side transistors assembly district 114 of the present embodiment is the drain electrode as low side transistors assembly 106, and the downside matrix doped region 150 of also contiguous the second insulating barrier 146 is the channel region as low side transistors assembly 106 between downside source doping region 152 and semiconductor base 102.Hence one can see that, and the low side transistors assembly 106 of the present embodiment is a groove type gold oxide-semiconductor transistor assembly, but is not limited to this.And the quantity of the groove 144 that the present invention forms is not only limit as single, also can be multiple, and can according to the wish quantity that forms low side transistors assembly do corresponding adjustment.
In addition, the semiconductor subassembly 100 of the present embodiment separately comprises one second interlayer dielectric layer 158, a high side drain metal layer 160, a high side source metal 162, a high side gate metal layer 164, a common metal level 166, a downside source metal 168 and a lowside gate metal level 170.The second interlayer dielectric layer 158 is arranged on the first interlayer dielectric layer 132, and exposes part the first contact plunger 136, part the second contact plunger 138 and part the 3rd contact plunger 140.High side drain metal layer 160 is located on the first interlayer dielectric layer 132, the second interlayer dielectric layer 158 and the 3rd contact plunger 140 in high-side transistor assembly district 112, and is electrically connected to drain doping region 124 and light drain doping region 122 by the 3rd contact plunger 140.High side source metal 162 is located on the first interlayer dielectric layer 132, the second interlayer dielectric layer 158, the first contact plunger 136 and second contact plunger 138 in high-side transistor assembly district 112, and be positioned at a side of high side drain metal layer 160, and be electrically connected to the first contact doping district 134 and epitaxial loayer 118 by the first contact plunger 136, and be electrically connected paramount side source doping region 126 and the second contact doping district 142 by the second contact plunger 138.It should be noted that, the high side drain metal layer 160 of the present embodiment and high side source metal 162 respectively with the first contact plunger 136, the second contact plunger 138 and the 3rd contact plunger 140 parts overlap, but second interlayer dielectric layer 158 of the present embodiment is not only arranged between high side drain metal layer 160 and the first contact plunger 136 and the second contact plunger 138, also be arranged between high side source metal 162 and the 3rd contact plunger 140, with the high side drain metal layer 160 of electrical isolation and the first contact plunger 136 and the second contact plunger 138, and the high side source metal 162 of electrical isolation and the 3rd contact plunger 140.Therefore, high side drain metal layer 160 can with the source electrode electrical isolation of high-side transistor assembly 104, and high side source metal 162 can with the drain electrode electrical isolation of high-side transistor assembly 104.First interlayer dielectric layer 132 of the present embodiment and the material of the second interlayer dielectric layer 158 can comprise the dielectric layer that the materials such as such as boron-phosphorosilicate glass (BPSG) or other Si oxide form, but are not limited to this.
In addition, high side gate metal layer 164 is located on first interlayer dielectric layer 132 in high-side transistor assembly district 112, and around high side drain metal layer 160 and high side source metal 162, and be electrically connected paramount side grid conducting layer 130.Common metal level 166 is located at the lower surface 110 of semiconductor base 102, can be electrically connected whereby high side source doping region 126 and semiconductor base 102.Downside source metal 168 is located on the semiconductor base 102 in low side transistors assembly district 114, and is electrically connected to downside source doping region 152 by the 4th contact plunger 156.Lowside gate metal level 170 is located on the semiconductor base 102 of low side transistors assembly 106, and is electrically connected lowside gate conductive layer 148.It should be noted that, the semiconductor subassembly 100 of the present embodiment utilizes the first contact plunger 136 that high side source metal 162 is electrically connected to as the semiconductor base 102 of the drain electrode of low side transistors assembly 106, the source electrode of high-side transistor assembly 104 can be electrically connected the drain electrode of low side transistors assembly 106 whereby, and is electrically connected to common metal level 166.
Hence one can see that, high-side transistor assembly 104 and low side transistors assembly 106 are made in same semiconductor base 102 by the semiconductor subassembly 100 of the present embodiment, and by the first contact plunger 136, the drain electrode of the source electrode of high-side transistor assembly 104 and low side transistors assembly 106 is electrically connected, make high-side transistor assembly 104 and low side transistors assembly 106 can be integrated into a transducer.
To describe below the manufacture method of the present embodiment semiconductor subassembly, and the first conduction type and the second conduction type be respectively taking N-type and P type as example, but the invention is not restricted to this.Please refer to Fig. 5 to Fig. 7, and in the lump with reference to figure 3 and Fig. 4.Fig. 3 to Fig. 7 is the manufacture method schematic diagram that first embodiment of the invention is integrated the semiconductor subassembly of transducer.As shown in Figure 5, first provide N type semiconductor substrate 102.Then, utilize a first photomask to coordinate photoetching and etch process, the upper surface 108 of the N type semiconductor substrate 102 in low side transistors assembly district 114 forms groove 144.Then, in the N type semiconductor substrate 102 in groove 144, cover the second insulating barrier 146, and in groove 144, insert lowside gate conductive layer 148.Subsequently, utilize a second photomask to coordinate photoetching and etch process, carry out a P type ion implantation technology and an injection process, the interior formation of N type semiconductor substrate 102 in the high-side transistor assembly district 112 high side group body of P type doped region 120, in the N type semiconductor substrate 102 interior formation P type downside matrix doped region 150 of groove 144 1 sides and in the semiconductor base 102 formation one P mold base doped regions 172 at edge that are positioned at low side transistors assembly district 114.Because the high side group body of P type doped region 120 and P type downside matrix doped region 150 form simultaneously, therefore there is same depth.Be used to form the ion that the ion implantation technology of P type doped region injects and comprise the such as dopant ion such as boron ion or boron fluoride ion, but not as limit.Then, utilize Yi tri-road photomasks to coordinate photoetching and etch process, carry out a N-type ion implantation technology and an injection process, in the light drain doping region 122 of the high side group body of P type doped region 120 interior formation N-type.
Then, as shown in Figure 6, utilize Yi tetra-road photomasks to coordinate photoetching and etch processs, in the high side source doping region 126 of the high side group body of the P type doped region of light drain doping region 122 1 sides of N-type 120 interior formation N-type, the interior formation N-type of the light drain doping region 122 of N-type drain doping region 124 in high-side transistor assembly district 112 and the interior formation N-type downside source doping region 152 in P type downside matrix doped region 150.Then, cover the first insulating barrier 128 in the upper surface 108 of N type semiconductor substrate 102.Then, utilize Yi five road photomasks to coordinate photoetching and etch process, on the first insulating barrier 128 between the light drain doping region 122 of N-type and the high side source doping region 126 of N-type, form high side grid conducting layer 130.
Then, as shown in Figure 7, on the first insulating barrier 128 and high side grid conducting layer 130, cover the first interlayer dielectric layer 132, and recycling Yi six road photomasks coordinate photoetching and etch process, in the first interlayer dielectric layer 132, form one first contact hole 174, at least one the second contact hole 176, one the 3rd contact hole 178, one the 4th contact hole 180 and one the 5th contact hole 182.The first interlayer dielectric layer 132 and first insulating barrier 128 in high-side transistor assembly district 112 are run through in the first contact hole 174, and expose a part for the N type semiconductor substrate 102 between high-side transistor assembly district 112 and low side transistors assembly district 114.The first interlayer dielectric layer 132, the first insulating barrier 128 and the high side source doping region 126 of N-type are run through in the second contact hole 176, and expose the high side group body of P type doped region 120.The first interlayer dielectric layer 132, the first insulating barrier 128 and N-type drain doping region 124 are run through in the 3rd contact hole 178, and expose the light drain doping region 122 of N-type.The first interlayer dielectric layer 132, the first insulating barrier 128 and the N-type downside source doping region 152 in low side transistors assembly district 114 are run through in the 4th contact hole 180, and expose P type downside matrix doped region 150.The first interlayer dielectric layer 132 and the first insulating barrier 128 are run through in the 5th contact hole 182, and expose P mold base doped region 172.Then, utilize Yi seven road photomasks to coordinate photoetching and etch process, carry out a P type ion implantation technology and an injection process, the interior formation of N type semiconductor substrate 102 the one P type contact doping district 134 exposing in the first contact hole 174, 120 interior formation the 2nd P type contact doping districts 142, the high side group body of P type doped region that expose in the second contact hole 176, 150 interior formation the 3rd P type contact doping districts 154, P type downside matrix doped region that expose in the 4th contact hole 180, and 172 interior formation 1 the 4th P type contact doping districts 184, P mold base doped region that expose in the 5th contact hole 182.Then, form the first contact plunger 136 fill up the first contact hole 174, form the second contact plunger 138 fill up the second contact hole 176, form the 3rd contact plunger 140 fill up the 3rd contact hole 178, form the 4th contact plunger 156 fill up the 4th contact hole 180 and form one the 5th contact plunger 186 fill up the 5th contact hole 182.
Then, as shown in Figure 3 and Figure 4, utilize Yi eight road photomasks to coordinate photoetching and etch process, on first interlayer dielectric layer 132 in high-side transistor assembly district 112, form one second interlayer dielectric layer 158, and the second interlayer dielectric layer 158 exposes a part for the first contact plunger 136 and the second contact plunger 138 and a part for the 3rd contact plunger 140.Then, utilize Yi nine road photomasks to coordinate photoetching and etch process, on second interlayer dielectric layer 158 in high-side transistor assembly district 112, form high side drain metal layer 160, high side source metal 162 and high side gate metal layer (not being shown in Fig. 3 and Fig. 4), and on first interlayer dielectric layer 132 in low side transistors assembly district 114, form downside source metal 168 and lowside gate metal level (not being shown in Fig. 3 and Fig. 4).Finally, then form a common metal level 166 in the lower surface 110 of N type semiconductor substrate 102, so far completed the semiconductor subassembly 100 of the integration transducer of the present embodiment.The material that the present invention forms common metal level 166, downside source metal 168, high side source metal 162 and high side drain metal layer 160 can be as metals such as aluminum bronze (AlCu), aluminium copper silicon (AlSiCu), titanium tungsten (TiW), titanium nitride (TiN), tungsten, but not as limit.
In addition, the present invention separately provides the encapsulating structure of the semiconductor subassembly of integrating transducer.Please continue to refer to Fig. 2.The emitted semiconductor assembly package structure 200 of the present embodiment comprises semiconductor subassembly 100 and a packaging body 204 of a lead frame 202, an integration transducer.Lead frame 202 comprises a chip bearing 202a, one first lead foot 202b, one second lead foot 202c, one the 3rd lead foot 202d, one the 4th lead foot 202e, one the 5th lead foot 202f, one the 6th lead foot 202g, one the 7th lead foot 202h and one the 8th lead foot 202i.Chip bearing 202a has one first side and second side with respect to the first side.The first lead foot 202b, the second lead foot 202c, the 3rd lead foot 202d and the 4th lead foot 202e are located at the first side of chip bearing 202a, and sequentially arrange along a direction 218.The 5th lead foot 202f, the 6th lead foot 202g, the 7th lead foot 202h and the 8th lead foot 202i are located at the second side of chip bearing 202a, and the 8th lead foot 202i, the 7th lead foot 202h, the 6th lead foot 202g and the 5th lead foot 202f sequentially arrange along this direction 218.And the 3rd lead foot 202d is connected with the 4th lead foot 202e, and the 7th lead foot 202h is connected with the 8th lead foot 202i.The 5th lead foot 202f is connected with the 6th lead foot 202g, and is connected with chip bearing 202a, thereby is electrically connected chip bearing 202a.In addition, it is upper that semiconductor subassembly 100 utilizes a conducting resinl to stick in chip bearing 202a, makes the common metal level of semiconductor subassembly 100 be electrically connected to chip bearing 202a, and then be electrically connected to the 5th lead foot 202f and the 6th lead foot 202g.
In the present embodiment, emitted semiconductor assembly package structure 200 separately comprises one first conductive component 206, one second conductive component 208, one the 3rd conductive component 210, one the 4th conductive component 212 and one the 5th conductive component 214.The first conductive component 206 is electrically connected respectively high side gate metal layer 164 and the first lead foot 202b, and the second conductive component 208 is electrically connected lowside gate metal level 170 and the second lead foot 202c.The 3rd conductive component 210 is electrically connected downside source metal 168 and the 3rd lead foot 202d and the 4th lead foot 202e, the 4th conductive component 212 is electrically connected high side drain metal layer 160 and the 7th lead foot 202h and the 8th lead foot 202i, and the 5th conductive component 214 is electrically connected high side source metal 162 and the 5th lead foot 202f and the 6th lead foot 202g.Therefore, the first lead foot 202b represents the grid lead foot of high-side transistor assembly 104, the second lead foot 202c represents the grid lead foot of low side transistors assembly 106, the 3rd lead foot 202d and the 4th lead foot 202e represent the source electrode lead foot of low side transistors assembly 106, the 5th lead foot 202f and the 6th lead foot 202g represent the source electrode lead foot of high-side transistor assembly 104 and the drain electrode lead foot of low side transistors assembly 106, and the 7th lead foot 202h and the 8th lead foot 202i represent the drain electrode lead foot of high-side transistor assembly 104.First conductive component 206 of the present embodiment and the second conductive component 208 are plain conductor, and its material comprises gold or copper, but is not limited to this.And the 3rd conductive component 210, the 4th conductive component 212 and the 5th conductive component 214 of the present embodiment are a sheet metal, its material comprises copper, but is not limited to this.In addition; the coated semiconductor subassembly 100 of packaging body 204, the first conductive component 206, the second conductive component 208, the 3rd conductive component 210, the 4th conductive component 212, the 5th conductive component 214 and part lead frame; in order to protect semiconductor subassembly 100, and it is destroyed to avoid semiconductor subassembly 100 to be electrically connected to the conductive component of lead frame 202.The packaging body 204 of the present embodiment can comprise the encapsulating material of for example epoxy resin, but the invention is not restricted to this.
Emitted semiconductor assembly package structure 200 that it should be noted that the present embodiment only needs to arrange semiconductor assembly 100, does not therefore need chip bearing 202a to be divided into two.In the situation of fixing encapsulating structure size, the area of the chip bearing 202a of the present embodiment can be greater than the gross area of known the first chip bearing and the second chip bearing, and the semiconductor subassembly 100 that makes to be arranged at chip bearing 202a can increase the area of semiconductor base 102 or increase the size of high-side transistor assembly 104 and low side transistors assembly 106.Whereby, the opening resistor between the drain electrode of high-side transistor assembly 104 and source electrode and between drain electrode and the source electrode of low side transistors assembly 106 can be lowered, and then reduces the power loss of power supply conversion.And, represent that the second lead foot 202c of the grid lead foot of low side transistors assembly 106 is adjacent to the 3rd lead foot 202d and the 4th lead foot 202e of the source electrode lead foot that represents low side transistors assembly 106, with the distance between grid and the source electrode of shortening low side transistors assembly 106, and reduce and be series at the grid of low side transistors assembly 106 and the resistance value of source electrode and inductance value, the grid that makes low side transistors assembly 106 is unlikely delay voltage in the time of reception signal.
Please refer to Fig. 8, and in the lump with reference to figure 2.Fig. 8 is the circuit diagram of the transducer that utilizes semiconductor subassembly of the present invention to do to switch.As shown in Fig. 2 and Fig. 8, the grid of high-side transistor assembly 104 is electrically connected to a control assembly 216, and the grid of low side transistors assembly 106 is electrically connected to control assembly 216, therefore represent that the first lead foot 202b of the grid lead foot of high-side transistor assembly 104 is electrically connected to respectively control assembly 216 with the second lead foot 202c of the grid lead foot that represents low side transistors assembly 106.The source electrode of low side transistors assembly 106 is electrically connected to an earth terminal GND, makes the 3rd lead foot 202d of the source electrode lead foot that represents low side transistors assembly 106 and the 4th lead foot 202e be electrically connected to earth terminal GND.The drain electrode of high-side transistor assembly 104 is electrically connected to an input Vin, makes the 7th lead foot 202h of the drain electrode lead foot that represents high-side transistor assembly 104 and the 8th lead foot 202i be electrically connected to input Vin.And, the common tie point of the drain electrode of the source electrode of high-side transistor assembly 104 and low side transistors assembly 106 is electrically connected to one end of an inductance L and one end of a Schottky diode D, makes to represent that the 5th lead foot 202f of the source electrode lead foot of high-side transistor assembly 104 and the drain electrode lead foot of low side transistors assembly 106 and the 6th lead foot 202g are electrically connected to one end of inductance L and one end of Schottky diode D.The other end of inductance L is electrically connected to one end of an output end vo ut and a capacitor C, and the other end of Schottky diode D and the other end of capacitor C are electrically connected to earth terminal GND.In addition, a load resistance R is electrically connected between output end vo ut and earth terminal GND.What deserves to be explained is, be electrically connected to the 7th lead foot 202h of input Vin and the 8th lead foot 202i and be electrically connected to the 5th lead foot 202f of output end vo ut and the 6th lead foot 202g and be arranged at the same side of chip bearing 202a via inductance L, the resistance value, inductance value and the capacitance that make to be series between input Vin and output end vo ut reduce, and then promote the voltage transitions efficiency of emitted semiconductor assembly package structure 200.
In addition, the 3rd conductive component of the present invention, the 4th conductive component and the 5th conductive component are not limited to sheet metal, also can be other conductive component.Please refer to Fig. 9 and Figure 10, another of the emitted semiconductor assembly package structure that Fig. 9 is first embodiment of the invention implemented aspect, and Figure 10 another enforcement aspect of emitted semiconductor assembly package structure that is first embodiment of the invention.As shown in Figure 9, compared to above-mentioned the first embodiment, the 3rd conductive component 210, the 4th conductive component 212 and the 5th conductive component 214 of this enforcement aspect are a metal lead wire band, and its material comprises aluminium, but is not limited to this.As shown in figure 10, compared to above-mentioned the first embodiment, the 3rd conductive component 210, the 4th conductive component 212 and the 5th conductive component 214 of this enforcement aspect are respectively many strip metals wire.
In addition, the first N-type source doping region of semiconductor subassembly of the present invention is not limited to utilize high side source metal and the first contact plunger to be electrically connected to N type semiconductor substrate.Please refer to Figure 11, the generalized section of the semiconductor subassembly that Figure 11 is second embodiment of the invention.Below will continue to disclose other embodiments of the invention, so for the purpose of simplifying the description and highlight the difference between each embodiment, hereinafter will use same numeral mark same components, and no longer counterweight partly repeat again.As shown in figure 11, compared to the first embodiment, the semiconductor subassembly 300 of the present embodiment does not comprise high side source metal and the first contact plunger, be electrically connected high side source doping region 126 and semiconductor base 102, and second interlayer dielectric layer 302 of the present embodiment covers the second contact plunger 304 completely, with the high side drain metal layer 306 of electrical isolation and the second contact plunger 304.Whereby, the area of the high side drain metal layer 306 of the present embodiment can be greater than the area of the high side drain metal layer 160 of the first embodiment.And, for high side source doping region 126 is electrically connected to semiconductor base 102, second contact plunger 304 of the present embodiment runs through the second contact doping district 142, high side group body doped region 120 and epitaxial loayer 118, make high side source doping region 126 be electrically connected semiconductor base 102 by the second contact plunger 304, therefore the source electrode of high-side transistor assembly 104 can be electrically connected the drain electrode of low side transistors assembly 106.And the degree of depth of second contact plunger 304 of the present embodiment is greater than the degree of depth of the 3rd contact plunger 140.The manufacture method of the present embodiment semiconductor subassembly separately can be in forming the step in contact doping district and forming between the step of contact plunger, utilize Yi ten road photomasks to coordinate photoetching and etch process, continue etching second and contact hole 176, make the second contact hole 176 run through the second contact doping district 142, high side group body doped region 120 and epitaxial loayer 118, and extend to base material 116.Then, then carry out the technique of contact plunger, to form the second contact plunger 304.Therefore, second contact plunger 304 of the present embodiment, except running through the second contact doping district 142, high side group body doped region 120 and epitaxial loayer 118, has separately run through the first interlayer dielectric layer 132 and high side source doping region 126.But, the second contact plunger 304 of the present invention is not limited to run through epitaxial loayer 118, also can not run through epitaxial loayer 118, and only contacts with epitaxial loayer 118.
The present invention separately utilizes the semiconductor subassembly of the second embodiment that semiconductor assembly encapsulation structure is provided.Please refer to Figure 12, on the emitted semiconductor assembly package structure that Figure 12 is second embodiment of the invention, look schematic diagram.As shown in figure 12, compared to the first embodiment, because the semiconductor subassembly 300 of the present embodiment does not comprise high side source metal, therefore the emitted semiconductor assembly package structure 350 of the present embodiment does not comprise the 5th conductive component.And, the high side drain metal layer 306 of the present embodiment is greater than the area of the high side drain metal layer 160 of the first embodiment, therefore the 4th conductive component 352 can be greater than the 4th conductive component 212 of the first embodiment and the contact area of high side drain metal layer 160 with the contact area of high side drain metal layer 306, and the resistance value between drain electrode and the input of high-side transistor assembly 104 is reduced.
In addition, the structure of lead frame of the present invention is not limited to the structure of above-described embodiment.Please refer to Figure 13, the semiconductor subassembly that Figure 13 is third embodiment of the invention with and encapsulating structure on look schematic diagram.As shown in figure 13, compared to the first embodiment, the orientation of the 5th lead foot 202f, the 6th lead foot 202g, the 7th lead foot 202h and the 8th lead foot 202i of the emitted semiconductor assembly package structure 450 of the present embodiment is contrary with the orientation of the first embodiment, that is the 5th lead foot 202f of the present embodiment, the 6th lead foot 202g, the 7th lead foot 202h and the 8th lead foot 202i sequentially arrange along this direction 218, and the 5th lead foot 202f is still connected with chip bearing 202a with the 6th lead foot 202g.It should be noted that, for the high side source metal 162 that makes the present embodiment semiconductor subassembly 400 is still electrically connected with common metal level 166, the high side source metal 162 of the semiconductor subassembly 400 of the present embodiment also must be contrary with the arrangement position of the high side drain metal layer of the first embodiment and high side source metal with high side drain metal layer 160, and the high side source metal 162 of the present embodiment is sequentially arranged along this direction 218 with drain metal layer 160.Hence one can see that, the present embodiment represent high-side transistor assembly 104 source electrode lead foot the 5th lead foot 202f and the 6th lead foot 202g and represent that the first lead foot 202b of the grid lead foot of high-side transistor assembly 104 is located at the same side of contiguous packaging body 204, can shorten whereby the distance between source electrode lead foot and the grid lead foot of high-side transistor assembly 104, to reduce resistance value and the inductance value of the grid lead foot and the source electrode lead foot that are series at high-side transistor assembly 104, make the grid of high-side transistor assembly 104 in the time receiving signal, be unlikely delay voltage.
In addition, emitted semiconductor assembly package structure of the present invention also can be by the semiconductor device package of the second embodiment on the lead frame of the 3rd embodiment.Please refer to Figure 14, on the emitted semiconductor assembly package structure that Figure 14 is fourth embodiment of the invention, look schematic diagram.As shown in figure 14, compared to the 3rd embodiment, the semiconductor subassembly 500 of the present embodiment does not comprise high side source metal, and therefore the emitted semiconductor assembly package structure 550 of the present embodiment does not comprise the 5th conductive component.And, the high side drain metal layer 306 of the present embodiment is greater than the area of the high side drain metal layer 306 of the 3rd embodiment, therefore the 4th conductive component 352 can be greater than the 4th conductive component 212 of the first embodiment and the contact area of high side drain metal layer 160 with the contact area of high side drain metal layer 306, and the resistance value between drain electrode and the input of high-side transistor assembly 104 is reduced.
In sum, semiconductor subassembly of the present invention is on same semiconductor base, to produce high-side transistor assembly and low side transistors assembly, and by contact plunger, the drain electrode of the source electrode of high-side transistor assembly and low side transistors assembly is electrically connected, make can combine as high-side transistor assembly and the low side transistors assembly of transducer.Whereby, emitted semiconductor assembly package structure only needs to utilize a chip bearing that semiconductor assembly is set, and the semiconductor subassembly that makes to be arranged at chip bearing can increase the area of semiconductor base or increase the size of high-side transistor assembly and low side transistors assembly.Whereby, the opening resistor between the drain electrode of high-side transistor assembly and source electrode and between drain electrode and the source electrode of low side transistors assembly can be lowered, and then reduces the power loss of power supply conversion.And, emitted semiconductor assembly package structure of the present invention further will be electrically connected to the 7th lead foot and the 8th lead foot of input and approach the 5th lead foot of output and the 6th lead foot is arranged at the same side of chip bearing, the resistance value, inductance value and the capacitance that make to be series between input and output reduce, and then can promote the voltage transitions efficiency of emitted semiconductor assembly package structure.
The foregoing is only the preferred embodiments of the present invention, all equalizations of doing according to the claims in the present invention change and modify, and all should belong to covering scope of the present invention.

Claims (21)

1. a semiconductor subassembly of integrating transducer, is characterized in that, comprising:
Semiconductor substrate, the definition of this semiconductor base has a high-side transistor assembly district and a low side transistors assembly district, and this semiconductor base has one first conduction type, and wherein this semiconductor base in this low side transistors assembly district has a groove;
One high-side transistor assembly, be located in this high-side transistor assembly district, and this high-side transistor assembly comprises:
One high side group body doped region, is located in this semiconductor base in this high-side transistor assembly district, and this high side group body doped region has one second conduction type;
One light drain doping region, be located in this high side group body doped region, and this light drain doping region has this first conduction type;
One drain doping region, is located in this light drain doping region, and this drain doping region has this first conduction type;
One high side source doping region, be located in this high side group body doped region of this light drain doping region one side, and this high side source doping region has this first conduction type; And
One high side grid conducting layer, is located on this high side group body doped region between this light drain doping region and this high side source doping region;
One high side drain metal layer, is located on this semiconductor base in this high-side transistor assembly district, and is electrically connected this drain doping region;
One high side gate metal layer, is located on this semiconductor base in this high-side transistor assembly district, and is electrically connected to this high side grid conducting layer;
One common metal level, be located at this semiconductor-based under, and be electrically connected this high side source doping region and this semiconductor base;
One low side transistors assembly, be located in this low side transistors assembly district, and this low side transistors assembly comprises:
One grid;
One downside matrix doped region, is located in this semiconductor base of this groove one side, and this downside matrix doped region has this second conduction type; And
One downside source doping region, is located in this downside matrix doped region, and this downside source doping region has this first conduction type, and as the one source pole of this low side transistors assembly, wherein this semiconductor base is as a drain electrode of this low side transistors assembly;
One downside source metal, is located on this semiconductor base in this low side transistors assembly district, and is electrically connected this source electrode of this low side transistors assembly;
One lowside gate metal level, is located on this semiconductor base of this low side transistors assembly, and is electrically connected this grid of this low side transistors assembly; And
One first interlayer dielectric layer, is located between this semiconductor base and this high side drain metal layer and this downside source metal.
2. semiconductor subassembly as claimed in claim 1, is characterized in that, separately comprises a high side source metal, is located on this first interlayer dielectric layer in this high-side transistor assembly district, and is electrically connected this semiconductor base and this high side source doping region.
3. semiconductor subassembly as claimed in claim 2, is characterized in that, separately comprises:
One first contact plunger, runs through this first interlayer dielectric layer, and is electrically connected this high side source metal and this semiconductor base; And
One second contact plunger, runs through this first interlayer dielectric layer and this high side source doping region, and is electrically connected this high side source metal and this high side source doping region.
4. semiconductor subassembly as claimed in claim 3, is characterized in that, separately comprises one the 3rd contact plunger, runs through this first interlayer dielectric layer and this drain doping region, and is electrically connected this high side drain metal layer, this drain doping region and this light drain doping region.
5. semiconductor subassembly as claimed in claim 4, it is characterized in that, separately comprise one second interlayer dielectric layer, be located on this first interlayer dielectric layer, and this high side drain metal layer of electrical isolation and this first contact plunger and this second contact plunger, and this high side source metal of electrical isolation and the 3rd contact plunger.
6. semiconductor subassembly as claimed in claim 1, is characterized in that, separately comprises:
One second contact plunger, runs through this first interlayer dielectric layer, this high side source doping region and this high side group body doped region, and is electrically connected this high side source doping region and this semiconductor base; And
One the 3rd contact plunger, runs through this first interlayer dielectric layer and this drain doping region, and is electrically connected this high side drain metal layer and this drain doping region and this light drain doping region.
7. semiconductor subassembly as claimed in claim 6, is characterized in that, separately comprises one second interlayer dielectric layer, is located between this second contact plunger and this high side drain metal layer, with this high side drain metal layer of electrical isolation and this second contact plunger.
8. semiconductor subassembly as claimed in claim 6, is characterized in that, wherein the degree of depth of this second contact plunger is greater than the degree of depth of the 3rd contact plunger.
9. semiconductor subassembly as claimed in claim 1, is characterized in that, separately comprises a contact doping district, is located in this semiconductor base of this high side group body doped region one side, and is electrically connected this high side source metal, and have this second conduction type.
10. semiconductor subassembly as claimed in claim 1, is characterized in that, wherein this low side transistors assembly comprises:
One insulating barrier, is covered on this semiconductor base in this groove; And
One lowside gate conductive layer, is located in this groove, and as this grid of this low side transistors assembly.
11. semiconductor subassemblies as claimed in claim 10, is characterized in that, wherein this high side group body doped region and this downside matrix doped region have same depth.
Integrate the emitted semiconductor assembly package structure of transducer for 12. 1 kinds, it is characterized in that, comprising:
One lead frame, comprising:
One chip bearing, has one first side and second side with respect to this first side;
One first lead foot, is located at this first side of this chip bearing;
One second lead foot, is located at this first side of this chip bearing;
One the 3rd lead foot, is located at this first side of this chip bearing;
One the 4th lead foot, is located at this first side of this chip bearing, and the 3rd lead foot and the 4th lead foot are electrically connected this chip bearing;
One the 5th lead foot, is located at this second side of this chip bearing;
One the 6th lead foot, is located at this second side of this chip bearing, and is connected with the 5th lead foot;
One the 7th lead foot, is located at this second side of this chip bearing; And
One the 8th lead foot, is located at this second side of this chip bearing, and is connected with the 7th lead foot;
Semiconductor assembly, be located in this chip bearing, and this semiconductor subassembly comprises:
Semiconductor substrate, the definition of this semiconductor base has a high-side transistor assembly district and a low side transistors assembly district, and this semiconductor base has one first conduction type, and wherein this semiconductor base in this low side transistors assembly district has a groove;
One high-side transistor assembly, be located in this high-side transistor assembly district, and this high-side transistor assembly comprises:
One high side group body doped region, is located in this semiconductor base in this high-side transistor assembly district, and this high side group body doped region has one second conduction type;
One light drain doping region, be located in this high side group body doped region, and this light drain doping region has this first conduction type;
One drain doping region, is located in this light drain doping region, and this drain doping region has this first conduction type;
One high side source doping region, be located in this high side group body doped region of this light drain doping region one side, and this high side source doping region has this first conduction type; And
One high side grid conducting layer, is located on this high side group body doped region between this light drain doping region and this high side source doping region;
One high side drain metal layer, is located on this semiconductor base in this high-side transistor assembly district, and is electrically connected this drain doping region;
One high side gate metal layer, is located on this semiconductor base in this high-side transistor assembly district, and is electrically connected to this high side grid conducting layer;
One common metal level, be located at this semiconductor-based under, and be electrically connected this high side source doping region and this semiconductor base;
One low side transistors assembly, be located in this low side transistors assembly district, and this low side transistors assembly comprises:
One grid;
One downside matrix doped region, is located in this semiconductor base of this groove one side, and this downside matrix doped region has this second conduction type; And
One downside source doping region, is located in this downside matrix doped region, and this downside source doping region has this first conduction type, and as the one source pole of this low side transistors assembly, wherein this semiconductor base is as a drain electrode of this low side transistors assembly;
One downside source metal, is located on this semiconductor base in this low side transistors assembly district, and is electrically connected this source electrode of this low side transistors assembly;
One lowside gate metal level, is located on this semiconductor base of this low side transistors assembly, and is electrically connected this grid of this low side transistors assembly; And
One first interlayer dielectric layer, is located between this semiconductor base and this high side drain metal layer and this downside source metal; And
One packaging body, coated this semiconductor subassembly and this lead frame of part.
13. emitted semiconductor assembly package structures as claimed in claim 12, it is characterized in that, separately comprise one first conductive component, one second conductive component, one the 3rd conductive component and one the 4th conductive component, this first conductive component is electrically connected high side gate metal layer and this first lead foot, this second conductive component is electrically connected this lowside gate metal level and this second lead foot, the 3rd conductive component is electrically connected this downside source metal and the 3rd lead foot and the 4th lead foot, and the 4th conductive component is electrically connected this high side drain metal layer and the 7th lead foot and the 8th lead foot.
14. emitted semiconductor assembly package structures as claimed in claim 13, is characterized in that, wherein this first conductive component and this second conductive component are respectively a plain conductor.
15. emitted semiconductor assembly package structures as claimed in claim 13, is characterized in that, wherein the 3rd conductive component and the 4th conductive component are respectively a metal lead wire band.
16. emitted semiconductor assembly package structures as claimed in claim 13, is characterized in that, wherein the 3rd conductive component and the 4th conductive component are respectively a sheet metal.
17. emitted semiconductor assembly package structures as claimed in claim 13, is characterized in that, wherein the 3rd conductive component and the 4th conductive component are respectively many strip metals wire.
18. emitted semiconductor assembly package structures as claimed in claim 13, is characterized in that, separately comprise a high side source metal, are located on this first interlayer dielectric layer in this high-side transistor assembly district, and are electrically connected this semiconductor base and this high side source doping region.
19. emitted semiconductor assembly package structures as claimed in claim 18, is characterized in that, separately comprise one the 5th conductive component, are electrically connected this high side source metal and the 5th lead foot and the 6th lead foot.
20. emitted semiconductor assembly package structures as claimed in claim 12, it is characterized in that, wherein this first lead foot, this second lead foot, the 3rd lead foot and the 4th lead foot are sequentially arranged along a direction, and the 8th lead foot, the 7th lead foot, the 6th lead foot and the 5th lead foot are sequentially arranged along this direction.
21. emitted semiconductor assembly package structures as claimed in claim 12, it is characterized in that, wherein this first lead foot, this second lead foot, the 3rd lead foot and the 4th lead foot are sequentially arranged along a direction, and the 5th lead foot, the 6th lead foot, the 7th lead foot and the 8th lead foot are sequentially arranged along this direction.
CN201010509457.7A 2010-10-08 2010-10-08 Semiconductor component of integration converter and packaging structure thereof Active CN102447383B (en)

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CN110299331A (en) * 2019-07-07 2019-10-01 上海晶丰明源半导体股份有限公司 Multichip packaging structure and packaging frame array applied to power supply change-over device
WO2021029150A1 (en) * 2019-08-13 2021-02-18 富士電機株式会社 Semiconductor device
CN114171472B (en) * 2021-11-26 2024-04-16 南京元络芯科技有限公司 Lateral double-diffusion metal oxide semiconductor field effect transistor and manufacturing method thereof

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