JPH10136641A - Dc-dc converter apparatus - Google Patents
Dc-dc converter apparatusInfo
- Publication number
- JPH10136641A JPH10136641A JP8290687A JP29068796A JPH10136641A JP H10136641 A JPH10136641 A JP H10136641A JP 8290687 A JP8290687 A JP 8290687A JP 29068796 A JP29068796 A JP 29068796A JP H10136641 A JPH10136641 A JP H10136641A
- Authority
- JP
- Japan
- Prior art keywords
- switching means
- diode
- mosfet
- built
- sbd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000004888 barrier function Effects 0.000 claims abstract description 15
- 239000003990 capacitor Substances 0.000 claims abstract description 9
- 238000009499 grossing Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 13
- 239000000758 substrate Substances 0.000 abstract description 13
- 229910052782 aluminium Inorganic materials 0.000 description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 12
- 239000000969 carrier Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000001360 synchronised effect Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000011084 recovery Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 108010017036 dynorphin A-converting enzyme Proteins 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000001172 regenerating effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1588—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Dc-Dc Converters (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＤＣ−ＤＣコンバ
ータ装置に関し、特に、同期整流方式のＤＣ−ＤＣコン
バータ装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC-DC converter, and more particularly to a synchronous rectification type DC-DC converter.
【０００２】[0002]
【従来の技術】スイッチング電源の主要な部分を構成す
る同期整流型のＤＣ−ＤＣコンバータは、図５に示すよ
うに、直流入力電源をスイッチングする第１のスイッチ
ング手段１と、第１のスイッチング手段１に接続され第
１のスイッチング手段１に同期してスイッチングする第
２のスイッチング手段２と、両スイッチング手段１、２
と接続されたリアクタ３及びコンデンサー４とをから構
成される。2. Description of the Related Art As shown in FIG. 5, a synchronous rectification type DC-DC converter constituting a main part of a switching power supply comprises a first switching means 1 for switching a DC input power supply, and a first switching means. A second switching means 2 connected to the first switching means 1 for switching in synchronization with the first switching means 1;
And a condenser 4 connected to the reactor 3.
【０００３】第１のスイッチング手段１をＯＮさせた
時、第２のスイッチング手段２をＯＦＦ状態として、両
スイッチング手段の同期期間を調整し、直流入力電源を
リアクタ３及びコンデンサー４により平滑化することに
より、負荷に所定の直流出力電源を供給する。上記のＤ
Ｃ−ＤＣコンバータは電圧降下が小さく高効率化に大き
く寄与することからスイッチング電源に広く用いられつ
つある。When the first switching means 1 is turned on, the second switching means 2 is turned off to adjust the synchronization period of the two switching means, and the DC input power is smoothed by the reactor 3 and the capacitor 4. Supplies a predetermined DC output power to the load. D above
C-DC converters are being widely used in switching power supplies because they have a small voltage drop and greatly contribute to higher efficiency.
【０００４】上記ＤＣ−ＤＣコンバータを構成する各要
素は、図示しないが、ガラスエポキシ、セラミックス、
金属等をベースにした配線基板上に実装され、上記第１
のスイッチング手段１はトタンジスタ或いはパワーＭＯ
ＳＦＥＴ、第２のスイッチング手段２はパワーＭＯＳＦ
ＥＴが用いられる。一般的な縦型パワーＭＯＳＦＥＴ素
子は、図６に示すように、Ｎ＋／Ｎ−基板のＮ−層１１
の表面にＰ型のベース領域１２を多数形成し、ベース領
域１２の表面にＮ＋型のソース領域１３を形成し、ベー
ス領域１２のチャンネル部分の上にゲート電極１４を配
置し、ベース領域１２とソース領域１３の両方にオーミ
ックコンタクトするソース電極１５を形成した構造を持
つものである。[0004] Although not shown, each element constituting the DC-DC converter is made of glass epoxy, ceramic,
Mounted on a wiring board based on metal or the like;
Switching means 1 is a transistor or power MO
SFET, the second switching means 2 is a power MOSF
ET is used. As shown in FIG. 6, a general vertical power MOSFET device has an N− layer 11 of an N + / N− substrate.
A large number of P-type base regions 12 are formed on the surface of the base region 12, an N + type source region 13 is formed on the surface of the base region 12, and a gate electrode 14 is disposed on a channel portion of the base region 12. It has a structure in which a source electrode 15 that makes ohmic contact with both of the source regions 13 is formed.
【０００５】上記ＤＣ−ＤＣコンバータの第２のスイッ
チング手段に、例えば、ＮｃｈＭＯＳＦＥＴを用いた場
合、以下の様な問題が確認された。第１のスイッチング
手段１がＯＦＦの時、第２のスイッチング手段２のＮｃ
ｈＦＥＴがＯＮし、電流経路に接続されるリアクタ３の
回生電流は、コンデンサー４、ＭＯＳＦＥＴ素子２（内
蔵ダイオード２Ａ）、リアクタ３というループで流れ、
ＭＯＳＦＥＴ素子２内部に形成された上記内蔵ダイオー
ド２Ａにキャリア（電子）が蓄積される。When the N-channel MOSFET is used as the second switching means of the DC-DC converter, for example, the following problems have been confirmed. When the first switching means 1 is OFF, Nc of the second switching means 2
The hFET is turned on, and the regenerative current of the reactor 3 connected to the current path flows through a loop of the capacitor 4, the MOSFET element 2 (built-in diode 2A), and the reactor 3.
Carriers (electrons) are accumulated in the built-in diode 2A formed inside the MOSFET element 2.
【０００６】この内蔵ダイオードに蓄積されたキャリア
によって、第２のスイッチング手段２がＯＦＦされ、第
１のスイッチング手段１がＯＮされたとき、キャリアが
完全に放出される時間、即ち、逆回復時間中、直流入力
電源の一部が内蔵ダイオード２Ａを介して流れることに
なり、負荷へ供給される電源効率が低下する。また、上
記直流入力電源の一部がＯＦＦ状態の第２のスイッチン
グ手段（ＮｃｈＭＯＳＦＥＴ）の内蔵ダイオード２Ａに
流れると新たなキャリアが蓄積され、このキャリアによ
る逆回復時間の間は、ＮｃｈＭＯＳＦＥＴ２のゲートに
ＯＮ信号が印加されても、ＭＯＳＦＥＴ素子２がＯＮ動
作しない。この逆回復時間は、Ｎ−型層１１に蓄積され
たキャリア（電子）が内蔵ダイオード２Ａを介して完全
に放出され内蔵ダイオード２ＡのＰＮ接合が回復するま
での時間であり、ベース領域とＮ−型層とのＰＮ接合が
不可避的にできるパワーＭＯＳＦＥＴの寄生ダイオード
によって形成される。When the second switching means 2 is turned off and the first switching means 1 is turned on by the carriers accumulated in the built-in diode, the time when the carriers are completely discharged, that is, during the reverse recovery time Part of the DC input power flows through the built-in diode 2A, and the efficiency of the power supplied to the load decreases. Further, when a part of the DC input power flows through the built-in diode 2A of the second switching means (NchMOSFET) in the OFF state, new carriers are accumulated, and during the reverse recovery time due to the carriers, the ON of the gate of the NchMOSFET2 is established. Even if the signal is applied, the MOSFET element 2 does not perform the ON operation. The reverse recovery time is the time until the carriers (electrons) accumulated in the N − -type layer 11 are completely released through the built-in diode 2A and the PN junction of the built-in diode 2A is recovered, and the base region and the N− The PN junction with the mold layer is formed by a parasitic diode of the power MOSFET which is inevitable.
【０００７】従って、同期整流方式のＤＣ−ＤＣコンバ
ータ装置の電源効率の低下及び回路全体のスイッチング
タイムを向上することができないという結果になる。上
述した不具合を解決するために、図７に示すように、内
蔵ダイオード２Ａと並列にショットキーバリアダイオー
ド（ＳＢＤ）２０を接続し、ＳＢＤ２０の順方向電圧Ｖ
FがＰＮダイオードより低いことを利用して、ＮｃｈＭ
ＯＳＦＥＴのドレイン電位を速やかにソース電位に落と
すことにより、回路全体のスイッチング速度を向上させ
てＤＣ−ＤＣコンバータの高効率化を向上させている。As a result, the power efficiency of the synchronous rectification type DC-DC converter device cannot be reduced and the switching time of the entire circuit cannot be improved. In order to solve the above problem, as shown in FIG. 7, a Schottky barrier diode (SBD) 20 is connected in parallel with the built-in diode 2A, and the forward voltage V
Utilizing that F is lower than PN diode, NchM
By rapidly reducing the drain potential of the OSFET to the source potential, the switching speed of the entire circuit is improved, and the efficiency of the DC-DC converter is improved.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、上記の
回路を各々個別素子で構成するには、部品点数が増大し
電子機器の小型化に障害となる。そこでＦＥＴチップと
ＳＢＤチップとを１パッケージに収納することも検討し
たが、別個のウェハーで製造するために各々の良品数な
どの問題があり、また組立工程も煩雑になる問題点があ
った。However, when each of the above circuits is constituted by individual elements, the number of components increases, which hinders miniaturization of electronic equipment. Therefore, it has been considered to house the FET chip and the SBD chip in one package. However, since they are manufactured on separate wafers, there are problems such as the number of non-defective products, and the assembly process becomes complicated.
【０００９】また、上記の問題点を解決すべくＦＥＴと
ＳＢＤとをディスクリート部品を用いて構成した場合、
両部品を基板上に実装し、両者を接続する導体パターン
が基板上に形成されるために、この導体パターンがノイ
ズ発生源となり周辺回路に悪影響を及ぼす問題点が及び
部品実装面積が大きくなり、配線基板の小型化に影響を
及ぼし、ひいてはＤＣ−ＤＣコンバータ装置或いはスイ
ッチング電源装置の小型化に影響を及ぼし、ハンディ・
カムコーダ、ディジタルカメラ、ラップトップ型ＰＣ等
の電子部品が小型化高密度されるセット製品の小型化に
まで影響を及ぼす。Further, when the FET and the SBD are configured by using discrete components in order to solve the above problems,
Since both parts are mounted on the board and the conductor pattern connecting them is formed on the board, this conductor pattern becomes a noise source and adversely affects peripheral circuits, and the component mounting area increases, This affects the miniaturization of the wiring board, which in turn affects the miniaturization of the DC-DC converter device or the switching power supply device.
Electronic components such as camcorders, digital cameras, and laptop PCs are downsized, which also affects the downsizing of high-density set products.
【００１０】そこで本発明は、上記の事情について鑑み
てなされたもので、ＤＣ−ＤＣコンバータを構成する部
品が実装される配線基板を小型化にし、セット製品の小
型化に寄与でき、且つ高効率化したＤＣ−ＤＣコンバー
タ装置を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has been made to reduce the size of a wiring board on which components constituting a DC-DC converter are mounted, to contribute to downsizing of a set product, and to achieve high efficiency. It is an object of the present invention to provide a simplified DC-DC converter device.
【００１１】[0011]
【課題を解決するための手段】本発明は上記課題を解決
するため、以下の構成を採用した。即ち、本発明のＤＣ
−ＤＣコンバータ装置は、少なくとも直流入力電源をＯ
Ｎ／ＯＦＦする第１のスイッチング手段と、前記第１の
スイッチング手段に同期しＯＦＦ／０Ｎする第２のスイ
ッチング手段と、前記第１、第２のスイッチング手段に
接続され前記直流入力電源を平滑するリアクタ及び前記
リアクタに一端が接続されたコンデンサーとが配線基板
上に実装され前記直流入力電源を所定の直流出力電源に
変換するＤＣ−ＤＣコンバータ装置において、前記第２
のスイッチング手段は、内蔵ダイオードと該内蔵ダイオ
ードに並列に接続されるショットキーバリアダイオード
とを備えたＭＯＳＦＥＴであることを特徴としている。The present invention has the following features to attain the object mentioned above. That is, the DC of the present invention
-The DC converter device has at least a DC input power supply
First switching means for turning on / off, second switching means for turning off / on in synchronization with the first switching means, and smoothing the DC input power supply connected to the first and second switching means; A DC-DC converter device, wherein a reactor and a capacitor having one end connected to the reactor are mounted on a wiring board and convert the DC input power to a predetermined DC output power;
Is characterized by being a MOSFET having a built-in diode and a Schottky barrier diode connected in parallel to the built-in diode.
【００１２】上述したように、ＤＣ−ＤＣコンバータ装
置の直流入力電源をスイッチングする第１のスイッチン
グ手段と同期してスイッチングする第２のスイッチング
手段に、パワーＭＯＳＦＥＴに内蔵される内蔵ダイオー
ドに並列に接続されるショットキーバリアダイオード
（ＳＢＤ）を同一の半導体基板に形成したパワーＭＯＳ
ＦＥＴを用いることにより、ＭＯＳＦＥＴ内部に形成し
ＳＢＤを形成しているので蓄積キャリアを瞬時に引き抜
いて完全遮断化を促進し、ＭＯＳＦＥＴの内蔵ダイオー
ドに順方向電流が流れた時であってもＭＯＳＦＥＴのス
イッチングを高速にすることができ、ＤＣ−ＤＣコンバ
ータ回路の更なる高効率化が可能となる。As described above, the second switching means for switching in synchronization with the first switching means for switching the DC input power of the DC-DC converter device is connected in parallel with the built-in diode built in the power MOSFET. MOS with Schottky barrier diode (SBD) formed on the same semiconductor substrate
By using the FET, the SBD is formed inside the MOSFET to form the SBD, so that the accumulated carriers are instantaneously pulled out to promote complete shutoff, and even when a forward current flows through the internal diode of the MOSFET, Switching can be performed at high speed, and the efficiency of the DC-DC converter circuit can be further improved.
【００１３】更に、ＭＯＳＦＥＴとＳＢＤとを１チップ
化することにより、スイッチング手段であるパワーＭＯ
ＳＦＥＴのサイズを高機能化して縮小することができ、
ＤＣ−ＤＣコンバータ装置の用いられる配線基板の小型
化に寄与することができる。Further, by integrating the MOSFET and the SBD into one chip, the power
It is possible to reduce the size of the SFET by enhancing its function,
This can contribute to downsizing of the wiring board used in the DC-DC converter device.
【００１４】[0014]
【発明の実施の形態】以下に、本発明のＤＣ−ＤＣコン
バータ装置を図面を参照して詳細に説明する。図１は、
本発明のＤＣ−ＤＣコンバータ装置の等価回路図であ
る。等価回路は、図５に示した従来のＤＣ−ＤＣコンバ
ータ装置と同様に、直流入力電源をスイッチングする第
１のスイッチング手段１と、第１のスイッチング手段１
に接続され第１のスイッチング手段１に同期してスイッ
チングする第２のスイッチング手段２と、両スイッチン
グ手段１、２と接続されたリアクタ３及びコンデンサー
４とをから構成され、少なくともそれらの構成要素が配
線基板上に実装接続される。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a DC-DC converter according to the present invention will be described in detail with reference to the drawings. FIG.
It is an equivalent circuit diagram of the DC-DC converter device of the present invention. The equivalent circuit includes a first switching unit 1 for switching a DC input power supply and a first switching unit 1 as in the conventional DC-DC converter shown in FIG.
And a second switching means 2 which is connected to the first switching means 1 and switches in synchronization with the first switching means 1, and a reactor 3 and a capacitor 4 which are connected to the two switching means 1 and 2, and at least those constituent elements are provided. It is mounted and connected on the wiring board.
【００１５】第１のスイッチング手段１は、トランジス
タ、ＭＯＳＦＥＴ等の半導体素子が用いられ、入力端子
に入力される所定周期のパルスでスイッチングされ、第
１のスイッチング手段に流れる直流入力電源をＯＮ／Ｏ
ＦＦする。第２のスイッチング手段２は、パワーＭＯＳ
ＦＥＴが用いられ、第１のスイッチング手段１と同期し
た所定周期のパルスが入力端子に入力されＯＦＦ／ＯＮ
される。この動作を繰り返し行い直流入力電源をリアク
タ３及びコンデンサー４により平滑化することにより、
負荷に所定の直流出力電源を供給する。The first switching means 1 uses a semiconductor element such as a transistor or a MOSFET, is switched by a pulse having a predetermined cycle inputted to an input terminal, and turns on / off a DC input power supply flowing through the first switching means.
FF. The second switching means 2 is a power MOS
An FET is used, and a pulse of a predetermined cycle synchronized with the first switching means 1 is input to an input terminal to turn OFF / ON.
Is done. By repeating this operation and smoothing the DC input power by the reactor 3 and the capacitor 4,
A predetermined DC output power is supplied to the load.
【００１６】ＤＣ−ＤＣコンバータを構成する上記第１
のスイッチング手段１、第２のスイッチング手段２、リ
アクタ３及びコンデンサー４は、ガラスエポキシ基板、
ポリイミド基板、フェノール基板、セラミックス基板、
絶縁処理された金属基板等の配線基板上に銅箔等により
形成された回路パターンに実装接続される。本発明の特
徴とするところは、第１のスイッチング手段１と同期し
てスイッチングする第２のスイッチング手段２にある。[0016] The first of the above constituting the DC-DC converter
The switching means 1, the second switching means 2, the reactor 3 and the capacitor 4 are a glass epoxy substrate,
Polyimide substrate, phenol substrate, ceramic substrate,
It is mounted and connected to a circuit pattern formed of a copper foil or the like on a wiring substrate such as a metal substrate that has been subjected to an insulation treatment. The feature of the present invention resides in a second switching means 2 that switches in synchronization with the first switching means 1.
【００１７】本発明の第２のスイッチング手段２は、図
２に示すように、Ｎ＋型基板の上にＮ−型エピタキシャ
ル層を形成したもの、あるいはＮ−型基板にＮ＋型層を
拡散により形成したＮ＋／Ｎー型の半導体基板２１を基
体とし、Ｎ−型層２２の表面にパワーＭＯＳＦＥＴ素子
２３とショットキーバリアダイオード素子２４（ＳＢＤ
素子と称する）とを形成したものである。パワーＭＯＳ
ＦＥＴ素子２３とショットキバリアダイオード素子２４
とを併設することにより、各々所望の電流容量を持つ素
子を１チップ化した半導体素子である。As shown in FIG. 2, the second switching means 2 of the present invention comprises an N + type epitaxial layer formed on an N + type substrate or an N + type layer formed on an N + type substrate by diffusion. With the N + / N− type semiconductor substrate 21 as a base, the power MOSFET element 23 and the Schottky barrier diode element 24 (SBD
(Referred to as an element). Power MOS
FET element 23 and Schottky barrier diode element 24
By combining these elements, the semiconductor elements each having a desired current capacity are integrated into one chip.
【００１８】ＭＯＳＦＥＴ素子２３は、Ｎ−型層２２を
共通ドレインとし、Ｎ−型層２２の表面にＰ＋型のベー
ス領域２５を複数形成し、ベース領域２５の表面にＮ＋
型のソース領域２６を形成し、ソース領域２６とＮ−型
層２２とに挟まれたベース領域２５のＰ型層をチャンネ
ル領域２７とし、チャンネル領域２７の上にゲート酸化
膜２８を挟んでポリシリコンゲート電極２９を配置し、
ゲート電極２９を被覆するＰＳＧ酸化膜３０に形成した
コンタクトホールを介して、バリアメタル３１とアルミ
電極３２とがベース領域２５とソース領域２６とにオー
ミックコンタクトしている。In the MOSFET element 23, the N− type layer 22 is used as a common drain, a plurality of P + type base regions 25 are formed on the surface of the N− type layer 22, and the N + type layer 22 is formed on the surface of the base region 25.
A source region 26 is formed, and a P-type layer of a base region 25 sandwiched between the source region 26 and the N− type layer 22 is defined as a channel region 27, and a poly oxide is formed on the channel region 27 with a gate oxide film 28 interposed therebetween. A silicon gate electrode 29 is arranged,
The barrier metal 31 and the aluminum electrode 32 are in ohmic contact with the base region 25 and the source region 26 via a contact hole formed in the PSG oxide film 30 covering the gate electrode 29.
【００１９】ＳＢＤ素子２４は、Ｎ−型層２２をカソー
ドとし、Ｎ−型層２２の表面にＰ＋型のガードリング領
域３３を形成し、ガードリング領域３３の上を端とする
酸化膜の開口を介してＮ−型層２２の表面にバリアメタ
ル３１がショットキーコンタクトし、その上にアルミ電
極３２を形成している。アルミ電極３２は、純粋アルミ
またはアルミニウム・シリコン合金が用いられ、ＭＯＳ
ＦＥＴ素子２３では多数のソース領域２６を並列接続す
るソース電極となり、ＳＢＤ素子２４ではアノード電極
となる。In the SBD element 24, an N− type layer 22 is used as a cathode, a P + type guard ring region 33 is formed on the surface of the N− type layer 22, and an opening of an oxide film having the upper end of the guard ring region 33 as an end. A barrier metal 31 is in Schottky contact with the surface of the N− type layer 22 via the via hole, and an aluminum electrode 32 is formed thereon. The aluminum electrode 32 is made of pure aluminum or aluminum-silicon alloy,
In the FET element 23, it becomes a source electrode for connecting a large number of source regions 26 in parallel, and in the SBD element 24, it becomes an anode electrode.
【００２０】図３は、第２のスイッチング手段を構成す
る半導体素子の平面図を示す。詳細には図示していない
が、ゲート電極２９は格子型のパターンを有し、ベース
領域２５は前記格子型パターンの網目の部分に点在する
島状のパターンを持つ。反対にゲート電極２９が島状、
ベース領域２５が格子型のパターンもある。前記格子型
パターンの網目の各々が単位ＭＯＳセルとなり、該ＭＯ
Ｓセルを形成した領域がＭＯＳＦＥＴ領域２３Ｂであ
る。FIG. 3 is a plan view of a semiconductor device constituting the second switching means. Although not shown in detail, the gate electrode 29 has a lattice-type pattern, and the base region 25 has an island-like pattern scattered in a mesh portion of the lattice-type pattern. On the contrary, the gate electrode 29 has an island shape,
There is also a pattern in which the base region 25 has a lattice type. Each of the meshes of the lattice type pattern becomes a unit MOS cell, and the MO
The region where the S cell is formed is the MOSFET region 23B.
【００２１】ＳＢＤ素子２４は、ガードリング領域３３
が環状のパターンを具備し、該環状パターンの内側でバ
リアメタル３１がＮ−型層２２表面にショットキー接触
している。該ガードリング領域を含めた領域が、ＳＢＤ
領域２４Ｂである。ＭＯＳＦＥＴ領域２３Ｂ、ＳＢＤ領
域２４Ｂを囲むようにチップ周囲にはＮ＋型のチャンネ
ルストッパ領域３４を形成し、チャンネルストッパ領域
３４はＭＯＳＦＥＴ領域２３ＢとＳＢＤ領域２４Ｂとの
間にも延在する。間に延在するチャンネルストッパ領域
３４Ｂは、ベース領域２５と、Ｎ−型層２２と、ガード
リング領域３３とで形成する寄生のＰＮＰトランジスタ
の発生を抑制する役割を果たす。The SBD element 24 has a guard ring region 33
Has an annular pattern, and the barrier metal 31 is in Schottky contact with the surface of the N− type layer 22 inside the annular pattern. The area including the guard ring area is SBD
This is the area 24B. An N + type channel stopper region 34 is formed around the chip so as to surround the MOSFET region 23B and the SBD region 24B, and the channel stopper region 34 also extends between the MOSFET region 23B and the SBD region 24B. The channel stopper region 34B extending therebetween plays a role of suppressing generation of a parasitic PNP transistor formed by the base region 25, the N − type layer 22, and the guard ring region 33.
【００２２】ソース領域２６を並列接続するアルミ電極
３２は、最終パッシベーション膜としてのシリコン窒化
膜（図示せず）で被覆され、該シリコン窒化膜に開口を
形成することによってボンディングパッドを形成する。
アルミ電極３２は、ＭＯＳＦＥＴ領域の前記ＭＯＳセル
の上部でソース電極パッド３５を形成する。ポリシリコ
ンゲート電極２９は、ポリシリコン材料をチップ周辺部
分まで延在させ、該延在したポリシリコン材料にアルミ
電極をコンタクトさせることでゲート電極パッド３６を
形成する。ゲート電極パッド３６はソース電極となるア
ルミ電極３２とは電気的に独立し、ポリシリコン層とア
ルミ材料との間にはバリアメタル３１は特に必要ない。The aluminum electrode 32 connecting the source regions 26 in parallel is covered with a silicon nitride film (not shown) as a final passivation film, and a bonding pad is formed by forming an opening in the silicon nitride film.
The aluminum electrode 32 forms a source electrode pad 35 above the MOS cell in the MOSFET region. The polysilicon gate electrode 29 extends the polysilicon material to the peripheral portion of the chip, and contacts the aluminum electrode to the extended polysilicon material to form the gate electrode pad 36. The gate electrode pad 36 is electrically independent of the aluminum electrode 32 serving as a source electrode, and the barrier metal 31 is not particularly required between the polysilicon layer and the aluminum material.
【００２３】バリアメタル３１とアルミ電極３２はチャ
ンネルストッパ領域３４Ｂの上方を横断してＳＢＤ領域
２４Ｂまで延在し、延在したアルミ電極３２はその上の
シリコン窒化膜の一部を開口することによってアノード
電極パッド３７を形成する。チャンネルストッパ領域３
４Ｂ上を延在するアルミ電極３２は、できるだけ電気抵
抗を下げるためおよび後述する熱的結合を強化するため
に、できるだけ幅広い線幅、例えば電極パッド３５、３
７の幅より大きい線幅で延在している。The barrier metal 31 and the aluminum electrode 32 extend over the channel stopper region 34B to the SBD region 24B, and the extended aluminum electrode 32 is formed by opening a part of the silicon nitride film thereon. An anode electrode pad 37 is formed. Channel stopper area 3
The aluminum electrode 32 extending on 4B has a line width as wide as possible, for example, the electrode pads 35, 3 to reduce the electric resistance as much as possible and to enhance the thermal coupling described later.
It extends with a line width larger than the width of 7.
【００２４】このように、第２のスイッチング手段２内
部に、内蔵ダイオード２Ａとその内蔵ダイオード２Ａと
並列に接続されるショットキバリアダイオードを形成す
ることにより、ＤＣ−ＤＣコンバータ装置の外付部品数
を削減できる。上記した第１、第２のスイッチング手段
１、２、リアクタ３、コンデンサー４は、図４に示すよ
うに、配線基板５上に形成された回路パターン６に接続
されＤＣ−ＤＣコンバータ装置が提供される。この実施
形態では、配線基板５上に実装する第１、第２のスッチ
ング素子は樹脂モールドされているが、半導体チップを
直接、ダイボンディングし周辺の回路パターン等にワイ
ヤでボンディング接続しても良い。As described above, by forming the built-in diode 2A and the Schottky barrier diode connected in parallel with the built-in diode 2A inside the second switching means 2, the number of external parts of the DC-DC converter device can be reduced. Can be reduced. As shown in FIG. 4, the first and second switching means 1 and 2, the reactor 3, and the capacitor 4 are connected to a circuit pattern 6 formed on a wiring board 5 to provide a DC-DC converter device. You. In this embodiment, the first and second switching elements mounted on the wiring board 5 are resin-molded. However, the semiconductor chip may be directly die-bonded and connected to a peripheral circuit pattern or the like by a wire. .
【００２５】ところで、ＳＢＤ素子の順方向立ち上がり
電圧ＶFは、温度に対して−２ｍＶ／℃程度の温度特性
を持ち、高温の方が電圧ＶFが小さい。従って、ＭＯＳ
ＦＥＴとＳＢＤとを１チップ化することにより、ＭＯＳ
ＦＥＴ素子２３のＯＮ動作時の発熱が同一チップに形成
されるＳＢＤ素子２４に瞬時に伝導し、ＳＢＤ素子２４
が加熱されるので、図１に示したＤＣ−ＤＣコンバータ
回路の第１のスイッチング手段１をＯＦＦし、第２にス
イッチング手段２をＯＮした時、第２のスイッチング手
段２のＭＯＳＦＥＴ素子２３の内蔵ダイオード、及びＳ
ＢＤ素子２４に順方向電流が流れる。Incidentally, the forward rise voltage VF of the SBD element has a temperature characteristic of about -2 mV / ° C. with respect to the temperature, and the voltage VF is smaller at a higher temperature. Therefore, MOS
By integrating FET and SBD into one chip, MOS
Heat generated during the ON operation of the FET element 23 is instantaneously transmitted to the SBD element 24 formed on the same chip, and the SBD element 24
Is heated, so that when the first switching means 1 of the DC-DC converter circuit shown in FIG. 1 is turned off and the second switching means 2 is turned on, the built-in MOSFET element 23 of the second switching means 2 Diode and S
A forward current flows through the BD element 24.
【００２６】その後、第１のスイッチング手段１に同期
させて第２のスイッチング手段２をＯＦＦし、ＯＦＦか
らＯＮ動作させるときであっても、第２のスイッチング
手段２に内蔵されたＳＢＤ素子２４の順方向電圧ＶF
は、上記したように、ＭＯＳＦＥＴ素子２３の発熱によ
り、更に低減化されるために、ＭＯＳＦＥＴ素子２３内
部の蓄積キャリアはＳＢＤ素子により瞬時に引き抜いて
完全遮断化を促進することになる。Thereafter, even when the second switching means 2 is turned off in synchronization with the first switching means 1 and turned on from the OFF state, the SBD element 24 built in the second switching means 2 is turned off. Forward voltage VF
As described above, since the heat generated by the MOSFET element 23 is further reduced, the accumulated carriers inside the MOSFET element 23 are instantaneously pulled out by the SBD element to promote complete shutoff.
【００２７】従って、同期整流型のＤＣ−ＤＣコンバー
タ装置の第２のスッチング手段２に上記のＭＯＳＦＥＴ
とＳＢＤとを内蔵した半導体素子を用いることで、ＭＯ
ＳＦＥＴ２３のスイッチングを高速にすることができ
る。また、ＤＣ−ＤＣコンバータ装置の第２のスイッチ
ング手段をＭＯＳＦＥＴ素子２３とＳＢＤ素子２４とに
１チップ化することにより、ＳＢＤを内蔵しているにも
係わらず、第２のスイッチング手段のサイズを最小限と
することができ、実装される配線基板を小型化にでき
る。Therefore, the above-mentioned MOSFET is provided in the second switching means 2 of the synchronous rectification type DC-DC converter device.
The use of a semiconductor device having a built-in SBD and
The switching speed of the SFET 23 can be increased. Further, by integrating the second switching means of the DC-DC converter into one chip of the MOSFET element 23 and the SBD element 24, the size of the second switching means can be minimized despite the fact that the SBD is built-in. The wiring board to be mounted can be reduced in size.
【００２８】[0028]
【発明の効果】以上に詳述したように、本発明のＤＣ−
ＤＣコンバータ装置によれば、ＤＣ−ＤＣコンバータ装
置の直流入力電源をスイッチングする第１のスイッチン
グ手段と同期してスイッチングする第２のスイッチング
手段に、パワーＭＯＳＦＥＴに内蔵される内蔵ダイオー
ドに並列に接続されるショットキーバリアダイオード
（ＳＢＤ）を同一の半導体基板に形成したパワーＭＯＳ
ＦＥＴを用いることにより、ＭＯＳＦＥＴ内部に形成し
ＳＢＤを形成しているので蓄積キャリアを瞬時に引き抜
いて完全遮断化を促進し、第２のスイッチング手段のＭ
ＯＳＦＥＴの内蔵ダイオードに順方向電流が流れた時で
あっても第２のスイッチング手段のスイッチングを高速
にすることができ、ＤＣ−ＤＣコンバータ回路の更なる
高効率化が可能となり、高性能なＤＣ−ＤＣコンバータ
装置を提供することができる。As described in detail above, the DC-
According to the DC converter device, the second switching unit that switches in synchronization with the first switching unit that switches the DC input power of the DC-DC converter device is connected in parallel to the built-in diode built in the power MOSFET. MOS with Schottky barrier diode (SBD) formed on the same semiconductor substrate
Since the SBD is formed inside the MOSFET by using the FET, the accumulated carriers are instantaneously pulled out to promote complete shutoff, and the M
Even when a forward current flows through the built-in diode of the OSFET, the switching of the second switching means can be performed at high speed, and the efficiency of the DC-DC converter circuit can be further increased, and a high-performance DC -A DC converter device can be provided.
【００２９】また、本発明のＤＣ−ＤＣコンバータ装置
では、第２のスイッチング手段はＭＯＳＦＥＴとＳＢＤ
とが１チップ化されているために、ＳＢＤを内蔵したス
イッチング手段でありながらサイズを縮小できることか
ら配線基板小型化が実現できる。その結果、ＤＣ−ＤＣ
コンバータ装置自体の小型化が可能となり、セット製品
の更なる小型化及び高密度化が可能となる。In the DC-DC converter according to the present invention, the second switching means includes a MOSFET and an SBD.
Since these are integrated into one chip, the size can be reduced even though the switching means has a built-in SBD, so that the wiring board can be downsized. As a result, DC-DC
The converter device itself can be reduced in size, and the set product can be further reduced in size and density.
【図１】本発明を説明するＤＣ−ＤＣコンバータ回路
図。FIG. 1 is a DC-DC converter circuit diagram illustrating the present invention.
【図２】本発明のＤＣ−ＤＣコンバータ装置に用いられ
る半導体素子の断面図。FIG. 2 is a cross-sectional view of a semiconductor element used in the DC-DC converter device of the present invention.
【図３】本発明のＤＣ−ＤＣコンバータ装置に用いられ
る半導体素子の平面図。FIG. 3 is a plan view of a semiconductor element used in the DC-DC converter device of the present invention.
【図４】本発明のＤＣ−ＤＣコンバータ装置の配線基板
の実装図。FIG. 4 is a mounting diagram of a wiring board of the DC-DC converter device of the present invention.
【図５】従来のＤＣ−ＤＣコンバータ回路図。FIG. 5 is a circuit diagram of a conventional DC-DC converter.
【図６】従来のＤＣ−ＤＣコンバータ装置に用いられる
半導体素子の断面図。FIG. 6 is a cross-sectional view of a semiconductor element used in a conventional DC-DC converter device.
【図７】従来のＤＣ−ＤＣコンバータ回路図。FIG. 7 is a circuit diagram of a conventional DC-DC converter.
１：第１のスイッチング手段 ２：第２のスイッチング手段 ２３：パワーＭＯＳＦＥＴ ２Ａ：内蔵ダイオード ２４：ショットキバリアダイオード ３：リアクタ ４：コンデンサー 1: First switching means 2: Second switching means 23: Power MOSFET 2A: Built-in diode 24: Schottky barrier diode 3: Reactor 4: Condenser
Claims (1)
する第１のスイッチング手段と、前記第１のスイッチン
グ手段に同期しＯＦＦ／０Ｎする第２のスイッチング手
段と、前記第１、第２のスイッチング手段に接続され前
記直流入力電源を平滑するリアクタ及び前記リアクタに
一端が接続されたコンデンサーとが配線基板上に実装さ
れ前記直流入力電源を所定の直流出力電源に変換するＤ
Ｃ−ＤＣコンバータ装置において、前記第２のスイッチ
ング手段は、内蔵ダイオードと該内蔵ダイオードに並列
に接続されるショットキーバリアダイオードとを備えた
ＭＯＳＦＥＴであることを特徴とするＤＣ−ＤＣコンバ
ータ装置。1. At least DC input power ON / OFF
A first switching means, a second switching means for turning OFF / 0N in synchronization with the first switching means, a reactor connected to the first and second switching means for smoothing the DC input power supply, and A capacitor having one end connected to the reactor is mounted on a wiring board and converts the DC input power to a predetermined DC output power.
In the C-DC converter device, the second switching means is a MOSFET having a built-in diode and a Schottky barrier diode connected in parallel to the built-in diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29068796A JP3291439B2 (en) | 1996-10-31 | 1996-10-31 | DC-DC converter device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29068796A JP3291439B2 (en) | 1996-10-31 | 1996-10-31 | DC-DC converter device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10136641A true JPH10136641A (en) | 1998-05-22 |
| JP3291439B2 JP3291439B2 (en) | 2002-06-10 |
Family
ID=17759210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29068796A Expired - Fee Related JP3291439B2 (en) | 1996-10-31 | 1996-10-31 | DC-DC converter device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3291439B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004158844A (en) * | 2002-10-15 | 2004-06-03 | Fuji Electric Device Technology Co Ltd | Semiconductor device and method of manufacturing the same |
| WO2007007670A1 (en) * | 2005-07-08 | 2007-01-18 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and electric device |
| WO2007013377A1 (en) * | 2005-07-26 | 2007-02-01 | Matsushita Electric Industrial Co., Ltd. | Semiconductor element and electric device |
| JP2007110869A (en) * | 2005-10-17 | 2007-04-26 | Matsushita Electric Ind Co Ltd | Power converter |
| US7791308B2 (en) | 2005-07-25 | 2010-09-07 | Panasonic Corporation | Semiconductor element and electrical apparatus |
| JP2011083104A (en) * | 2009-10-06 | 2011-04-21 | Rohm Co Ltd | Step-down switching regulator and semiconductor integrated circuit device including the same |
| CN111370490A (en) * | 2020-03-18 | 2020-07-03 | 鑫金微半导体(深圳)有限公司 | Novel N-type silicon-based field effect transistor with performance similar to third-generation semiconductor and processing method |
-
1996
- 1996-10-31 JP JP29068796A patent/JP3291439B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004158844A (en) * | 2002-10-15 | 2004-06-03 | Fuji Electric Device Technology Co Ltd | Semiconductor device and method of manufacturing the same |
| WO2007007670A1 (en) * | 2005-07-08 | 2007-01-18 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and electric device |
| US7751215B2 (en) | 2005-07-08 | 2010-07-06 | Panasonic Corporation | Semiconductor device and electric apparatus having a semiconductor layer divided into a plurality of square subregions |
| US7791308B2 (en) | 2005-07-25 | 2010-09-07 | Panasonic Corporation | Semiconductor element and electrical apparatus |
| WO2007013377A1 (en) * | 2005-07-26 | 2007-02-01 | Matsushita Electric Industrial Co., Ltd. | Semiconductor element and electric device |
| US7964911B2 (en) | 2005-07-26 | 2011-06-21 | Panasonic Corporation | Semiconductor element and electrical apparatus |
| JP2007110869A (en) * | 2005-10-17 | 2007-04-26 | Matsushita Electric Ind Co Ltd | Power converter |
| JP2011083104A (en) * | 2009-10-06 | 2011-04-21 | Rohm Co Ltd | Step-down switching regulator and semiconductor integrated circuit device including the same |
| CN111370490A (en) * | 2020-03-18 | 2020-07-03 | 鑫金微半导体(深圳)有限公司 | Novel N-type silicon-based field effect transistor with performance similar to third-generation semiconductor and processing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3291439B2 (en) | 2002-06-10 |
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