JP2011083104A - Step-down switching regulator and semiconductor integrated circuit device including the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switching regulator for preventing a switching transistor from being deteriorated and damaged even if a second diode element for composing a flywheel diode is open-circuited electrically, and to provide a semiconductor integrated circuit device using the switching regulator. <P>SOLUTION: When the second diode element Ds (flywheel diode) connected to an output terminal 120 of an integrated circuit unit 100a is open-circuited for some reason or other, a detection transistor Tc is turned on to make a noise mask circuit 150 operate. When the noise mask circuit 150 operates, supply of a signal S1 (PWM drive signal) to the switching transistor Tsw from a PWM circuit 160 via a logic circuit 170 and a level shift circuit 180 is stopped. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

The present invention relates to a step-down switching regulator and a semiconductor integrated circuit device including the same.

Conventionally, switching regulators that include a so-called overvoltage protection circuit and a breakdown prevention circuit are known.

Japanese Patent Laid-Open No. 10-136641 discloses a synchronous rectification type DC-DC converter device. FIG. 4 is a circuit diagram of the DC-DC converter shown in Patent Document 1 and FIG. The DC-DC converter includes a first switching unit 1 and a second switching unit 2 connected to the first switching unit 1 and switching in synchronization with the first switching unit. The second switching means 2 includes a MOSFET element 23, a built-in diode 2A, and a Schottky barrier diode element 24, and the built-in diode element 2A and the Schottky barrier diode element 24 are connected in parallel. When the first switching means 1 is off, the second switching means 2 is turned on, and the regenerative current of the reactor 3 connected to the current path flows in a loop of the capacitor 4, the built-in diode element 2A, and the reactor 3, and the MOSFET Carriers (electrons) are accumulated in the built-in diode element 2 </ b> A formed inside the element 2.

A Schottky barrier diode (SBD) 24 is connected in parallel with the built-in diode element 2A. Utilizing the fact that the forward rising voltage VF of the SBD 24 is lower than that of the PN diode, the switching speed of the entire circuit is improved to increase the efficiency of the DC-DC converter.

Patent Document 2 (Japanese Patent Laid-Open No. 8-80034) provides a switching power supply device that can detect an open load. In order to detect the lamp burnout of the load, etc., it detects that the load has been released by detecting the drive pulse width given to the switching element and the current flowing through the main circuit, and the load release is detected. And the operation of the switching power supply is stopped.

The switching power supply control semiconductor device disclosed in Patent Document 3 (Japanese Patent Application Laid-Open No. 2003-274644) is caused by an abnormality such as deterioration or destruction of an external connection component that gives a feedback signal for switching control of a switching element to a control terminal. When the control terminal and external connection parts are in the open state, the feedback signal to the control terminal is cut off, and the current does not flow out from the control terminal, the switching operation is stopped, this stopped state is maintained, and the switching is stopped. This is to prevent destruction of the power supply device.

Patent Document 4 (Japanese Patent Laid-Open No. 10-229638) provides a switching power supply device having a function of detecting a load release and a failure of a power supply device and determining which failure is caused.

In Patent Document 5 (Japanese Patent Laid-Open No. 2001-286127), in a switching regulator, when a load is released due to some trouble, the voltage at a predetermined terminal connected to the load drops, and the difference between the voltage at the predetermined terminal and the reference voltage is 0V. The PWM control circuit operates to prevent the various elements including the switching elements from being deteriorated or destroyed.

JP-A-10-136641 JP-A-8-80034 JP 2003-274644 A JP-A-10-229638 JP 2001-286127 A

Patent Document 1 relates to a DC-DC converter, which uses a Schottky barrier diode whose forward rising voltage VF is lower than that of a PN diode to improve switching speed and increase power consumption efficiency. Patent Documents 2 to 5 relate to a device that eliminates a problem that may occur when a load or an external connection component of a semiconductor integrated circuit device is in an open state.

The present invention relates to the technical fields of Patent Documents 1 to 5, and is destroyed so that the switching regulator is not deteriorated or destroyed when the Schottky barrier diode as a flywheel diode falls into an open state for some reason. A switching regulator having a prevention function is provided. The present invention also provides a semiconductor integrated circuit device including the switching regulator.

The step-down switching regulator of the present invention
(A) a switching transistor having a first main electrode, a second main electrode, and a control electrode, which is turned on and off in response to a pulse drive signal supplied to the control electrode;
(B) a power supply voltage input terminal connected to the first main electrode of the switching transistor;
(C) an output terminal to which the second main electrode of the switching transistor is connected;
(D) an inductor having one end connected to the output terminal;
(E) a capacitor having one end connected to the other end of the inductor and the other end connected to a ground potential terminal;
(F) a power supply voltage output terminal connected to a common connection point between the other end of the inductor and one end of the capacitor;
(G) a first diode element having a cathode connected to the output terminal and an anode connected to the ground potential terminal;
(H) a second diode element having a cathode connected to the output terminal, an anode connected to the ground potential terminal, and connected in parallel with the first diode element;
(I) comprising a detection transistor having a first main electrode from which a detection signal is extracted, a second main electrode connected to the output terminal, and a control electrode connected to the ground potential terminal;
(J) The detection transistor is turned on when the potential between the ground potential terminal and the output terminal is higher than the forward rising voltage between the anode and the cathode of the first diode element. Is to turn off the operation.

In addition, the step-down switching regulator according to the present invention has a detection transistor that transitions from OFF to ON when the potential of the output terminal becomes lower than the potential of the ground potential terminal exceeding the forward rising voltage of the first diode element. To do.

  In addition, the detection transistor included in the step-down switching regulator according to the present invention transitions from OFF to ON because the second diode element falls into an electrically open state from the conductive path between the output terminal and the ground potential terminal. When

  The first diode element included in the step-down switching regulator according to the present invention is a PN junction diode, and the second diode element is a Schottky barrier diode.

  Further, the forward rising voltage of the first diode element included in the step-down switching regulator according to the present invention is larger than that of the second diode element.

Another aspect of the invention is a semiconductor integrated circuit device,
(A) a switching transistor in which a first main electrode, a second main electrode, and a control electrode are formed on a semiconductor substrate, a predetermined DC power supply voltage is supplied to the first main electrode, and a pulse drive signal is supplied to the control electrode; ,
(B) an output terminal to which the second main electrode of the switching transistor is connected;
(C) a first diode element formed on a semiconductor substrate together with a switching transistor having a cathode connected to the output terminal and an anode connected to the ground potential terminal;
(D) a second diode element having a cathode connected to the output terminal, an anode connected to the ground potential terminal, prepared separately from the semiconductor substrate, and connected in parallel with the first diode element; ,
(E) a detection transistor formed on a semiconductor substrate and having a first main electrode from which a detection signal is extracted, a second main electrode connected to the output terminal, and a control electrode connected to the ground potential terminal; ,
With
(F) When the potential of the output terminal becomes lower than the potential of the ground potential terminal exceeding the forward rising voltage of the first diode element, the detection transistor transitions from off to on and turns off the operation of the switching transistor. This is a semiconductor integrated circuit device.

In the step-down switching regulator of the present invention, when the flywheel diode connected to the output terminal falls into an open state for some reason, the detection transistor is turned on and the supply of the PWM drive signal to the switching transistor is stopped. And other circuit elements can be prevented from being deteriorated or destroyed.

  Further, if the switching regulator of the present invention is constituted by a semiconductor integrated circuit device, a part of the first diode element provided for electrostatic discharge can be used also as a part of the detection transistor, so that it is relatively simple. The circuit configuration can be achieved without increasing the number of integrated circuit elements.

In addition, since the semiconductor integrated circuit device in which the switching regulator of the present invention is built actively uses a parasitic transistor formed between the semiconductor substrate and the first diode element, the number of integrated circuits is not increased. In addition, the switching regulator can be configured as a semiconductor integrated circuit device.

1 shows a circuit of a switching regulator according to an embodiment of the present invention. The operation state when the flywheel diode of the switching regulator concerning the 1st Embodiment of this invention falls into an open state is shown. 1B shows a timing chart according to the first embodiment of the present invention shown in FIG. 1A. 1B is a timing chart when the flywheel diode shown in FIG. 1B falls into an open state. 1 shows a semiconductor integrated circuit device according to the present invention. An example of the conventional switching regulator is shown.

(First embodiment)
1A and 1B show a step-down switching regulator according to the present invention. The step-down switching regulator outputs an output power supply voltage VOUT lower than the input power supply voltage VIN. FIG. 1A shows a switching regulator 100A during normal operation, and FIG. 1B shows a so-called abnormal switching regulator 100B when a second diode element Ds described later, that is, a Schottky barrier diode falls into an open state.

A step-down switching regulator 100A shown in FIG. 1A is roughly composed of an integrated circuit unit 100a, a smoothing circuit 100b, and a control circuit 100c.

A power supply voltage input terminal 110, an output terminal 120, and a ground potential terminal 130 are prepared in the integrated circuit unit 100a. An input power supply voltage VIN is supplied to the power supply voltage input terminal 110. The magnitude of the input power supply voltage VIN is, for example, a DC voltage of 42V. The output terminal 120 takes out the output voltage output from the integrated circuit unit 100a. A smoothing circuit 100b is connected to the output terminal 120 and is displayed as a node N2. The ground potential terminal 130 is maintained at 0 potential, that is, the potential GND.

A switching transistor Tsw, a detection transistor Tc, a first diode element D, and a resistor R are built in the integrated circuit unit 100a. The transistor Tp is a so-called parasitic transistor formed when the switching transistor Tsw is formed on a P-type semiconductor substrate. The detection transistor Tc is used in the smoothing circuit 100b and has a role of detecting whether the flywheel diode (second diode element Ds) is normally connected or is in an electrically open state.

The first diode element D is originally prepared for electrostatic discharge (ESD). That is, when, for example, a pulse voltage of minus 0.7 V or less arrives at the output terminal 120, the first diode element D is turned on, and various semiconductor elements connected to the output terminal 120 are deteriorated or destroyed. It has a role to prevent this. Here, the magnitude of 0.7 V indicates the rising voltage in the forward direction of the first diode element D. The first diode element D also performs an alternative operation when the second diode element Ds is brought into an electrically open state. Note that the first diode element D is not limited to the purpose of electrostatic discharge (ESD), but may be configured as a built-in diode 2A incorporated in the MOSFET element 23 as shown in FIG. 1A and 1B show an asynchronous step-down switching regulator, but when a synchronous step-down switching regulator is configured, the power supply voltage input terminal 120 and the ground potential terminal 130 are connected between conductive paths. Since a synchronization transistor (not shown) is connected in series with the switching transistor Tsw, it is equivalent to the first diode element D between the source or drain of the synchronization transistor and the P-type semiconductor substrate. A diode is formed.

A specific configuration when the integrated circuit portion 100a is formed on the semiconductor substrate will be clarified by FIG. 3 and the description thereof to be described later. First, referring to FIG. 1A, the circuit configuration of the switching regulator 100A and its configuration The operation will be described.

The switching transistor Tsw includes a first main electrode 101, a second main electrode 102, and a control electrode 103. The switching transistor Tsw may be either a MOS transistor or a bipolar transistor. When the switching transistor Tsw is an N-channel MOS transistor, the first main electrode 101 corresponds to the drain, the second main electrode 102 corresponds to the source, and the control electrode 103 corresponds to the gate. Further, when the switching transistor Tsw is a P-channel type, the control electrode 103 does not change to be a gate, but the first main electrode 101 corresponds to the source and the second main electrode 102 corresponds to the drain, respectively. The relationship between the electrode and the second main electrode is reversed. The N channel type MOS transistor can be replaced with an NPN type bipolar transistor, and the P channel type MOS transistor can be replaced with a PNP type bipolar transistor. In this case, the drain, source, and gate are replaced with the collector, emitter, and base, respectively.

When the switching transistor Tsw is turned on, the output current ia1 is supplied from the input power supply voltage terminal 110 to the inductor L which is an inductive load. When the switching transistor Tsw is turned off, it does not immediately become 0 due to the nature of the inductor L, and the regenerative current ia2 flows from the ground potential terminal 130 via the second diode element Ds. The second diode element Ds having such an action is usually called a flywheel diode.

The detection transistor Tc serves as a detection for preventing breakdown according to the present invention. That is, whether the switching regulator 100a according to the present invention is in a normal state or an abnormal state depends on whether the detection transistor Tc is in an off state or an on state. When the detection transistor Tc is in the off state for a predetermined time, the switching regulator 100A is normally operated, and when the detection transistor Tc is in the on state, it is determined to be in an abnormal state. The abnormal state is explained by FIG. 1B and FIG. 2B described later.

The first main electrode 101 of the switching transistor Tsw is connected to the power supply voltage input terminal 110 and supplied with the input power supply voltage VIN. The magnitude of the input power supply voltage VIN is, for example, 42V. The second main electrode 102 of the switching transistor Tsw is connected to the node N2, that is, the output terminal 120. One end of the inductor L constituting the smoothing circuit 100b, the cathode of the first diode element D, and the cathode of the second diode element Ds are commonly connected to the output terminal 120. The other end of the inductor L is commonly connected to the power supply voltage output terminal 140, one end of the capacitor C, and one end of the feedback resistor Ra. The second diode element Ds has a Schottky barrier structure and functions as a flywheel diode. That is, the second diode element Ds is prepared for supplying the regenerative current ia2 to the inductor L when the switching transistor Tsw is off.

Feedback resistors Ra and Rb are connected in series between the power supply voltage output terminal 140 and the ground terminal 130. A feedback voltage 162 corresponding to the resistance division ratio and the output voltage VOUT is generated at the common connection point of these two feedback resistors. The feedback voltage 162 is fed back to the PWM circuit 160 described later, and the output voltage VOUT output to the power supply voltage output terminal 140 is controlled to a predetermined magnitude.

The control electrode 103 of the switching transistor Tsw is displayed as a node N1, and is supplied with a signal S1, that is, a PWM drive signal. The PWM drive signal is a so-called PWM (Pulse Width Modulation) signal whose pulse width changes with time. The on / off operation of the switching transistor Tsw is responsive to the PWM drive signal. The second main electrode 102 of the switching transistor Tsw, that is, the output terminal 120, outputs a signal S2 having a magnitude substantially equal to the PWM drive signal (signal S1) supplied to the control electrode 103. The signal S2 is referred to as a switching signal in this document and is distinguished for convenience from the signal S1, that is, the PWM drive signal.

The signal S1 is supplied from the control circuit 100c to the control electrode 103 of the switching transistor Tsw. Originally, the signal is the same as the PWM input signal 160a supplied from the PWM circuit 160 and the PWM output signal 170a output from the logic circuit 170. is there. A drive signal is supplied. In addition to pulse width modulation (PWM (Pulse Width Modulation)), the switching regulator according to the present invention includes pulse frequency modulation (PFM (Pulse Width Modulation)).
Frequency Modulation) and pulse amplitude modulation (PAM (Pulse Amplitude)
Modulation)) or the like can be applied.

The smoothing circuit 100b includes a series connection body of an inductor L and a capacitor C and a second diode element Ds. The inductance of the inductor L is 68 mH, for example, and the capacitance of the capacitor C is selected to be 220 μF, for example. This series connection body is connected in series with the switching transistor Tsw via the output terminal 120 and is provided between the power supply voltage input terminal 110 and the ground potential terminal 130. The cathode of the second diode element Ds is connected to the output terminal 120, and the anode thereof is connected to the ground potential terminal 130. A common connection point between the inductor L and the capacitor C is connected to the power supply voltage output terminal 140, and a DC output power supply voltage VOUT of, for example, 12V lower than the input power supply voltage VIN is output to the power supply voltage output terminal 140. The step-down switching regulator outputs an output power supply voltage VOUT smaller than the input power supply voltage VIN.

In the integrated circuit unit 100a, the first main electrode (collector) 111 of the detection transistor Tc is connected to the node N3. A resistor R is connected between the node N3 and the power supply voltage Vcc. That is, a resistor R is prepared as a collector load for the detection transistor Tc. The magnitude of the power supply voltage Vcc is much smaller than the magnitude of the input power supply voltage VIN, for example, 3.3V or 5V. The resistor R is made of, for example, polysilicon, and the resistance value is, for example, about 100 KΩ. In addition, as a load of the detection transistor Tc, a transistor or a diode may be connected in series or in parallel with the resistor R. The second main electrode (emitter) 112 of the detection transistor Tc is connected to the output terminal 120, and its control electrode (base) 113 is connected to the ground potential terminal 130, that is, the ground potential GND.

Usually, since the potential of the control electrode 113 (base) is the ground potential, that is, 0 V, the detection transistor Tc is placed in the off state. The detection transistor Tc is turned on when the potential of the second main electrode 112, that is, the output terminal 120 is set to minus 0.7V or less. However, when the switching regulator 100A is operating normally, the potential of the output terminal 120 is not placed below minus 0.7V. This is because the second diode element Ds is connected between the output terminal 120 and the ground potential terminal 130, and the forward rising voltage of the second diode element Ds is equal to the forward rising voltage 0 of the first diode element D. 0.2V to 0.3V lower than 0.7V, and when the potential of the output terminal 120 is set to minus 0.2 to 0.3V, the second diode element Ds is applied to the second diode element Ds before the detection transistor Tc is activated. This is because current flows.

The noise mask circuit 150 is prepared for filtering or masking the signal S3 output to the node N3. When negative static electricity having a very small spike-like pulse width, for example, arrives at the output terminal 120, the detection transistor Tc is turned on, so that the signal S3 appears at a node N3 within a relatively short time. Since this state is different from the state in which the second diode element Ds is in an open state, that is, the signal S3 always appears at the node N3, both states must be distinguished. The noise mask circuit 150 is prepared for distinguishing these states. That is, when the pulse width of the signal S3 is within a predetermined time range, the logic circuit 170 at the subsequent stage is not controlled.

A relatively simple circuit configuration for configuring the noise mask circuit 150 is to employ an integration circuit composed of a resistor and a capacitor. A pulse signal component smaller than a predetermined pulse width can be attenuated by appropriately setting the time constants of the resistor and the capacitor. Also, the integration circuit and the comparator are combined, a predetermined reference potential is applied to one input terminal of the comparator, a signal output from the integration circuit is applied to the other input terminal, and output from the output terminal of the comparator. The circuit operation of the logic circuit 170 may be controlled based on the signal. In addition, the noise mask circuit 150 can include at least one of a D flip-flop, a logical product circuit, a negative logical product circuit, a logical sum circuit, a negative logical sum circuit, and the like. For example, when a D flip-flop is used, when noise shorter than the period of the clock signal input to the D flip-flop is output, the noise mask circuit 150 masks the signal so that no signal appears at the node N4. Can do. In any case, the purpose of preparing the noise mask circuit 150 is that when the time width of the signal S3 output to the node N3 is within a predetermined time range, they are regarded as noise and the subsequent circuit is not controlled. It is for doing so.

The control circuit 100c includes a PWM circuit 160, a logic circuit 170, and a level shift circuit 180. The PWM circuit 160 generates a PWM input signal 160a having a frequency of 200 KHz to 1 MHz, for example. The logic circuit 170 is composed of, for example, a logical product (AND) circuit. The logic circuit 170 is supplied with a PWM input signal 160a and a signal S4 as a noise mask signal. In a normal operation state, that is, a normal operation state, the signal S4 is at a high level, and the same signal as the PWM input signal 160a is output from the logic circuit 170 as the PWM output signal 170a. Therefore, when in a normal operation state, that is, when the noise mask circuit 150 is not operating, the PWM output signal 170a supplied from the logic circuit 170 is equal to the PWM input signal 160a. The level shift circuit 180 is prepared to generate a signal S1, which is set to a voltage level sufficient to drive the switching transistor Tsw, that is, a PWM drive signal.

FIG. 1B schematically shows a circuit operation state when the second diode element Ds attached to the outside of the integrated circuit portion 100a, that is, the Schottky barrier diode is electrically opened for some reason. Reference symbol X indicates an open position. For convenience of explanation, the reference symbol X indicates that the cathode of the second diode element Ds is in an open state, but the anode may be in an open state. It is also possible for both the cathode and the anode to fall open.

When the second diode element Ds is disconnected from the conductive path between the output terminal 120 and the ground potential terminal 130 and is electrically opened, the first diode element D functions as a substitute for the second diode element. . That is, the first diode element D functions as a flywheel diode. Since the first diode element D is a silicon-based PN junction diode, the forward rising voltage VF is about 0.7V. However, the functions of the first diode element D and the second diode element Ds are not exactly equivalent. This is because the first diode element D is a silicon-based PN junction diode, so that the forward rising voltage VF is larger than that of the second diode element Ds having the Schottky barrier structure. While the second diode element Ds is operating normally, the potential of the output terminal 120 does not fall below the potential rising voltage of the second diode element Ds below the potential GND of the ground potential terminal 130. For example, if the forward rising voltage of the second diode element Ds is 0.2V, the potential of the output terminal 120 does not drop below −0.2V. However, when the second diode element Ds is opened and the first diode element D operates instead, the potential of the output terminal 120 is set to minus 0.7V. When the potential of the output terminal 120 becomes minus 0.7 V, a parasitic transistor effect occurs between the regions formed on the semiconductor substrate.

When the potential of the output terminal 120 reaches minus 0.7 V, an NPN-type parasitic transistor formed between the first main electrode 101, the second main electrode 102, and the ground potential terminal 130 (GND) of the switching transistor Tsw. Tp is activated. When the parasitic transistor Tp is activated, the parasitic current ib3 is transmitted from the power supply voltage input terminal 110 to the first main electrode and the second main electrode of the parasitic transistor Tp, that is, between the collector and the emitter, and via the output terminal 120. A parasitic current ib3 flows toward the inductor L. Such a parasitic current ib3 accelerates the heat generation of the integrated circuit portion 100a itself. This further increases the parasitic current ib3 flowing through the parasitic transistor Tp, leading to acceleration of deterioration or destruction of the semiconductor integrated circuit device 100B.

When the potential of the output terminal 120 reaches minus 0.7V, the detection transistor Tc is turned on. When the detection transistor Tc is turned on, the potential Vn3 of the node N3 becomes equal to the potential Vn2 of the node N2. That is, Vn3 = −0.7V.

The noise mask circuit 150 used in FIG. 1B is exactly the same as that shown in FIG. 1A. Therefore, the noise mask circuit 150 responds to the signal S3. That is, when the signal S3 transitions from the high level to the low level, the noise mask circuit 150 operates. However, the output of the noise mask circuit 150, that is, the potential of the signal S4 appearing at the node N4 is changed to the low level only when the low level of the signal S3 is maintained for a predetermined time. Once the signal S4 is maintained at a low level, it is then latched at a low level, for example. That is, the noise mask circuit 150 includes a latch function.

When the output signal of the noise mask circuit 150, that is, the signal S4 is maintained at a low level, the PWM output signal 170a output from the logic circuit 170 is maintained at a low level. The PWM output signal 170a is obtained by extracting the PWM input signal 160a supplied from the PWM circuit 160 through the logic circuit 170. However, when the signal S4 is set at the low level, the high level and the low level are set during normal operation. The alternating PWM output signal 170a is maintained only at a low level.

When the PWM output signal 170a is maintained at the low level, the signal S1, that is, the PWM drive signal output from the level shift circuit 180 is maintained at the low level until the latch is released. As a result, the switching transistor Tsw is kept off so as not to be turned on from off. At this time, since the potential of the node N2, that is, the output terminal 120 is gradually shifted to the ground potential GND, the parasitic transistor Tp is switched from on to off. Along with this, the flow of the parasitic current ib3 is interrupted, so that a problem that each circuit element is deteriorated or destroyed can be eliminated.

For convenience of explanation, the control circuit 100c is illustrated as being different from the integrated circuit portion 100a in FIG. 1B; however, the control circuit 100c can be formed on the same semiconductor substrate as the integrated circuit portion 100a.

FIG. 2A schematically shows a signal at each node when the switching regulator 100A shown in FIG. 1A is operating normally. The signal S1 indicates a PWM drive signal supplied to the node N1, that is, the control electrode 103 of the switching transistor Tsw. The signal S1 is a so-called PWM signal whose pulse width changes with the lapse of time t, but is simply shown for convenience of drawing. The signal S1 is supplied from the PWM circuit 160 shown in FIG. 1A to the node N1 through the logic circuit 170 and the level shift circuit 180.

The signal S2 indicates a switching signal output to the second main electrode 102 of the switching transistor Tsw, that is, the node N2 (output terminal 120). The signal S2 is substantially the same signal as the signal S1, that is, the PWM drive signal, but is expressed as a signal indicated by a negative potential Vn2L whose low level is lower than 0 potential. This is because the inductor L is connected to the output terminal 120, that is, the node N2. Even when the switching transistor Tsw is switched from on to off, the second diode element Ds (flywheel) is supplied to supply energy to the inductor L. This is because a so-called regenerative current ia2 continues to flow to the inductor L via the diode).

The signal S3 indicates a detection signal output to the node N3, that is, the first main electrode 111 of the detection transistor Tc. In other words, the signal S3 serves as a signal that informs the presence or absence of the open state of the second diode element Ds. When the signal S3 is at a high level, it indicates that the second diode element Ds is in a normal state, that is, not in an open state. Of course, the signal S3 may be taken out at a low level when the second diode element Ds falls into an open state.

A signal S4 indicates a noise mask signal extracted to the node N4. The noise mask signal is set so as to respond to the signal S3 extracted from the node N3, and when the signal S3 is at a high level, for example, the signal S4 is at a high level. In the signals S3 and S4, the relationship between the high level and the low level of both can be set as needed. For example, the signal S4 may be set to a low level when the signal S3 is at a high level. Of course, this may be reversed. That is, the signal S4 may be set to be at a high level when the signal S3 is at a low level.

FIG. 2B schematically shows each signal appearing at each node when the switching regulator 100B shown in FIG. 1B, that is, the second diode element Ds is electrically opened.

The signal S1 indicates a PWM drive signal supplied to the node N1, that is, the control electrode 103 of the switching transistor Tsw. Although the pulse width of the PWM drive signal (signal S1) changes with the lapse of time t, it is simply shown for convenience of drawing. The signal S1 is supplied from the PWM circuit 160 shown in FIG. 1B to the node N1 through the logic circuit 170 and the level shift circuit 180.

Focusing on the signal S1, it can be seen that a high level is output from time t1 to t2 and a normal operating state is exhibited. After the time t2, it shows a state where the regular PWM drive signal is not output while being fixed at the low level. That is, the second diode element Ds is in an electrically open state.

The signal S2 indicates a switching signal output to the second main electrode 102 of the switching transistor Tsw, that is, the node N2 (output terminal 120). The switching signal is substantially the same as the signal S1 appearing at the node N1, that is, the PWM drive signal, but exhibits a negative potential Vn2Lb whose low level is lower than 0 potential from time t0 to time t1, and is low after time t2. It exhibits a negative potential Vn20L whose level is lower than 0 potential. First, from time t0 to time t1, the second diode element Ds is not open and is operating normally. Therefore, even when the switching transistor Tsw is switched from on to off, energy must be supplied due to the nature of the inductor L. In order to supply this energy, a so-called regenerative current ia2 flows to the inductor L via the second diode element Ds (flywheel diode). Thereby, from time t0 to time t1, the low level exhibits a negative potential Vn2Lb lower than the zero potential. The potential Vn2Lb is determined by the forward rising voltage between the anode and the cathode of the second diode element D. If the rising voltage in the forward direction of the second diode element Ds is 0.2V, for example, the potential Vn2Lb is approximately minus 0.2V.

After time t2, the second diode element Ds is in an open state, that is, an abnormal operation state. Therefore, when the switching transistor Tsw switches from on to off, energy must be supplied due to the nature of the inductor L as in the case of the times t0 to t1, and therefore the second diode element Ds (flywheel diode) is used instead of the second diode element Ds. A so-called regenerative current ib2 is supplied to the inductor L through one diode element D. For this reason, after time t2, the low level has a negative potential Vn20L lower than 0 potential. The potential Vn20L is determined by the forward rising voltage between the anode and the cathode of the first diode element D, and its magnitude is, for example, minus 0.7 V, which is 0 as compared to when the second diode element Ds is operating. About 5V is reduced. Note that the potential Vn20L gradually approaches the ground potential 0 V after the time t4.

The signal S3 indicates a detection signal output to the node N3, that is, the first main electrode 111 of the detection transistor Tc. In other words, the detection signal serves as a signal notifying whether or not the second diode element Ds is open. The signal S3 exhibits a high level from time t0 to time t2, and transitions from a high level to a low level at time t2. When the time t3 has elapsed and the time t4 is reached, the signal S3 transitions to the high level again. This is because the potential of the output terminal 120 has returned to the ground potential, that is, 0 V again, and the detection transistor Tc has been placed in the off state.

Signal S4 represents the noise mask signal extracted at node N4. The signal S4 is set to be at a high level when the signal S3 is at a high level. The level relationship between the signals S3 and S4 can be set at any time. For example, the signal S4 may be set to a low level when the signal S3 is at a high level. Of course, the reverse is also possible. That is, the signal S4 may be set to be at a high level when the signal S3 is at a low level.

Signal S4 responds to signal S3 from time t0 to time t2. That is, the signals S3 and S4 exhibit the same behavior. However, it can be seen that the time t2 has passed and the signal S3 is not responded at the time t3 and the time t4. When the detection transistor Tc changes to the on state at time t2, the signal S3 changes from the high level to the low level. The fact that the detection transistor Tc has entered the on state suggests that the second diode element Ds has fallen into an open state. Therefore, the noise mask circuit 150 should respond to the detection transistor Tc and immediately change the operation state. However, the signal S4 (noise mask signal) is still kept at the high level from time t2 to time t3. In other words, the operation state is not reversed for a predetermined time between the operation of the detection transistor Tc and the operation of the noise mask circuit 150, that is, a time lag is provided. The reason for providing such a time lag is to accurately distinguish whether the second diode element Ds is truly open or whether it is a pseudo open state. For example, when the detection transistor Tc is turned on by a pulsed noise signal, it is determined that the signal is a signal indicating a pseudo open state, and the noise mask circuit 150 is not controlled.

Referring to signal S4, noise mask time t23 is provided between times t2 and t3. The magnitude of the noise mask time t23 is determined by, for example, the frequency of the PWM drive signal. Alternatively, it is determined in consideration of noise resistance measures applied to the switching regulator, the mounting state of the switching regulator, and the surrounding environment in which the switching regulator is used. Here, the surrounding environment is whether or not it is a place where noise is likely to occur. In consideration of this, the noise mask time t23 is generally selected between several ns and several hundreds ms, for example. However, as the noise mask time t23 is increased, the power consumed by the first diode element D is also increased, and the heat generation of the integrated circuit portion 100a is also not preferable. Therefore, the noise mask time t23 may be determined in consideration of the power consumption of the integrated circuit portion 100a.

(Second Embodiment)
FIG. 3 schematically shows an example in which the switching regulator according to the present invention is configured by a semiconductor integrated circuit device. In the semiconductor integrated circuit device 300, the switching transistor Tsw, the detection transistor Tc, and the first diode element D are configured by a semiconductor integrated circuit device. The second diode element Ds, that is, the Schottky barrier diode is prepared outside the semiconductor integrated circuit device 300.

A P-type semiconductor substrate 50 is prepared as a common substrate of the semiconductor integrated circuit device 300, and N-type buried layers 54, 56, and 58 are selectively formed on one main surface 52 of the semiconductor substrate. These buried layers are prepared, for example, to reduce the resistance component interposed between the collector and the emitter of the bipolar transistor. The buried layer is not an essential component for configuring the MOS transistor, but in the present invention, the buried layer is prepared in advance so that the bipolar transistor can be formed at any time.

An N type epitaxial layer 60 is formed on one main surface 52 of the semiconductor substrate 50 and on the buried layers 54, 56 and 58. Epitaxial layer 60 is separated into three island-like regions of island-like regions 64, 66 and 68 by P-type isolation region 62. A switching transistor Tsw is formed in the island region 64, a first diode element D is formed in the island region 66, and a detection transistor Tc is formed in the island region 68. Instead of providing the epitaxial layer 60, various regions of the same conductivity type or different conductivity types may be formed in the N-type well or the P-type well. In this document, the epitaxial layer and the well are collectively referred to as a semiconductor region.

A first P-type region 72 is formed at a predetermined position of the island-shaped region 64 where the switching transistor Tsw is formed, and a first N-type region 74 is formed in the first P-type region 72. . Electrodes 120a and 102a are separately applied to parts of the first P-type region 72 and the first N-type region 74, and these electrodes 120a and 102a are connected in common, and are connected to the node N2, that is, the output terminal 120. Connected. The second N-type region 76 is formed in the island-like region 64 with the first P-type region 72 sandwiched therebetween, facing the first N-type region 74 and at the same depth.

The switching transistor Tsw formed in the island region 64 has a generally well-known LD (Lateral Double Diffused) MOS transistor structure. The first N-type region 74 corresponds to the source of the switching transistor Tsw, and the second N-type region 76 corresponds to the drain thereof. An electrode 101 a is deposited on the second N-type region 76. The electrode 101a corresponds to the first main electrode 101 of the switching transistor Tsw shown in FIG. A first P-type region 72 between the first N-type region 74 and the second N-type region 76 corresponds to the channel region of the switching transistor Tsw. A gate oxide film 78 is formed on the first P-type region 72, and a control electrode 103 a is formed on the gate oxide film 78. The control electrode 103a corresponds to the control electrode 103 of the switching transistor Tsw shown in FIG. It should be noted that other types of transistors, such as general MOS transistors and IGBTs, may be formed in the island regions 64 instead of LDMOS transistors.

The island region 66 is prepared as a formation region of the first diode element D. That is, the second P-type region 82 and the third N-type region 84 are formed in the island-shaped region 66. The second P-type region 82 is formed simultaneously with the first P-type region 72 and at the same depth. The third N-type region 84 is formed simultaneously with the first and second N-type regions 74 and 76. The second P-type region 82 and the third N-type region 84 correspond to the anode and the cathode of the first diode element D, respectively. An electrode 86 is deposited on a part of the second P-type region 82, and the electrode 86 is connected to the ground potential GND, that is, the ground potential terminal 130. An electrode 88 is deposited on a part of the third N-type region 84, and the electrode 88 is connected to the node N2, that is, the output terminal 120 shown in FIG. 1A.

The island area 68 is prepared as a formation area of the detection transistor Tc. In FIG. 3, only the first main electrode 111 of the detection transistor Tc, that is, the fourth N-type region 92 corresponding to the collector is formed, and the second main electrode 112 and the control electrode 113 utilize the existing regions. In other words, the second main electrode 112 and the control electrode 113 respectively use the third N-type region 84 and the semiconductor substrate 50 for forming the first diode element D. An electrode 111 a is deposited on the fourth N-type region 92. The electrode 111a corresponds to the first main electrode (collector) 111 of the detection transistor Tc.

In the configuration in which only the first main electrode, that is, the collector, of the detection transistor Tc is formed in the island region 68, the second main electrode (emitter) 112 of the detection transistor Tc is also used as the cathode of the first diode element D. The area occupied by the detection transistor Tc in the semiconductor substrate 50 can be reduced. Of course, the detection transistor Tc does not use such other regions, but the second main electrode (collector) as well as all the electrodes of the detection transistor Tc, that is, the first main electrode (collector) in the island region 68. An emitter) and a control electrode (base) may be formed. An insulating film 94 such as a silicon oxide film is formed on one main surface 60 a of epitaxial layer (semiconductor region) 60.

When the second main electrode 112 of the detection transistor Tc is also used as the cathode of the first diode element D, the third N-type region 84 and the fourth N-type region 92 may be provided as close as possible. As a result, the transistor characteristics of the detection transistor Tc are enhanced, and a transistor operation substantially equivalent to that of a normal transistor can be obtained.

With the above configuration, the integrated circuit portion 100a capable of detecting the open state of the second diode element Ds (Schottky barrier diode) used in the smoothing circuit 100b of the step-down switching regulator can be configured on the same semiconductor substrate.

The present invention prevents a switching transistor or a semiconductor integrated circuit device including the switching transistor from being deteriorated or destroyed by a detection transistor that detects an open state when a flywheel diode constituting a smoothing circuit falls into an open state for some reason. Since the switching regulator and the semiconductor integrated circuit device having the switching regulator can be provided, the industrial applicability is extremely high.

50 Semiconductor substrate 52 One main surface 54, 56, 58 of semiconductor substrate Embedded layer 60 Epitaxial layer (semiconductor region)
62 P-type isolation regions 64, 66, 68 Island-like region 72 First P-type region 74 First N-type region 76 Second N-type region 78 Gate oxide film 82 Second P-type region 84 Third N Type region 86, 88, 101a, 111a, 102a, 120a Electrode 92 Fourth N type region 94 Insulating film 100A, 100B Switching regulator 100a Integrated circuit unit 100b Smoothing circuit 100c Control circuit 101, 111 First main electrode
102, 112 Second main electrodes 103, 103a, 113 Control electrode 110 Power supply voltage input terminal 120 Output terminal 130 Ground potential terminal 140 Power supply voltage output terminal 150 Noise mask circuit 160 PWM circuit 160a PWM input signal 162 Feedback voltage 170 Logic circuit 170a PWM Output signal 180 Level shift circuit 300 Semiconductor integrated circuit device C Capacitor D First diode element Ds Second diode element (Schottky barrier diode)
L Inductors N1, N2, N3, N4 Node R Resistors S1, S2, S3, S4 Signal Tsw Switching transistor Tc Detection transistor Tp Parasitic transistor

Claims (18)

A switching transistor having a first main electrode, a second main electrode, and a control electrode, which is turned on and off in response to a pulse drive signal input to the control electrode;
A power supply voltage input terminal connected to the first main electrode of the switching transistor;
An output terminal to which a second main electrode of the switching transistor is connected;
An inductor having one end connected to the output terminal;
A capacitor having one end connected to the other end of the inductor and the other end connected to a ground potential terminal;
A power supply voltage output terminal connected to a common connection point between the other end of the inductor and one end of the capacitor;
A first diode element having a cathode connected to the output terminal and an anode connected to the ground potential terminal;
A cathode connected to the output terminal, an anode connected to the ground potential terminal, and a second diode element connected in parallel with the first diode element;
A detection transistor having a first main electrode from which a detection signal is extracted, a second main electrode connected to the output terminal, and a control electrode connected to the ground potential terminal;
With
The detection transistor is turned on when the potential difference between the ground potential terminal and the output terminal becomes larger than the forward rising voltage between the anode and the cathode of the first diode element, and the switching transistor operates. Step-down switching regulator that turns off the power.   2. The step-down switching regulator according to claim 1, wherein the pulse drive signal is a signal composed of PWM, PFM, or PAM.   The detection transistor transitions from off to on when the conductive path between the output terminal and the ground potential terminal of the second diode element falls into an electrically open state. The step-down switching regulator described.   2. The step-down switching regulator according to claim 1, wherein the first diode element is a PN junction diode, and the second diode element is a Schottky barrier diode.   2. The step-down switching regulator according to claim 1, wherein a forward rising voltage of the first diode element is larger than that of the second diode element.   2. The step-down switching regulator according to claim 1, wherein the detection transistor is a bipolar NPN transistor, and the first main electrode, the second main electrode, and the control electrode are a collector, an emitter, and a base, respectively.   The step-down switching regulator according to claim 6, wherein the collector of the detection transistor is connected to a power supply voltage terminal different from the power supply voltage input terminal via a resistor.   A noise mask circuit is connected to the collector of the detection transistor, and the noise mask circuit is responsive to a detection signal extracted from the collector of the detection transistor and based on a signal extracted from the output of the noise mask circuit. The step-down switching regulator according to claim 7, wherein the on operation is shifted to the off operation.   The step-down switching regulator according to claim 8, wherein a predetermined time is provided after the detection transistor transitions from off to on until the circuit operation of the noise mask circuit is switched.   The step-down switching regulator according to claim 9, wherein the predetermined time includes at least one of an integration circuit, a D flip-flop, a logical product circuit, a negative logical product circuit, a logical sum circuit, and a negative logical sum circuit. The step-down switching regulator further includes a logic circuit. The pulse input signal is input to the first input terminal of the logic circuit, and the noise extracted from the noise mask circuit is input to the second input terminal of the logic circuit. 9. The drive signal supplied to the control electrode of the switching transistor is cut off when a mask signal is input and the noise mask signal transits from a predetermined level to another predetermined level. Item 11. The step-down switching regulator according to any one of Items 9 and 10. Switching in which a first main electrode, a second main electrode, and a control electrode are formed on a semiconductor substrate, and a predetermined DC power supply voltage is supplied to the first main electrode and a pulse drive signal is supplied to the control electrode. A transistor,
An output terminal to which a second main electrode of the switching transistor is connected;
A cathode connected to the output terminal, an anode connected to a ground potential terminal, a first diode element formed on the semiconductor substrate together with the switching transistor;
A cathode connected to the output terminal, an anode connected to the ground potential terminal, a second diode element prepared outside the semiconductor substrate and connected in parallel with the first diode element;
A detection transistor having a first main electrode formed on the semiconductor substrate and from which a detection signal is extracted, a second main electrode connected to the output terminal, and a control electrode connected to the ground potential terminal;
With
The detection transistor is turned on when a potential difference between the ground potential and a potential supplied to the output terminal becomes larger than a forward rising voltage between the anode and the cathode of the first diode element, and the switching transistor Integrated circuit device for turning off the operation of.   13. The semiconductor integrated circuit device according to claim 12, wherein the switching transistor is an N channel type MOS transistor. 13. The semiconductor integrated circuit device according to claim 12, wherein the first main electrode, the second main electrode, and the control electrode of the detection transistor are NPN bipolar transistors each having a collector, an emitter, and a base. 15. The semiconductor integrated circuit device according to claim 14, wherein the emitter and base of the detection transistor are formed by using a cathode of the first diode element and the P-type semiconductor substrate, respectively. A first conductivity type semiconductor substrate; a second conductivity type semiconductor region formed on one main surface of the first conductivity type semiconductor substrate; and the second conductivity type semiconductor region to form the switching transistor. A first island region provided in the semiconductor region, a second island region provided in the semiconductor region to form the first diode element, and the semiconductor region to form the detection transistor. The semiconductor integrated circuit device according to claim 12, further comprising a third island-shaped region provided in the semiconductor integrated circuit device.   The semiconductor integrated circuit device according to claim 16, wherein the switching transistor formed in the first island-shaped region is an LDMOS transistor. The semiconductor integrated circuit device according to claim 16, wherein the second island-like region and the third island-like region are provided adjacent to each other in the semiconductor region.