US20050007088A1 - Pfc-pwm controller having a power saving means - Google Patents
Pfc-pwm controller having a power saving means Download PDFInfo
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- US20050007088A1 US20050007088A1 US10/617,516 US61751603A US2005007088A1 US 20050007088 A1 US20050007088 A1 US 20050007088A1 US 61751603 A US61751603 A US 61751603A US 2005007088 A1 US2005007088 A1 US 2005007088A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
- H02M1/007—Plural converter units in cascade
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- the present invention generally relates to a forward switching mode power converter. More particularly, the present invention relates to a PFC-PWM controller having a power saving means. The present invention teaches a forward power converter with power factor correction in the front end.
- Switching-mode power converters have been widely used in many electronic appliances over the last few decades. Switching-mode power converters have several advantages over linear power converters, including higher power conversion efficiency, lighter weight, and smaller size.
- a typical switching mode power converter conducts a non-sinusoidal line current in short pulses that are in phase with the line voltage. This is undesirable for a switching-mode power supply, because it reduces the power factor.
- a switching mode power converter should have a power factor close to 1, but non-sinusoidal line current conduction reduces this to approximately 0.6. For applications that consume 70 watts or more, this could be a serious source of power loss.
- some prior-art switching-mode power converters include power-factor correction circuitry. Power-factor correction is applied to the line current to create a sinusoidal input current waveform that is in phase with the line voltage.
- a switching-mode power supply having power factor correction and a switching frequency reducing means under light-load and zero-load conditions is needed.
- a principal objective of the present invention is to provide a PFC-PWM controller having a power saving means.
- Another objective of the present invention is to synchronize the PWM signal and the PFC signal in an interleaved manner so that a smoother energy delivery from the PFC circuit to the PWM circuit can be effectively achieved and as well increasing power transmission efficiency.
- the PFC-PWM controller according to the present invention uses a pulse signal to accomplish this objective.
- Another objective of the present invention is to provide a pulse-width limiter to establish a maximum on-time for the PWM signal so that switching components such as the transformer and the transistor can be effectively prevented from being saturated.
- Still another objective of the present invention is to eliminate the pin-count of the PFC-PWM controller.
- the PFC-PWM controller includes a current synthesizer that generates a bias current in response to a PFC-feedback voltage and a PWM-feedback voltage.
- the bias current will modulate an oscillator frequency to vary the switching frequency of the PFC signal and the PWM signal.
- the bias current will be reduced to increase the switching period. This feature can dramatically reduce the power consumption of the PFC-PWM controller.
- the PFC-PWM controller is started up using an external resistor and once the PFC-PWM controller is in operation, the external resistor provides an AC current reference.
- the AC current reference is supplied to a multiplier/divider circuit and an error amplifier circuit to improve PFC control.
- FIG. 1 shows a prior-art schematic diagram of a forward power converter with a PFC-PWM controller.
- FIG. 2 shows a schematic diagram of a forward power converter with a PFC-PWM controller according to the present invention.
- FIG. 3 illustrates one embodiment of the PFC-PWM controller according to the present invention.
- FIG. 4 shows an embodiment of a current synthesizer for power saving according to the present invention.
- FIG. 5 shows an embodiment of an oscillator according to the present invention.
- FIG. 6 shows an embodiment of a pulse-width limiter according to the present invention.
- FIG. 7 shows an embodiment of a saw-wave generator according to the present invention.
- FIG. 8 shows an embodiment of a current reference generator according to the present invention.
- FIG. 9 shows a timing diagram observed during the operation of the PFC-PWM controller according to the present invention.
- FIG. 1 shows a conventional forward power converter equipped with a PFC-PWM controller 350 to drive a PFC circuit 200 and a PWM circuit 300 .
- a resistor 22 and a resistor 23 form a resistor divider to sense the output voltage of the PFC circuit 200 from a cathode of a rectifying diode 17 .
- An operational amplifier 20 generates a PFC-feedback voltage V E that is varied in inverse proportion to the voltage at the junction of the resistors 22 and 23 .
- the PWM circuit 300 can be viewed as the load of the PFC circuit 200 . An increased load will cause the output voltage of the PWM circuit 300 to decrease, and with that the output voltages of the PFC circuit 200 and the PWM circuit 300 will also decrease accordingly.
- the PFC-PWM controller 350 accepts several input signals.
- the input signals include the line current information, the PFC-feedback voltage V E , the root-mean square value of the line voltage, and a current-detect voltage V CS .
- the line current information is taken from a positive output of a rectifying bridge diode 10 .
- the root-mean square value of the line voltage is taken from the junction of a resistor 11 and a resistor 38 .
- the current-detect voltage V CS is taken from a current-detect resistor 13 .
- the PFC-PWM controller 350 enables energy from the PFC circuit 200 to be delivered smoothly to the PWM circuit 300 .
- the prior-art power converters operate in a lower and fixed switching frequency under light load condition. Since power consumption is proportional to the switching frequency, this fixed switching frequency still cause unavoidable power consumption. Therefore, in order to save more energy under standby mode, a means for power saving is needed.
- FIG. 3 shows a schematic circuit diagram of a forward power converter according to the present invention.
- the forward power converter according to the present invention can reduce power consumption under light-load and no load conditions
- the PFC-PWM controller 360 comprises a current synthesizer 60 , an oscillator 61 , a pulse-width limiter 62 , an AND-gate 77 , a buffer-gate 78 , a SR flip-flop 76 , a SR flip-flop 79 , a NOT-gate 75 , a saw-wave generator 74 , a comparator 72 , a comparator 73 , an error amplifier circuit 80 , a resistor 71 , a multiplier/divider circuit 64 , a current reference generator 63 , and a diode 121 .
- the current synthesizer 60 comprises an adder 52 , an adder 53 , adder 58 , a V-to-I converter 54 , a V-to-I converter 55 , a current mirror 56 , a current mirror 57 , and a current limiter 59 .
- a positive input of the adder 52 is supplied by a PWM-feedback voltage V FB , which is derived from an output terminal of an opto-coupler 27 shown in FIG. 2 .
- a positive input of the adder 53 is supplied by a PFC-feedback voltage V E , which is derived from an output of an operational amplifier 20 shown in FIG. 2 .
- a negative input of the adder 52 is supplied by a reference voltage V R1 .
- a negative input of the adder 53 is supplied by a reference voltage V R2 .
- An output of the adder 52 is connected to an input of the V-to-I converter 54 .
- the magnitude of the output signal of the adder 52 is equal to the reference voltage V R1 subtracted from the PWM-feedback voltage V FB .
- An output of the adder 53 is connected to an input of the V-to-I converter 55 .
- the magnitude of the output signal of the adder 53 is equal to the reference voltage V R2 subtracted from the PFC-feedback voltage V E .
- An output of the V-to-I converter 54 is connected to a first input of the adder 58 via the current mirror 56 .
- An output of the V-to-I converter 55 is connected to a second input of the adder 58 via the current mirror 57 .
- the current synthesizer 60 outputs a bias current I M from an output of the adder 58 via the current limiter 59 .
- the bias current I M is supplied to an input of the oscillator 61 .
- the frequency of the oscillator 61 can be varied to control the switching frequency of the PWM signal and the PFC signal.
- a first output of the oscillator 61 generates a pulse signal V P , which is supplied to a first input of the pulse-width limiter 62 , an input of the NOT-gate 75 , a reset-input of the SR flip-flop 79 and an input of the saw-wave generator 74 .
- a second output of the oscillator 61 outputs a first saw-tooth signal SAW 1 , which is supplied to a second input of the pulse-width limiter 62 .
- a set-input of the SR flip-flop 76 is connected to an output of the NOT-gate 75 .
- An output of the pulse-width limiter 62 outputs the limit signal wpls, which is supplied to a first input of the AND-gate 77 .
- a second input of the AND-gate 77 is connected to an output of the SR flip-flop 76 .
- the AND-gate 77 outputs the PWM signal for switching the PWM circuit 300 shown in FIG. 2 .
- the resistor 71 is connected between a supply voltage terminal V DD and a positive input of the comparator 72 .
- the resistor 71 is used to bias the opto-coupler 27 shown in FIG. 2 .
- the positive input and a negative input of the comparator 72 are further connected to the output of the opto-coupler 27 and the second output of the oscillator 61 respectively.
- An output of the comparator 72 is connected to a reset-input of the SR flip-flop 76 .
- An input resistor 51 is connected between an input voltage terminal V IN and an input of the current reference generator 63 .
- An anode of the diode 121 is connected to the input of the current reference generator 63 .
- a cathode of the diode 121 supplies the supply voltage V DD from the auxiliary winding of a PFC transformer 16 via a rectifying diode 15 .
- the PFC transformer 16 and the rectifying diode 15 are shown in FIG. 2 .
- An output of the current reference generator 63 supplies an AC template signal I AC to a first input of the multiplier/divider circuit 64 .
- a second input of the multiplier/divider circuit 64 is supplied by the PFC-feedback voltage V E .
- a third input of the multiplier/divider circuit 64 is supplied by an input voltage with root-mean-square value V RMS .
- a resistor 65 , a resistor 66 , a resistor 67 , an operational amplifier 70 , a resistor 68 , and a capacitor 69 form the error amplifier circuit 80 .
- the feedback current I f is supplied to a first input of the error amplifier circuit 80 .
- the current-detect voltage V CS is supplied to a second input of the error amplifier circuit 80 .
- FIG. 2 shows a bridge rectifier 10 and a resistor 13 .
- the resistor 13 is connected between a negative output of the bridge rectifier 10 and the ground reference.
- the input current I f will generate the current-detect voltage V CS across the resistor 13 .
- the error amplifier circuit 80 will generate a feedback voltage V, in response to the feedback current I f and the current-detect voltage V CS .
- a positive input of the comparator 73 is supplied by the feedback voltage V f .
- a negative input of the comparator 73 is connected to an output of the saw-wave generator 74 .
- the SR flip-flop 79 is set by an output of the comparator 73 .
- the SR flip-flop 79 outputs the PFC signal via the buffer-gate 78 to drive the PFC circuit 200 .
- FIG. 4 shows a preferred embodiment of the current synthesizer 60 according to the present invention.
- the current synthesizer 60 comprises a current source 100 , a first current mirror composed of a transistor 101 and a transistor 104 , a second current mirror composed of a transistor 102 and a transistor 105 , an operational amplifier 103 , an operational amplifier 106 , a buffer amplifier 111 , a buffer amplifier 112 , a V-to-I transistor 107 , a V-to-I transistor 108 , a resistor 109 , and a resistor 110 .
- An input of the current source 100 is supplied by the supply voltage V D0 .
- An output of the current source 100 is connected to a source of the transistor 101 , a source of the transistor 102 , a source of the transistor 104 , and a source of the transistor 105 .
- a gate of the transistor 101 , a gate of the transistor 104 , a drain of the transistor 101 , and a drain of the V-to-I transistor 107 are tied together.
- a gate of the transistor 102 , a gate of the transistor 105 , a drain of the transistor 102 , and a drain of the V-to-I transistor 108 are tied together.
- a gate of the V-to-I transistor 107 is driven by an output of the operational amplifier 103 .
- a gate of the V-to-I transistor 108 is driven by an output of the operational amplifier 106 .
- the PWM-feedback voltage V FB is supplied to a positive input of the operational amplifier 103 .
- the PFC-feedback voltage V E is supplied to a positive input of the operational amplifier 106 .
- a negative input of the operational amplifier 103 is connected to a source of the V-to-I transistor 107 .
- a negative input of the operational amplifier 106 is connected to a source of the V-to-I transistor 108 .
- a negative input of the buffer amplifier 111 is connected to an output of the buffer amplifier 111 .
- a negative input of the buffer amplifier 112 is connected to an output of the buffer amplifier 112 .
- a positive input of the buffer amplifier 111 and a positive input of the buffer amplifier 112 are supplied by the reference voltage V R1 and the reference voltage V R2 respectively.
- the resistor 109 is connected between the negative input of the operational amplifier 103 and the negative input of the buffer amplifier 111 .
- the resistor 110 is connected between the negative input of the operational amplifier 106 and the negative input of the buffer amplifier 112 .
- a drain of the transistor 104 and a drain of the transistor 105 are connected together to generate the bias current I M .
- both the PWM-feedback voltage V FB and the PFC-feedback voltage V E will be reduced.
- the first current mirror mirrors the current I FB to the current I 1 .
- the second current mirror mirrors the current I E to the current I 2 .
- the currents I 1 and I 2 are summed together to generate the bias current I M
- the bias current I M varies in response to the load conditions of the PFC circuit and PWM circuit.
- the bias current I M is supplied to the oscillator 61 to modulate the switching frequency.
- FIG. 5 shows a preferred embodiment of the oscillator 61 according to the present invention.
- the oscillator 61 comprises a third current mirror composed of a transistor 84 and a transistor 85 , a switch 82 , a switch 83 , a capacitor 87 , a comparator 88 , a comparator 89 , a NAND-gate 90 , a NAND-gate 91 , a NOT-gate 86 , and a current source 81 .
- An input of the current source 81 is supplied by the supply voltage V DD .
- An output of the current source 81 is connected to an input terminal of the switch 82 .
- An output terminal of the switch 82 and an input terminal of the switch 83 are tied together, and are connected to a negative input of the comparator 88 and a positive input of the comparator 89 .
- a positive input of the comparator 88 is supplied by an upper-threshold voltage V H .
- a negative input of the comparator 89 is supplied by a lower-threshold voltage V L .
- An output of the comparator 88 is connected to a first input of the NAND-gate 90 .
- An output of the comparator 89 is connected to a second input of the NAND-gate 91 .
- An output of the NAND-gate 91 is connected to a second input of the NAND-gate 90 .
- An output of the NAND-gate 90 which outputs the pulse signal V P , is connected to a first input of the NAND-gate 91 , an input of the NOT-gate 86 , and a control terminal of the switch 83 .
- An output of the NOT-gate 86 is connected to a control terminal of the switch 82 .
- the third current mirror formed by the transistors 84 and 85 mirrors the bias current I M to a discharge current I DISCHARGE .
- a source of the transistor 84 and a source of the transistor 85 are connected to the ground reference.
- a gate of the transistor 84 , a gate of the transistor 85 , a drain of the transistor 84 , and an output of the current synthesizer 60 shown in FIG. 2 are connected together.
- a drain of the transistor 85 is connected to an output terminal of the switch 83 .
- the capacitor 87 is connected between the negative input of the comparator 88 and the ground reference.
- the voltage of the capacitor 87 is zero.
- the comparator 88 will output a logic-high signal to the first input of the NAND-gate 90
- the comparator 89 will output a logic-low signal to the second input of the NAND-gate 91 . Therefore, the output of the NAND-gate 90 will output a logic-low signal to the input of the NOT-gate 86 to turn on the switch 82 .
- the current source 81 will then start to charge the capacitor 87 .
- the comparator 88 will output a logic-low signal to the first input of the NAND-gate 90 .
- the NAND-gate 90 will output a logic-high signal to turn off the switch 82 and turn on the switch 83 .
- the discharge current I DISCHARGE which is varied in proportion to the bias current IM, will start to discharge the capacitor 87 .
- the discharge time of the capacitor 87 modulates the off-time of the pulse signal Vp.
- the discharge time of the capacitor 87 also determines the switching period of the PFC-PWM controller.
- the oscillator 61 outputs the first saw-tooth signal SAW 1 from the capacitor 87 for PWM control.
- the pulse signal Vp provides a base frequency for easily synchronizing the PWM signal and the PFC signal.
- FIG. 6 shows a preferred embodiment of the pulse-width limiter 62 according to the present invention.
- the pulse-width limiter 62 comprises a NAND-gate 126 , a NAND-gate 128 , and a comparator 127 .
- a reference voltage VR 3 is supplied to a negative input of the comparator 127 .
- the first saw-tooth signal SAW 1 is supplied to a positive input of the comparator 127 .
- the pulse signal V P is supplied to a first input of the NAND-gate 126 .
- An output of the NAND-gate 126 is connected to a first input of the NAND-gate 128 .
- a second input of the NAND-gate 128 is connected to an output of the comparator 127 .
- An output of the NAND-gate 128 is connected to a second input of the NAND-gate 126 and outputs the limit signal wpls.
- the magnitude of the reference voltage V R3 determines a maximum on-time of the PWM signal. While the pulse signal V P is logic-low and the first saw-tooth signal SAW 1 is less than the reference voltage V R3 , the NAND-gate 128 will output a logic-high limit signal. Once the first saw-tooth signal SAW 1 reaches the reference voltage V R3 , the comparator 127 will output a logic-high signal, causing the limit signal wpls to become logic-low.
- FIG. 7 shows a preferred embodiment of the saw-wave generator 74 . Similar to the way the first saw-tooth signal SAW 1 controls the PWM signal, a second saw-tooth signal SAW 2 is generated by the saw-wave generator 74 for PFC control.
- the saw-wave generator 74 comprises a transistor 131 , a current source 130 , a switch 132 , a capacitor 133 , and a fourth current mirror composed of a transistor 134 and a transistor 135 .
- a source of the transistor 131 , a source of the transistor 134 , and a source of the transistor 135 are connected to the ground reference.
- the pulse signal V P is provided to a gate of the transistor 131 and a control terminal of the switch 132 .
- An input of the current source 130 is supplied by the supply voltage V DD .
- An output of the current source 130 is connected to a drain of the transistor 131 .
- a drain of the transistor 131 , a drain of the transistor 135 , a gate of the transistor 134 , and a gate of the transistor 135 are tied together.
- An input terminal of the switch 132 is supplied by a reference voltage V R4 .
- An output terminal of the switch 132 is connected to a drain of the transistor 134 .
- the capacitor 133 is connected between the drain of the transistor 134 and the ground reference.
- the switch 132 While the pulse signal V P is logic-high, the switch 132 will be turned on and the reference voltage V R4 will immediately charge the capacitor 133 to the voltage level of V R4 . Meanwhile, the current source 130 will be grounded and no current will flow into the drain of the transistor 135 . Once the pulse signal V P drops to logic-low, the switch 132 is turned off and the energy stored in the capacitor 133 will be discharged by a discharge current I D , which is mirrored from the current source 130 . The capacitor 133 supplies the second saw-tooth signal SAW 2 for PFC control.
- FIG. 8 shows one embodiment of the present invention that uses the input resistor 51 to start up the PFC-PWM controller 360 .
- This embodiment also uses the input resistor 51 to provide the AC template signal I AC for PFC control.
- the input resistor 51 is connected between the input voltage terminal VIN shown in FIG. 2 and the anode of the diode 121 .
- the supply voltage V DD is supplied from a cathode of the diode 121 , which is also connected to the auxiliary winding of the PFC transformer 16 via the rectifying diode 15 .
- a start-up capacitor 120 is connected between the ground reference and the supply voltage terminal V DD of the PFC-PWM controller 360 .
- the current reference generator 63 comprises a transistor 123 and a fifth current mirror composed of a transistor 124 and a transistor 125 .
- a drain of the transistor 123 is connected to the anode of the diode 121 .
- a gate of the transistor 123 is supplied by a reference voltage V R5 .
- a source of the transistor 123 , a drain of the transistor 124 , a gate of the transistor 124 , and a gate of the transistor 125 are tied together.
- a source of the transistor 124 and a source of the transistor 125 are connected to the ground reference.
- the input resistor 51 will convert the input voltage V IN to a start-up current I S .
- the start-up current I S will then start to charge the start-up capacitor 120 via the diode 121 .
- the reference voltage V R5 will be initialized.
- the reference voltage V R5 will turn on the transistors 123 , and the voltage at the anode of the diode 121 will drop to inverse-bias the diode 121 .
- the diode 121 When the diode 121 is inverse-biased, the current path via the diode 121 will be cut off, and the supply voltage V DD will be supplied by the auxiliary winding of the PFC transformer 16 via the rectifying diode 15 . Since the start-up current Is no longer flows through the diode 121 , a third current 13 will flow through the transistors 123 and 124 . The transistor 125 will generate the AC template signal I AC in response to the third current 13 .
- FIG. 9 shows the timing diagram of the PFC-PWM controller 360 according to the present invention.
- the PWM and the PFC signal can interleave each other. Since the PWM signal and the PFC signal are generated alternately, transmission efficiency is improved. Further, since the PWM signal and the PFC signal are synchronized by the pulse signal V P , the off-times of the PWM signal and the PFC signal are extended under light-load and no-load conditions. The switching frequencies of the PWM signal and the PFC signal will then be reduced by expanding the switching period. Therefore, power consumption under light-load and no-load conditions can be greatly reduced by the PFC-PWM controller 360 according to the present invention.
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Abstract
Description
- 1. Field of the Invention
- The present invention generally relates to a forward switching mode power converter. More particularly, the present invention relates to a PFC-PWM controller having a power saving means. The present invention teaches a forward power converter with power factor correction in the front end.
- 2. Description of the Related Art
- Switching-mode power converters have been widely used in many electronic appliances over the last few decades. Switching-mode power converters have several advantages over linear power converters, including higher power conversion efficiency, lighter weight, and smaller size.
- However, traditional switching-mode power supplies have some drawbacks. A typical switching mode power converter conducts a non-sinusoidal line current in short pulses that are in phase with the line voltage. This is undesirable for a switching-mode power supply, because it reduces the power factor. Ideally, a switching mode power converter should have a power factor close to 1, but non-sinusoidal line current conduction reduces this to approximately 0.6. For applications that consume 70 watts or more, this could be a serious source of power loss.
- Another drawback of switching mode power converters is that line harmonics are produced whenever the line current is not sinusoidal. The harmonic currents do not contribute to the load power, but they do cause excess heat generation in the power contribution system.
- To avoid unnecessary power losses and heat dissipation, some prior-art switching-mode power converters include power-factor correction circuitry. Power-factor correction is applied to the line current to create a sinusoidal input current waveform that is in phase with the line voltage.
- One drawback of traditional power factor correction schemes is that they do not reduce power consumption sufficiently to comply with recent environmental regulations. In recent years, many countries have adopted strict regulations regarding power consumption. Electronic devices that consume 70 watts or more are generally required to minimize power consumption during standby, or idle-mode. However, traditional switching-mode power supplies with power factor correction still operate at a specific PWM switching frequency during standby. Since the power consumption of a switching-mode power converter is directly proportional to the switching frequency of the PWM signal and the PFC signal, prior-art switching-mode power supplies fail to minimize power consumption during standby.
- Recently enacted environmental regulations regarding standby mode power consumption have created a need in many countries for more efficient power supplies. A switching-mode power supply having power factor correction and a switching frequency reducing means under light-load and zero-load conditions is needed.
- A principal objective of the present invention is to provide a PFC-PWM controller having a power saving means.
- Another objective of the present invention is to synchronize the PWM signal and the PFC signal in an interleaved manner so that a smoother energy delivery from the PFC circuit to the PWM circuit can be effectively achieved and as well increasing power transmission efficiency. The PFC-PWM controller according to the present invention uses a pulse signal to accomplish this objective.
- Another objective of the present invention is to provide a pulse-width limiter to establish a maximum on-time for the PWM signal so that switching components such as the transformer and the transistor can be effectively prevented from being saturated.
- Still another objective of the present invention is to eliminate the pin-count of the PFC-PWM controller.
- According to one aspect of the present invention, the PFC-PWM controller includes a current synthesizer that generates a bias current in response to a PFC-feedback voltage and a PWM-feedback voltage. The bias current will modulate an oscillator frequency to vary the switching frequency of the PFC signal and the PWM signal. When the power converter operates under light-load conditions, the bias current will be reduced to increase the switching period. This feature can dramatically reduce the power consumption of the PFC-PWM controller.
- According to another aspect of the present invention, the PFC-PWM controller is started up using an external resistor and once the PFC-PWM controller is in operation, the external resistor provides an AC current reference. The AC current reference is supplied to a multiplier/divider circuit and an error amplifier circuit to improve PFC control.
- It is to be understood that both the foregoing general descriptions and the following detailed descriptions are exemplary, and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
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FIG. 1 shows a prior-art schematic diagram of a forward power converter with a PFC-PWM controller. -
FIG. 2 shows a schematic diagram of a forward power converter with a PFC-PWM controller according to the present invention. -
FIG. 3 illustrates one embodiment of the PFC-PWM controller according to the present invention. -
FIG. 4 shows an embodiment of a current synthesizer for power saving according to the present invention. -
FIG. 5 shows an embodiment of an oscillator according to the present invention. -
FIG. 6 shows an embodiment of a pulse-width limiter according to the present invention. -
FIG. 7 shows an embodiment of a saw-wave generator according to the present invention. -
FIG. 8 shows an embodiment of a current reference generator according to the present invention. -
FIG. 9 shows a timing diagram observed during the operation of the PFC-PWM controller according to the present invention. -
FIG. 1 shows a conventional forward power converter equipped with a PFC-PWM controller 350 to drive aPFC circuit 200 and aPWM circuit 300. Aresistor 22 and aresistor 23 form a resistor divider to sense the output voltage of thePFC circuit 200 from a cathode of a rectifyingdiode 17. Anoperational amplifier 20 generates a PFC-feedback voltage VE that is varied in inverse proportion to the voltage at the junction of theresistors PWM circuit 300 can be viewed as the load of thePFC circuit 200. An increased load will cause the output voltage of thePWM circuit 300 to decrease, and with that the output voltages of thePFC circuit 200 and thePWM circuit 300 will also decrease accordingly. On the other hand, when the load decreases, the output voltages of thePFC circuit 200 andPWM circuit 300 will also increase. To obtain a sinusoidal line current waveform, the PFC-PWM controller 350 accepts several input signals. The input signals include the line current information, the PFC-feedback voltage VE, the root-mean square value of the line voltage, and a current-detect voltage VCS. The line current information is taken from a positive output of a rectifyingbridge diode 10. The root-mean square value of the line voltage is taken from the junction of a resistor 11 and aresistor 38. The current-detect voltage VCS is taken from a current-detect resistor 13. The PFC-PWM controller 350 enables energy from thePFC circuit 200 to be delivered smoothly to thePWM circuit 300. - However, the prior-art power converters operate in a lower and fixed switching frequency under light load condition. Since power consumption is proportional to the switching frequency, this fixed switching frequency still cause unavoidable power consumption. Therefore, in order to save more energy under standby mode, a means for power saving is needed.
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FIG. 3 shows a schematic circuit diagram of a forward power converter according to the present invention. The forward power converter according to the present invention can reduce power consumption under light-load and no load conditions Further referring toFIG. 3 , the PFC-PWM controller 360 comprises acurrent synthesizer 60, anoscillator 61, a pulse-width limiter 62, an AND-gate 77, a buffer-gate 78, a SR flip-flop 76, a SR flip-flop 79, a NOT-gate 75, a saw-wave generator 74, acomparator 72, acomparator 73, anerror amplifier circuit 80, aresistor 71, a multiplier/divider circuit 64, acurrent reference generator 63, and adiode 121. - Referring to
FIG. 3 , thecurrent synthesizer 60 comprises anadder 52, anadder 53,adder 58, a V-to-I converter 54, a V-to-I converter 55, acurrent mirror 56, acurrent mirror 57, and acurrent limiter 59. A positive input of theadder 52 is supplied by a PWM-feedback voltage VFB, which is derived from an output terminal of an opto-coupler 27 shown inFIG. 2 . A positive input of theadder 53 is supplied by a PFC-feedback voltage VE, which is derived from an output of anoperational amplifier 20 shown inFIG. 2 . - A negative input of the
adder 52 is supplied by a reference voltage VR1. A negative input of theadder 53 is supplied by a reference voltage VR2. An output of theadder 52 is connected to an input of the V-to-I converter 54. The magnitude of the output signal of theadder 52 is equal to the reference voltage VR1 subtracted from the PWM-feedback voltage VFB. An output of theadder 53 is connected to an input of the V-to-I converter 55. The magnitude of the output signal of theadder 53 is equal to the reference voltage VR2 subtracted from the PFC-feedback voltage VE. An output of the V-to-I converter 54 is connected to a first input of theadder 58 via thecurrent mirror 56. An output of the V-to-I converter 55 is connected to a second input of theadder 58 via thecurrent mirror 57. Thecurrent synthesizer 60 outputs a bias current IM from an output of theadder 58 via thecurrent limiter 59. - The bias current IM is supplied to an input of the
oscillator 61. By modulating the bias current IM, the frequency of theoscillator 61 can be varied to control the switching frequency of the PWM signal and the PFC signal. A first output of theoscillator 61 generates a pulse signal VP, which is supplied to a first input of the pulse-width limiter 62, an input of the NOT-gate 75, a reset-input of the SR flip-flop 79 and an input of the saw-wave generator 74. A second output of theoscillator 61 outputs a first saw-tooth signal SAW1, which is supplied to a second input of the pulse-width limiter 62. A set-input of the SR flip-flop 76 is connected to an output of the NOT-gate 75. An output of the pulse-width limiter 62 outputs the limit signal wpls, which is supplied to a first input of the AND-gate 77. A second input of the AND-gate 77 is connected to an output of the SR flip-flop 76. The AND-gate 77 outputs the PWM signal for switching thePWM circuit 300 shown inFIG. 2 . Theresistor 71 is connected between a supply voltage terminal VDD and a positive input of thecomparator 72. Theresistor 71 is used to bias the opto-coupler 27 shown inFIG. 2 . The positive input and a negative input of thecomparator 72 are further connected to the output of the opto-coupler 27 and the second output of theoscillator 61 respectively. An output of thecomparator 72 is connected to a reset-input of the SR flip-flop 76. - An
input resistor 51 is connected between an input voltage terminal VIN and an input of thecurrent reference generator 63. An anode of thediode 121 is connected to the input of thecurrent reference generator 63. A cathode of thediode 121 supplies the supply voltage VDD from the auxiliary winding of aPFC transformer 16 via a rectifyingdiode 15. ThePFC transformer 16 and the rectifyingdiode 15 are shown inFIG. 2 . An output of thecurrent reference generator 63 supplies an AC template signal IAC to a first input of the multiplier/divider circuit 64. A second input of the multiplier/divider circuit 64 is supplied by the PFC-feedback voltage VE. A third input of the multiplier/divider circuit 64 is supplied by an input voltage with root-mean-square value VRMS. The feedback current If generated by the multiplier/divider circuit 64 can be expressed by following equation: - A
resistor 65, a resistor 66, aresistor 67, anoperational amplifier 70, aresistor 68, and acapacitor 69 form theerror amplifier circuit 80. The feedback current If is supplied to a first input of theerror amplifier circuit 80. The current-detect voltage VCS is supplied to a second input of theerror amplifier circuit 80.FIG. 2 shows abridge rectifier 10 and aresistor 13. Theresistor 13 is connected between a negative output of thebridge rectifier 10 and the ground reference. The input current If will generate the current-detect voltage VCS across theresistor 13. - The
error amplifier circuit 80 will generate a feedback voltage V, in response to the feedback current If and the current-detect voltage VCS. A positive input of thecomparator 73 is supplied by the feedback voltage Vf. A negative input of thecomparator 73 is connected to an output of the saw-wave generator 74. The SR flip-flop 79 is set by an output of thecomparator 73. The SR flip-flop 79 outputs the PFC signal via the buffer-gate 78 to drive thePFC circuit 200. -
FIG. 4 shows a preferred embodiment of thecurrent synthesizer 60 according to the present invention. Thecurrent synthesizer 60 comprises acurrent source 100, a first current mirror composed of atransistor 101 and atransistor 104, a second current mirror composed of atransistor 102 and atransistor 105, anoperational amplifier 103, anoperational amplifier 106, abuffer amplifier 111, abuffer amplifier 112, a V-to-I transistor 107, a V-to-I transistor 108, aresistor 109, and aresistor 110. - An input of the
current source 100 is supplied by the supply voltage VD0. An output of thecurrent source 100 is connected to a source of thetransistor 101, a source of thetransistor 102, a source of thetransistor 104, and a source of thetransistor 105. A gate of thetransistor 101, a gate of thetransistor 104, a drain of thetransistor 101, and a drain of the V-to-I transistor 107 are tied together. A gate of thetransistor 102, a gate of thetransistor 105, a drain of thetransistor 102, and a drain of the V-to-I transistor 108 are tied together. A gate of the V-to-I transistor 107 is driven by an output of theoperational amplifier 103. A gate of the V-to-I transistor 108 is driven by an output of theoperational amplifier 106. - The PWM-feedback voltage VFB is supplied to a positive input of the
operational amplifier 103. The PFC-feedback voltage VE is supplied to a positive input of theoperational amplifier 106. A negative input of theoperational amplifier 103 is connected to a source of the V-to-I transistor 107. A negative input of theoperational amplifier 106 is connected to a source of the V-to-I transistor 108. - A negative input of the
buffer amplifier 111 is connected to an output of thebuffer amplifier 111. A negative input of thebuffer amplifier 112 is connected to an output of thebuffer amplifier 112. A positive input of thebuffer amplifier 111 and a positive input of thebuffer amplifier 112 are supplied by the reference voltage VR1 and the reference voltage VR2 respectively. Theresistor 109 is connected between the negative input of theoperational amplifier 103 and the negative input of thebuffer amplifier 111. Theresistor 110 is connected between the negative input of theoperational amplifier 106 and the negative input of thebuffer amplifier 112. A drain of thetransistor 104 and a drain of thetransistor 105 are connected together to generate the bias current IM. - Further referring to
FIG. 4 , under light-load conditions, both the PWM-feedback voltage VFB and the PFC-feedback voltage VE will be reduced. The current IFB flowing through theresistor 109 can be expressed by the following equation:
where R109 is the resistance of theresistor 109. The current IE flowing through theresistor 110 can be expressed by the following equation:
where R110 is the resistance of theresistor 110. - The first current mirror mirrors the current IFB to the current I1. The second current mirror mirrors the current IE to the current I2. The currents I1 and I2 are summed together to generate the bias current IM The bias current IM can be expressed by the following equation:
I M =I 1 +I 2 =N 1 ×I FB +N 2 ×I E (4)
where N1 and N2 are the mirror ratios of the first current mirror and the second mirror respectively. The bias current IM varies in response to the load conditions of the PFC circuit and PWM circuit. The bias current IM is supplied to theoscillator 61 to modulate the switching frequency. -
FIG. 5 shows a preferred embodiment of theoscillator 61 according to the present invention. Theoscillator 61 comprises a third current mirror composed of atransistor 84 and atransistor 85, aswitch 82, aswitch 83, acapacitor 87, acomparator 88, acomparator 89, a NAND-gate 90, a NAND-gate 91, a NOT-gate 86, and acurrent source 81. An input of thecurrent source 81 is supplied by the supply voltage VDD. An output of thecurrent source 81 is connected to an input terminal of theswitch 82. An output terminal of theswitch 82 and an input terminal of theswitch 83 are tied together, and are connected to a negative input of thecomparator 88 and a positive input of thecomparator 89. A positive input of thecomparator 88 is supplied by an upper-threshold voltage VH. A negative input of thecomparator 89 is supplied by a lower-threshold voltage VL. An output of thecomparator 88 is connected to a first input of the NAND-gate 90. An output of thecomparator 89 is connected to a second input of the NAND-gate 91. An output of the NAND-gate 91 is connected to a second input of the NAND-gate 90. An output of the NAND-gate 90, which outputs the pulse signal VP, is connected to a first input of the NAND-gate 91, an input of the NOT-gate 86, and a control terminal of theswitch 83. An output of the NOT-gate 86 is connected to a control terminal of theswitch 82. - The third current mirror formed by the
transistors transistor 84 and a source of thetransistor 85 are connected to the ground reference. A gate of thetransistor 84, a gate of thetransistor 85, a drain of thetransistor 84, and an output of thecurrent synthesizer 60 shown inFIG. 2 are connected together. A drain of thetransistor 85 is connected to an output terminal of theswitch 83. Thecapacitor 87 is connected between the negative input of thecomparator 88 and the ground reference. - Initially, the voltage of the
capacitor 87 is zero. Thecomparator 88 will output a logic-high signal to the first input of the NAND-gate 90, and thecomparator 89 will output a logic-low signal to the second input of the NAND-gate 91. Therefore, the output of the NAND-gate 90 will output a logic-low signal to the input of the NOT-gate 86 to turn on theswitch 82. Thecurrent source 81 will then start to charge thecapacitor 87. When the voltage of thecapacitor 87 reaches the upper-threshold voltage VH, thecomparator 88 will output a logic-low signal to the first input of the NAND-gate 90. The NAND-gate 90 will output a logic-high signal to turn off theswitch 82 and turn on theswitch 83. At the moment theswitch 83 is turned on, the discharge current IDISCHARGE, which is varied in proportion to the bias current IM, will start to discharge thecapacitor 87. The discharge time of thecapacitor 87 modulates the off-time of the pulse signal Vp. The discharge time of thecapacitor 87 also determines the switching period of the PFC-PWM controller. Besides the pulse signal VP, theoscillator 61 outputs the first saw-tooth signal SAW1 from thecapacitor 87 for PWM control. The pulse signal Vp provides a base frequency for easily synchronizing the PWM signal and the PFC signal. -
FIG. 6 shows a preferred embodiment of the pulse-width limiter 62 according to the present invention. The pulse-width limiter 62 comprises a NAND-gate 126, a NAND-gate 128, and acomparator 127. A reference voltage VR3 is supplied to a negative input of thecomparator 127. The first saw-tooth signal SAW1 is supplied to a positive input of thecomparator 127. The pulse signal VP is supplied to a first input of theNAND-gate 126. An output of theNAND-gate 126 is connected to a first input of theNAND-gate 128. A second input of theNAND-gate 128 is connected to an output of thecomparator 127. An output of theNAND-gate 128 is connected to a second input of the NAND-gate 126 and outputs the limit signal wpls. The magnitude of the reference voltage VR3 determines a maximum on-time of the PWM signal. While the pulse signal VP is logic-low and the first saw-tooth signal SAW1 is less than the reference voltage VR3, the NAND-gate 128 will output a logic-high limit signal. Once the first saw-tooth signal SAW1 reaches the reference voltage VR3, thecomparator 127 will output a logic-high signal, causing the limit signal wpls to become logic-low. -
FIG. 7 shows a preferred embodiment of the saw-wave generator 74. Similar to the way the first saw-tooth signal SAW1 controls the PWM signal, a second saw-tooth signal SAW2 is generated by the saw-wave generator 74 for PFC control. The saw-wave generator 74 comprises atransistor 131, acurrent source 130, aswitch 132, acapacitor 133, and a fourth current mirror composed of atransistor 134 and atransistor 135. - A source of the
transistor 131, a source of thetransistor 134, and a source of thetransistor 135 are connected to the ground reference. The pulse signal VP is provided to a gate of thetransistor 131 and a control terminal of theswitch 132. An input of thecurrent source 130 is supplied by the supply voltage VDD. An output of thecurrent source 130 is connected to a drain of thetransistor 131. A drain of thetransistor 131, a drain of thetransistor 135, a gate of thetransistor 134, and a gate of thetransistor 135 are tied together. An input terminal of theswitch 132 is supplied by a reference voltage VR4. An output terminal of theswitch 132 is connected to a drain of thetransistor 134. Thecapacitor 133 is connected between the drain of thetransistor 134 and the ground reference. - While the pulse signal VP is logic-high, the
switch 132 will be turned on and the reference voltage VR4 will immediately charge thecapacitor 133 to the voltage level of VR4. Meanwhile, thecurrent source 130 will be grounded and no current will flow into the drain of thetransistor 135. Once the pulse signal VP drops to logic-low, theswitch 132 is turned off and the energy stored in thecapacitor 133 will be discharged by a discharge current ID, which is mirrored from thecurrent source 130. Thecapacitor 133 supplies the second saw-tooth signal SAW2 for PFC control. -
FIG. 8 shows one embodiment of the present invention that uses theinput resistor 51 to start up the PFC-PWM controller 360. This embodiment also uses theinput resistor 51 to provide the AC template signal IAC for PFC control. Theinput resistor 51 is connected between the input voltage terminal VIN shown inFIG. 2 and the anode of thediode 121. The supply voltage VDD is supplied from a cathode of thediode 121, which is also connected to the auxiliary winding of thePFC transformer 16 via the rectifyingdiode 15. A start-upcapacitor 120 is connected between the ground reference and the supply voltage terminal VDD of the PFC-PWM controller 360. - The
current reference generator 63 comprises atransistor 123 and a fifth current mirror composed of atransistor 124 and atransistor 125. A drain of thetransistor 123 is connected to the anode of thediode 121. A gate of thetransistor 123 is supplied by a reference voltage VR5. A source of thetransistor 123, a drain of thetransistor 124, a gate of thetransistor 124, and a gate of thetransistor 125 are tied together. A source of thetransistor 124 and a source of thetransistor 125 are connected to the ground reference. - Once the power converter is turned on, the
input resistor 51 will convert the input voltage VIN to a start-up current IS. The start-up current IS will then start to charge the start-upcapacitor 120 via thediode 121. When the voltage of the start-upcapacitor 120 reaches the start-up threshold voltage of the PFC-PWM controller 360, the reference voltage VR5 will be initialized. The reference voltage VR5 will turn on thetransistors 123, and the voltage at the anode of thediode 121 will drop to inverse-bias thediode 121. When thediode 121 is inverse-biased, the current path via thediode 121 will be cut off, and the supply voltage VDD will be supplied by the auxiliary winding of thePFC transformer 16 via the rectifyingdiode 15. Since the start-up current Is no longer flows through thediode 121, a third current 13 will flow through thetransistors transistor 125 will generate the AC template signal IAC in response to the third current 13. -
FIG. 9 shows the timing diagram of the PFC-PWM controller 360 according to the present invention. By properly setting the reference voltage VR3 and the feedback voltage Vf, the PWM and the PFC signal can interleave each other. Since the PWM signal and the PFC signal are generated alternately, transmission efficiency is improved. Further, since the PWM signal and the PFC signal are synchronized by the pulse signal VP, the off-times of the PWM signal and the PFC signal are extended under light-load and no-load conditions. The switching frequencies of the PWM signal and the PFC signal will then be reduced by expanding the switching period. Therefore, power consumption under light-load and no-load conditions can be greatly reduced by the PFC-PWM controller 360 according to the present invention. - It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the present invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided that they fall within the scope of the following claims and their equivalents.
Claims (12)
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PCT/CN2004/000686 WO2005006523A1 (en) | 2003-07-10 | 2004-06-25 | Pfc-pwm controller having a power saving means |
CNB2004800196577A CN100403634C (en) | 2003-07-10 | 2004-06-25 | PFC-PWM controller having a power saving means |
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Also Published As
Publication number | Publication date |
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CN1849742A (en) | 2006-10-18 |
CN100403634C (en) | 2008-07-16 |
US6839247B1 (en) | 2005-01-04 |
WO2005006523A1 (en) | 2005-01-20 |
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