CN109286318B - Step-down converter with constant switching frequency - Google Patents
Step-down converter with constant switching frequency Download PDFInfo
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- CN109286318B CN109286318B CN201811526413.8A CN201811526413A CN109286318B CN 109286318 B CN109286318 B CN 109286318B CN 201811526413 A CN201811526413 A CN 201811526413A CN 109286318 B CN109286318 B CN 109286318B
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- 239000003990 capacitor Substances 0.000 claims description 17
- 230000004044 response Effects 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 4
- 238000001914 filtration Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000000306 component Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The application discloses a buck converter with constant switching frequency, which comprises an SFC core circuit and a voltage feedback loop, wherein the voltage feedback loop comprises a first switching tube Q1 and a second switching tube Q2, the source electrode of the first switching tube Q1 is connected with a VIN input signal, the grid electrode of the first switching tube Q1 is connected with a PWM output signal of the SFC core circuit through a driver, the drain electrode of the first switching tube Q1 is connected with the source electrode of the second switching tube Q2, the drain electrodes of the first switching tube Q1 and the second switching tube Q2 are respectively connected with an output voltage feedback signal vfb through a third resistor R3 and a fourth resistor R4, and the output voltage feedback signal vfb and a reference voltage VREF are input into the SFC core circuit as pulse signals after passing through a comparator. The buck converter with constant switching frequency has a simple circuit structure, can perform rapid load current response and rapid input voltage response, and can realize stable voltage output.
Description
Technical Field
The present application relates to a buck converter, and more particularly, to a buck converter with constant switching frequency.
Background
Typical constitution of buck converters are: the controller provides a periodic PWM control signal and the driver drives a pair of switches and an inductor and an output capacitor, a type of buck converter known as a synchronous buck converter. The switch Q2 may be replaced by a diode, a buck converter of the so-called asynchronous type.
There are a variety of architectures to implement the functions of the controller, such as voltage mode, peak current mode, constant on-time mode. However, the current buck converters with various architectures have complex circuit structures and slow load response.
Disclosure of Invention
The application aims to provide a buck converter with constant switching frequency, which solves the problems of complex circuit structure and slower load response of the existing buck converters with various architectures.
In order to solve the technical problems, the application adopts the following technical scheme:
the buck converter with constant switching frequency comprises an SFC core circuit and a voltage feedback loop, wherein the voltage feedback loop comprises a first switching tube Q1 and a second switching tube Q2, the source electrode of the first switching tube Q1 is connected with a VIN input signal, the grid electrode of the first switching tube Q1 is connected with a PWM output signal of the SFC core circuit through a driver, the drain electrode of the first switching tube Q1 is connected with the source electrode of the second switching tube Q2, the drain electrode of the first switching tube Q1 and the drain electrode of the second switching tube Q2 are respectively connected to an output voltage feedback signal vfb through a third resistor R3 and a fourth resistor R4, and the output voltage feedback signal vfb and a reference voltage VREF are input into the SFC core circuit as pulse signals after passing through a comparator.
Preferably, the SFC core circuit includes a first flip-flop rsregister1 and a second flip-flop rsregister2, wherein an S pin of the first flip-flop rsregister1 and an S pin of the second flip-flop rsregister2 are connected with pulse signals, a q pin of the first flip-flop rsregister1 and a q pin of the second flip-flop rsregister2 are connected with a PWM output signal and an LDREN output signal, respectively, and an r pin of the first flip-flop rsregister1 and an r pin of the second flip-flop rsregister2 are connected with an S1 input signal and an S2 input signal, respectively.
Preferably, the q pin of the first flip-flop rsregister1 is further connected to a gate of a first switch SW1, a source of the first switch SW1 is connected to a power supply through a first resistor R1, and a drain of the first switch SW1 is grounded through a first capacitor C1.
Preferably, the S1 input signal is an output signal of Vin signal after being connected to the first resistor R1 and the first capacitor C1 and passing through the first comparator 1.
Preferably, the drain of the first switch SW1 is further connected to the source of a second switch SW2, the gate of the second switch SW2 is connected to the qb pin of the first flip-flop rsregister1, and the drain of the second switch SW2 is grounded.
Preferably, the q pin of the second trigger rsregister1 is further connected to a gate of a third switch SW3, a source of the third switch SW3 is connected to a power supply through a second resistor R2, and a drain of the third switch SW3 is grounded through a second capacitor C2.
Preferably, the S2 input signal is an output signal of Vout signal after being connected to the second resistor R2 and the second capacitor C2 and passing through the second comparator 2.
Preferably, the drain of the third switch SW3 is further connected to the source of the fourth switch SW4, the gate of the fourth switch SW4 is connected to the q pin of the edge detector edge_detector, and the drain of the fourth switch SW4 is grounded.
Compared with the prior art, the application has the beneficial effects that:
the buck converter with constant switching frequency has a simple circuit structure, can perform rapid load current response and rapid input voltage response, and can realize stable voltage output.
Drawings
Fig. 1 is a schematic circuit diagram of a buck converter according to the present application.
Fig. 2 is a schematic circuit diagram of an SFC core circuit in the buck converter according to the present application.
Fig. 3 is a schematic diagram of the working principle of the SFC core circuit of the present application.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
Referring to fig. 1, fig. 1 shows a buck converter composed of an SFC core circuit and a telephone feedback loop, in which the buck converter mainly includes two core components, namely, the SFC core circuit and a voltage feedback loop cooperating with the SFC core circuit, in which two switching transistors, namely, a first switching transistor Q1 and a second switching transistor Q2 are disposed, a source of the first switching transistor Q1 is connected to an input signal VIN, a gate is connected to a PWM output signal of the SFC core circuit through a driver, a drain of the first switching transistor Q1 is connected to a source of the second switching transistor Q2, a gate of the second switching transistor Q2 is connected to the SFC core circuit through a driving, a drain of the first switching transistor Q1 and a drain of the second switching transistor Q2 are connected to an output voltage feedback signal vfb through a third resistor R3 and a fourth resistor R4, respectively, and the output voltage feedback signal vfb and a reference voltage VREF are input to the SFC core circuit as a pulse signal SFC through a comparator.
In fig. 2, a schematic diagram of an SFC core circuit is shown, where the SFC core circuit includes a first flip-flop rsregister1 and a second flip-flop rsregister2, an S pin of the first flip-flop rsregister1 and an S pin of the second flip-flop rsregister2 are connected to pulse signals, a q pin of the first flip-flop rsregister1 and a q pin of the second flip-flop rsregister2 are connected to a PWM output signal and an LDREN output signal, respectively, and an r pin of the first flip-flop rsregister1 and an r pin of the second flip-flop rsregister2 are connected to an S1 input signal and an S2 input signal, respectively.
In addition, the q pin of the first trigger rsregister1 is further connected to a gate of a first switch SW1, a source of the first switch SW1 is connected to a power supply through a first resistor R1, and a drain of the first switch SW1 is grounded through a first capacitor C1.
The S1 input signal is an output signal of Vin signal after being connected to the first resistor R1 and the first capacitor C1 and passing through the first comparator 1.
The drain electrode of the first switch SW1 is further connected to the source electrode of the second switch SW2, the gate electrode of the second switch SW2 is connected to the qb pin of the first trigger rsregister1, and the drain electrode of the second switch SW2 is grounded.
The q pin of the second trigger rsregister1 is further connected to a gate of a third switch SW3, a source of the third switch SW3 is connected to a power supply through a second resistor R2, and a drain of the third switch SW3 is grounded through a second capacitor C2.
The S2 input signal is an output signal after the Vout signal is connected to the second resistor R2 and the second capacitor C2 and then passes through the second comparator 2.
The drain of the third switch SW3 is further connected to the source of the fourth switch SW4, the gate of the fourth switch SW4 is connected to the q pin of the edge detector edge_detector, and the drain of the fourth switch SW4 is grounded.
The principle of the SFC core circuit is divided into two paths of filtering as follows:
first path RC filtering: the first resistor R1, the first capacitor C1 is connected to VIN and the first comparator1, and the circuit determines the voltage range of ramp_ton between kvout and gnd. The Pulse signal and the first comparator output signal S1 are input to the first trigger rstegister 1, and the PWM signal is output. The function realized by the method is to calculate the on time of the first switching tube Q1. Ton= (R1 x C1 x K x VOUT)/VIN; from this calculation formula, it can be seen that the change of VIN voltage can react in one period, so this architecture has a good VIN feedforward response capability.
Second path RC filtering: the second resistor R2, the second capacitor C2 is connected to VOUT and the second comparator2, and the circuit determines that the voltage range of ramp_t is between kvout and gnd. The Pulse signal and the second comparator output signal S2 are input to the second flip-flop rstegister 2, outputting the LDREN signal. The function this part of the circuit implements is to calculate the time of the switching cycle.
Switching period t= (r2×c2×kvout)/vout=r2×c2×k;
in general, r1=r2=r, c1=c2=c; the switching period T is determined by R, C and K. The switching period (frequency) is a constant value even in the case of different VIN and VOUT.
The following comparators function as devices in the SFC core circuit: when the positive input signal is higher than the negative input signal, the output is high; when the positive side input signal is lower than the negative side input signal, the output is low.
RS flip-flop: when the output signal of the R end is high, resetting the output signal Q; when the S-terminal input signal is high, the output signal Q is set high.
A switch SW turned on when the control signal is high; the control signal is turned off when low.
The falling edge detector edge_detector, when the input signal falls, the output signal Q is a short pulse signal, and the pulse high time is about 20nS.
At pwm=high; switch SW1 is turned on, VIN charges capacitor C1 through resistor R1, and when signal ramp_ton rises from gnd to Kvout voltage, first comparator1 outputs signal S1 high;
the first flip-flop rstegister 1 input signals are pulse and S1; when pulse=high, the first flip-flop is set high, and the output signal pwm=high; when s1=high, the first flip-flop is cleared, and the output signal pwm=low; at the same time pwmb=high, switch SW1 is off, SW2 is on, ramp_ton signal is pulled to gnd, and S1 signal goes low.
The second flip-flop rstegister 2 input signals are pulse and S2; when pulse=high, the second flip-flop is set high, the output signal ldren=high, and the switch SW3 is turned on. Vout charges the capacitor C2 through the resistor R2, and when the signal ramp_t rises from gnd to the voltage Kvout, the second comparator2 outputs the signal S2 to become high. The second flip-flop rsregister2 sets LDREN low, ldren=0; SW3 is closed; the edge detector outputs a pulse signal ldren_ed at the falling edge of LDREN, with a high level of about 20nS, during which time the switch SW4 is turned on, pulling ramp_t to gnd, and the S2 signal goes low.
For the working principle of the present application, referring to the circuit structures of fig. 1 and 2, the output voltage feedback signal vfb and the reference voltage are input to the comparator, which outputs the pulse signal. The whole SFC buck converter works as follows: when the feedback signal vfb is lower than vref, the pulse signal goes high; within the SFC core circuit, pulse sets PWM high through the first flip-flop rsregister1 while ramp_ton starts going up until kvout voltage, at which time the S1 signal goes high while PWM is set low. This is the calculation of the open time of the upper tube.
On the other hand, pulse goes high setting LDREN high by the second flip-flop rsregister2 while ramp_t starts going up until kvout voltage, at which time signal S2 goes high while LDREN is set low, as shown in fig. 3. This is the calculation of the switching period.
If LDREN goes low, pulse is still low, and at this time, both the first switching tube Q1 and the second switching tube Q2 are in the off state, and the buck converter is in skip mode.
If the output suddenly increases the output load before the S2 signal goes high, vfb is pulled low, at which time pulse goes high and the PWM value is immediately high, entering the next switching cycle. By adopting the control mode, the output load change can be immediately reacted to the loop control in one switching period, so that the quick response of the output load current is achieved.
Reference throughout this specification to "one embodiment," "another embodiment," "an embodiment," "a preferred embodiment," etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application as broadly described. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is intended that such feature, structure, or characteristic be implemented within the scope of the application.
Although the application has been described herein with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the scope and spirit of the principles of this disclosure. More specifically, various variations and modifications may be made to the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, drawings and claims. In addition to variations and modifications in the component parts and/or arrangements, other uses will be apparent to those skilled in the art.
Claims (1)
1. A buck converter with constant switching frequency, characterized by: the SFC core circuit comprises an SFC core circuit and a voltage feedback loop, wherein the voltage feedback loop comprises a first switch tube Q1 and a second switch tube Q2, the source electrode of the first switch tube Q1 is connected with a VIN input signal, the grid electrode of the first switch tube Q1 is connected with a PWM output signal of the SFC core circuit through a driver, the drain electrode of the first switch tube Q1 is connected with the source electrode of the second switch tube Q2, the drain electrodes of the first switch tube Q1 and the second switch tube Q2 are respectively connected with an output voltage feedback signal vfb through a third resistor R3 and a fourth resistor R4, the output voltage feedback signal vfb and a reference voltage VREF are used as a plus pulse signal after passing through a comparator and are input into the SFC core circuit, the SFC core circuit comprises a first trigger rsregister1 and a second trigger rsregister2, the S pin of the first trigger rsregister1 and the S pin of the second trigger rsregister2 are connected with the plus pulse signal, the Q pin of the first trigger rsregister1 and the Q pin of the second trigger rsregister2 are respectively connected with a PWM output signal and an LDREN output signal, the R pin of the first trigger rsregister1 and the R pin of the second trigger rsregister2 are respectively connected with an S1 input signal and an S2 input signal, the Q pin of the first trigger rsregister1 is also connected with a grid electrode of a first switch SW1, the source electrode of the first switch SW1 is connected with a power supply through a first resistor R1, the drain electrode of the first switch SW1 is grounded through a first capacitor C1, the S1 input signal is an output signal after VIN signals are connected with the first resistor R1 and the first capacitor C1 and then pass through a first comparator1, the drain electrode of the first switch SW1 is also connected with a source electrode of the second switch SW2, the grid electrode of the second switch SW2 is also connected with a grid electrode of the first trigger rsregister1, the drain electrode of the second switch SW2 is also connected with a drain electrode of the third switch SW3, the source of the third switch SW3 is connected to the power supply through a second resistor R2, the drain of the third switch SW3 is grounded through a second capacitor C2, the S2 input signal is an output signal after the Vout signal is connected to the second resistor R2 and the second capacitor C2 and passes through a second comparator2, the drain of the third switch SW3 is further connected to the source of the fourth switch SW4, the gate of the fourth switch SW4 is connected to the q pin of the edge detector, and the drain of the fourth switch SW4 is grounded.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811526413.8A CN109286318B (en) | 2018-12-13 | 2018-12-13 | Step-down converter with constant switching frequency |
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| CN201811526413.8A CN109286318B (en) | 2018-12-13 | 2018-12-13 | Step-down converter with constant switching frequency |
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| CN109286318B true CN109286318B (en) | 2023-10-27 |
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| CN109286318A (en) | 2019-01-29 |
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