US20040245530A1 - Optical semiconductor device and method of manufacturing same - Google Patents

Optical semiconductor device and method of manufacturing same Download PDF

Info

Publication number
US20040245530A1
US20040245530A1 US10/812,454 US81245404A US2004245530A1 US 20040245530 A1 US20040245530 A1 US 20040245530A1 US 81245404 A US81245404 A US 81245404A US 2004245530 A1 US2004245530 A1 US 2004245530A1
Authority
US
United States
Prior art keywords
optical semiconductor
sealing resin
semiconductor element
portions
covering layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/812,454
Inventor
Koujiro Kameyama
Kiyoshi Mita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kanto Sanyo Semiconductors Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Kanto Sanyo Semiconductors Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kanto Sanyo Semiconductors Co Ltd, Sanyo Electric Co Ltd filed Critical Kanto Sanyo Semiconductors Co Ltd
Assigned to KANTO SANYO SEMICONDUCTORS CO., LTD., SANYO ELECTRIC CO., LTD. reassignment KANTO SANYO SEMICONDUCTORS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MITA, KIYOSHI, KAMEYAMA, KOUJIRO
Publication of US20040245530A1 publication Critical patent/US20040245530A1/en
Priority to US11/537,496 priority Critical patent/US7728438B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52Encapsulations
    • H01L33/54Encapsulations having a particular shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14618Containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14683Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0203Containers; Encapsulations, e.g. encapsulation of photodiodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02377Fan-in arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05008Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05569Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05575Plural external layers
    • H01L2224/0558Plural external layers being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13023Disposition the whole bump connector protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13025Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01012Magnesium [Mg]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0102Calcium [Ca]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483Containers
    • H01L33/486Containers adapted for surface mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52Encapsulations
    • H01L33/56Materials, e.g. epoxy or silicone resin

Definitions

  • the present invention relates to an optical semiconductor device in which an optical semiconductor element including a light-receiving or light-emitting portion is accommodated.
  • CSP chip size packages
  • FIG. 7 shows a CSP 66 with a size slightly larger than a chip size, in which a glass epoxy substrate 65 is employed as a supporting substrate. A description will be given here assuming that a transistor chip T is mounted on the glass epoxy substrate 65 .
  • First and second electrodes 67 , 68 and a die pad 69 are formed on a surface of this glass epoxy substrate 65 , and first and second back electrodes 70 and 71 are formed on a back of the glass epoxy substrate 65 .
  • the first electrode 67 and first back electrode 70 , as well as the second electrode 68 and second back electrode 71 are electrically connected through a through-hole TH.
  • the bare transistor chip T is fixed to the die pad 69 .
  • An emitter electrode of the transistor and the first electrode 67 are connected by a thin-metal wire 72
  • a base electrode of the transistor and the second electrode 68 are connected by another thin metal wire 72 .
  • a resin layer 73 is provided on the glass epoxy substrate 65 so as to cover the transistor chip T.
  • the CSP 66 unlike a wafer scale CSP, has a simple elongating structure from the transistor chip T up to the back electrodes 70 and 71 for external connection, and therefore has a merit of being able to be manufactured at low costs.
  • the embodiment of the present invention was accomplished in the light of the above-mentioned problems, and a primary object of the embodiment of the present invention is to provide an optical semiconductor device of which the moisture resistance and the like are improved, and a manufacturing method thereof.
  • the optical semiconductor device of the embodiment of the present invention includes an optical semiconductor element having a circuit portion including any one of a light-receiving element and a light-emitting element on a surface thereof; a terminal portion which is provided on a back of the optical semiconductor element and electrically connected with the circuit portion; a covering layer which covers the surface of the optical semiconductor element and is made of a transparent material; and sealing resin which covers side surfaces of the optical semiconductor element.
  • the method of manufacturing the optical semiconductor device of the embodiment of present invention includes: preparing a wafer having a plurality of circuit portions each including anyone of a light-receiving element and a light-emitting element on a surface thereof; separating the wafer into individual optical semiconductor elements by forming separating grooves from a back surface of the wafer so that the wafer is separated; providing terminal portions electrically connected with the circuit portions on back surface of the optical semiconductor elements; forming sealing resin so that at least the separating grooves are filled with the sealing resin; and separating individual optical semiconductor devices from each other along the separating grooves.
  • FIG. 1A is a sectional view of an optical semiconductor device of an embodiment according to the present invention
  • FIG. 1B is a sectional view of an optical semiconductor device according to another embodiment of the present invention.
  • FIGS. 2A and 2B are a plan view and a sectional view, respectively, showing a method of manufacturing the optical semiconductor device of the present invention.
  • FIGS. 3A and 3B are a plan view and a sectional view, respectively, showing the method of manufacturing the optical semiconductor device of the present invention.
  • FIGS. 4A and 4B are sectional views showing the method of manufacturing the optical semiconductor device of the present invention.
  • FIGS. 5A to 5 C are sectional views showing the method of manufacturing the optical semiconductor device of the present invention.
  • FIGS. 6A to 6 D are sectional views showing another method of manufacturing the optical semiconductor device of the present invention.
  • FIG. 7 is a sectional view showing a conventional optical semiconductor device.
  • FIG. 1A is a sectional view of an optical semiconductor device 10 A
  • FIG. 1B is a sectional view of an optical semiconductor device 10 B of another embodiment.
  • the optical semiconductor device 10 A of the present embodiment is configured to include an optical semiconductor element 11 on a surface of which a circuit portion 21 including a light-receiving or light-emitting element is formed; terminal portions 17 which are provided on a back of the optical semiconductor element 11 and electrically connected with the circuit portion 21 ; a covering layer 12 which covers the surface of the optical semiconductor element 11 and is made of a transparent material; and sealing resin 16 which covers side faces of the optical semiconductor element 11 .
  • an optical semiconductor element 11 on a surface of which a circuit portion 21 including a light-receiving or light-emitting element is formed
  • terminal portions 17 which are provided on a back of the optical semiconductor element 11 and electrically connected with the circuit portion 21
  • a covering layer 12 which covers the surface of the optical semiconductor element 11 and is made of a transparent material
  • sealing resin 16 which covers side faces of the optical semiconductor element 11 .
  • the covering layer 12 is adhered to the surface of the optical semiconductor element 11 with adhesive resin 13 interposed therebetween so as to protect the circuit portion 21 formed on the surface of the optical semiconductor element 11 .
  • a transparent material is used which transmits light to be inputted into the optical semiconductor element 11 or light emitted from the optical semiconductor element 11 .
  • the optical semiconductor element 11 is an element which detects visible light
  • a material with transparency to the visible light is employed as the covering layer 12 .
  • glass, acrylic sheet, or the like can be employed as the covering layer 12 .
  • the optical semiconductor element 11 is an imaging device such as a CCD image sensor, a filter or the like is added.
  • a light-receiving or light-emitting element can be employed.
  • a solid-state imaging device such as a charge coupled device (CCD) image sensor or complementary metal oxide semiconductor (CMOS) image sensor, or a photo sensor such as a photo diode or photo transistor can be employed as the optical semiconductor element 11 .
  • CMOS complementary metal oxide semiconductor
  • a photo sensor such as a photo diode or photo transistor
  • a light-emitting element a light-emitting diode, a semiconductor laser, or the like can be employed as the optical semiconductor element 11 .
  • Rewiring patterns 15 are conductive patterns which electrically connect the circuit portion 21 of the optical semiconductor element 11 and the terminal portions 17 provided on the back surface of the optical semiconductor element 11 .
  • Rewiring patterns detour along side surface portions of the optical semiconductor element 11 , the rewiring patterns 15 electrically connect the circuit portion 21 and the terminal portions 17 .
  • a metal mainly containing Cu, a metal mainly containing Al, or an alloy containing Au, conductive paste and the like is used for the material of the rewiring patterns 15 .
  • a surface of each of the rewiring patterns 15 is covered with an insulating layer, thus achieving insulation from the optical semiconductor element 11 .
  • Each of the side surface portions of the optical semiconductor element 11 is formed to be an inclined face. Specifically, an angle a between the main face of the optical semiconductor element 11 where the circuit portion 21 is formed and each side face portion thereof is an acute angle.
  • This structure facilitates the formation of the rewiring patterns 15 on the side face portions of the optical semiconductor element 11 , a detailed description of which will be given later in the description of the manufacturing method.
  • the sealing resin 16 covers the side face portions of the optical semiconductor element 11 and of the covering layer 12 . Further, the back surface of the optical semiconductor element 11 is also covered with the sealing resin 16 , and bump electrodes 18 are formed on the terminal portions 17 which are exposed from the sealing resin 16 at given positions. In this way, the covering layer 12 is exposed on a face of the optical semiconductor device 10 A through which the optical semiconductor element 11 performs receiving light or emitting light, and the other faces of the optical semiconductor device 10 A are formed of the sealing resin 16 .
  • the sealing resin 16 it is possible to employ a light blocking material into which an inorganic filler is mixed for the improvement in mechanical strength and moisture resistance.
  • thermoplastic resin or thermosetting resin can be employed generally.
  • the thermoplastic resin applicable to the present embodiment includes, for example, ABS resin, polypropylene, polyethylene, polystyrene, acrylic, polyethylene terephthalate, polyphenylene ether, nylon, polyamide, polycarbonate, polyacetal, polybutylene terephthalate, polyphenylene sulfide, polyether ether ketone, liquid crystal polymer, fluororesin, polyurethane resin, and elastomer.
  • the thermosetting resin applicable to the present embodiment includes, for example, urea, phenol, melamine, furan, alkyd, unsaturated polyester, diallyl phthalate, epoxy, silicon resin, and polyeurethane.
  • the adhesive resin 13 is made of epoxy resin or the like and has a function to adhere the covering layer 12 to the optical semiconductor element 11 . Moreover, in order to transmit the light which the optical semiconductor element 11 emits or receives, the adhesive resin 13 has transparency at approximately the same degree as that of the covering layer 12 . It is also possible to employ an adhesive tape as the adhesive resin 13 . In addition, it is also possible to constitute a hollow structure by forming the adhesive resin only at the peripheral portion, of the optical semiconductor element 11 .
  • An insulating layer 14 has a function to cover a face of the optical semiconductor element 11 where the circuit portion 21 is not formed.
  • the rewiring patterns 15 are allowed to elongate to an upper face of the insulating layer 14 , where the terminal portions 17 are formed on the rewiring patterns 15 .
  • a resin or the like with insulating properties can be employed generally, and similarly to the covering layer 12 , glass or acrylic resin can also be employed.
  • the terminal portions 17 have a function to electrically connect the outside and the rewiring patterns 15 elongating past the insulating layer 14 up to the back side of the optical semiconductor element 11 .
  • One end of each of the terminal portions 17 is connected to each of the rewiring patterns 15 , and the other end thereof is exposed from the sealing resin 16 .
  • the terminal portions 17 are made of a conductive member, for which the same material as the rewiring patterns 15 can be employed.
  • An outer face of the sealing resin 16 where the terminal portions 17 are exposed and the exposed faces of the terminal portions 17 are positioned on the same plane.
  • the bump electrodes 18 which are made of a solder material, are adhered to the exposed terminal portions 17 .
  • FIG. 1B A description will be given of the optical semiconductor device 10 B of another configuration with reference to FIG. 1B.
  • a basic configuration of the optical semiconductor device 10 B shown in FIG. 1B is similar to that of the optical semiconductor device 10 A described above but different therefrom in the elongating structure of the rewiring patterns 15 up to the back of the optical semiconductor element 11 . Focusing on this different point, the configuration of the optical semiconductor device 10 B will be described below.
  • the rewiring patterns 15 are electrically connected with the circuit portion 21 provided on the surface of the optical semiconductor element 11 .
  • the rewiring patterns 15 exist only on the surface of the optical semiconductor element 11 .
  • the optical semiconductor element 11 is perforated at positions where the rewiring patterns 15 are formed with via holes for penetrating electrodes which penetrate the element. These via holes are filled with a conductive material, thereby forming posts 19 .
  • the posts 19 penetrate the optical semiconductor element 11 and the insulating layer 14 , and one end of each of the posts 19 is electrically connected with each of the rewiring patterns 15 .
  • the other end of each of the posts 19 serves as the terminal portion 17 and is exposed from the sealing resin 16 to the outside.
  • the bump electrodes 18 are formed on the exposed faces of the terminal portions 17 . That is, since the rewiring patterns 15 and the bump electrodes 18 are electrically connected by the posts 19 , they can be connected with the shortest distance therebetween.
  • a surface of each of the posts 19 is covered with an insulating resin, thus achieving insulation from the inner wall of the optical semiconductor element 11 .
  • An advantage of the embodiment exists in that the side faces of the optical semiconductor element 11 and of the covering layer 12 are covered with the sealing resin 16 .
  • the covering layer 12 is adhered to the surface of the optical semiconductor element 11 , and the sealing resin 16 covers the side faces of both of them. Furthermore, an interface portion between the optical semiconductor element 11 and the covering layer 12 is also covered with the sealing resin 16 . Accordingly, it is possible to prevent water from entering the inside of the optical semiconductor device 10 from the interface portion between the optical semiconductor element 11 and the covering layer 12 .
  • the sealing resin 16 seals the entire optical semiconductor element 11 including the back thereof. Accordingly, since the components exposed to the outside, except the covering layer 12 and the terminal portion 17 , are covered with the sealing resin 16 , it is possible to further improve the moisture resistance and the like of the optical semiconductor device 10 .
  • the rewiring patterns 15 detour along the side surfaces of the optical semiconductor element 11 and are connected to the terminal portions 17 as shown in FIG. 1A, the rewiring patterns 15 formed on the side face portions of the optical semiconductor element 11 are protected by the sealing resin 16 . Accordingly, it is possible to prevent breakage of the rewiring patterns 15 .
  • the method of manufacturing the optical semiconductor device 10 includes the steps of preparing a wafer 20 on a surface of which a plurality of the circuit portions 21 including light-receiving or light-emitting elements are formed; separating the wafer 20 into the individual optical semiconductor elements 11 by forming separating grooves 24 from the back of the wafer 20 so that the wafer 20 is separated; providing the terminal portions 17 electrically connected with the circuit portions 21 on the backs of the optical semiconductor elements 11 ; forming the sealing resin 16 so that at least the separating grooves 24 are filled with the sealing resin 16 ; and separating the individual optical semiconductor devices 10 from each other along the separating grooves 24 .
  • Each of these steps will be described below.
  • the wafer 20 is prepared, on the surface of which a plurality of the circuit portions 21 including light-receiving or light-emitting elements are formed, and then the transparent covering layer 12 is adhered onto the surface of the wafer 20 so as to cover the circuit portions 21 .
  • a large number of the circuit portions 21 are formed in matrix through a diffusion process and the like on the wafer 20 made of a semiconductor such as silicon.
  • An identical circuit including a light-receiving or light-emitting element is formed for each circuit portion 21 .
  • each of the circuit portions 21 is electrically connected with the rewiring patterns 15 .
  • the covering layer 12 is adhered with the adhesive resin 13 onto the face of the wafer 20 where the circuit portions 21 are formed.
  • the covering layer 12 transparent glass, acrylic resin or the like can be employed.
  • the adhesive resin 13 transparent epoxy resin or the like can be employed.
  • a sheet 22 is adhered onto a surface of the covering layer 12 . With this sheet 22 , it is possible to prevent the covering layer 12 from being damaged in the subsequent processes. Moreover, it is also possible to prevent the optical semiconductor devices 10 from coming apart until the last process.
  • the wafer 20 may be thinned by abrading, such as grinding, or etching of the back of the wafer 20 .
  • the wafer 20 is separated into the individual optical semiconductor elements 11 by forming the separating grooves 24 from the back of the wafer 20 so that the wafer 20 is separated.
  • dicing is performed along dicing lines 22 that are the borders between the circuit portions 21 by use of a dicing blade 23 .
  • the depth to be made by dicing is set to such a depth or more that at least the wafer 20 is divided to form the individual optical semiconductor elements 11 .
  • dicing is performed so that both the wafer 20 and the covering layer 12 are divided.
  • the adhesive resin 13 and the rewiring patterns 15 are also subjected to the dicing in portions corresponding to the dicing lines 22 .
  • the side faces of the optical semiconductor elements 11 and of the covering layers 12 are formed to be inclined faces. The fact that the side faces of the optical semiconductor elements 11 are inclined faces facilitates the formation of the rewiring patterns 15 on the side face portions of the optical semiconductor elements 11 in the subsequent processes.
  • the dicing may be performed to such an extent that the sheet 22 is partly cut. Even if the coveting layers 12 and the optical semiconductor elements 11 are separated, since the covering layers 12 are adhered to the single sheet 22 , there is a merit that the devices do not come apart until the last process.
  • the back of each of the optical semiconductor elements 11 is protected by the insulating layer 14 .
  • dicing may be performed for simultaneously with the other members.
  • the insulating layer 14 may be formed after dicing is performed.
  • the terminal portions 17 electrically connected with the circuit portions 21 are provided on the back surface of the optical semiconductor elements 11 .
  • the rewiring patterns 15 are allowed to elongate up to the upper faces of the insulating layer 14 .
  • the material of the rewiring patterns 15 is Al, Ag, Au, Pt, Pd, conductive paste, or the like, and the rewiring patterns 15 are formed by evaporation, sputtering, deposition such as CVD under low or high vacuum, electroplating, electroless plating, sintering, or the like.
  • the side face portions of the optical semiconductor elements 11 are inclined faces, which facilitates the formation of the rewiring patterns 15 using the above-mentioned method.
  • the rewiring patterns 15 are formed by sputtering in particular, it is possible to more surely perform the deposition of the material owing to the fact that the side faces of the optical semiconductor elements 11 are inclined faces.
  • the terminal portions 17 electrically connected with the rewiring patterns 15 are formed.
  • the formation of the terminal portions 17 can be performed, for example, by arraying solder balls using a transfer method.
  • the sealing resin 16 is formed so that at least the separating grooves 24 are filled with the sealing resin 16 , and then the individual optical semiconductor devices 10 are separated from each other along the separating grooves 24 .
  • the sealing resin 16 is formed so as to fill the separating grooves 24 and cover the terminal portions 17 .
  • the sealing resin 16 is formed so as to cover the entire wafer 20 .
  • the formation of the sealing resin 16 can be performed by a sealing or casting method using a mold, vacuum printing, or the like.
  • the terminal portions 17 are exposed from the sealing resin 16 .
  • This process can be performed by grinding the sealing resin 16 by use of a grinding attachment. Accordingly, an upper face of the resultant, which is formed of the sealing resin 16 , is formed to be a planer face, making a structure in which the terminal portions 17 are exposed from this face.
  • the bump electrodes 18 made of solder or the like are formed on the exposed terminal portions 17 .
  • the exposed terminal portions 17 may be plated, and ball electrodes may be formed on the exposed terminal portions 17 .
  • dicing is performed along the separating grooves 24 , thus separating the optical semiconductor devices from each other. Since only the sealing resin 16 is cut in this dicing, a process can be realized where abrasion on the dicing blade is reduced. Thereafter, a process of testing and the removal of the sheet 22 are performed to complete the optical semiconductor devices 10 A, for example, as shown in FIG. 1A.
  • FIG. 6A shows a process of separating the wafer 20 into the optical semiconductor elements 11 by dicing
  • FIG. 6B shows a process of allowing the rewiring patterns 15 to elongate up to the backs of the optical semiconductor elements 11 and providing the terminal portions 17
  • FIG. 6C shows a state where, after sealing with resin, the terminal portions 17 are exposed therefrom and the bump electrodes 18 are formed on the terminal portions 17
  • FIG. 6D shows a state where the sealing resin 16 and the covering layer 12 are subjected to dicing at the separating grooves 24 , thus separating the individual optical semiconductor devices 10 from each other.
  • the prevent embodiment can have beneficial effects as follows.
  • the sealing resin 16 since the side faces of the covering layer 12 and of the optical semiconductor element 11 are protected by the sealing resin 16 , it is possible to provide the optical semiconductor device 10 of which the moisture resistance, heat resistance, and mechanical strength are improved. Moreover, since part of the rewiring patterns 15 elongating along the side faces of the optical semiconductor element 11 is protected by the sealing resin 16 , it is possible to make a structure in which the rewiring patterns 15 are prevented from breaking.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Light Receiving Elements (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Led Device Packages (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Led Devices (AREA)

Abstract

An optical semiconductor device of which the moisture resistance and the like are improved and the manufacturing method thereof are provided. An optical semiconductor device of the embodiment is configured to include an optical semiconductor element on a surface of which a circuit portion including a light-receiving or light-emitting element is formed; a terminal portion which is provided on a back of the optical semiconductor element and electrically connected with the circuit portion; a covering layer which covers the surface of the optical semiconductor element and is made of a transparent material; and sealing resin which covers side faces of the covering layer and of the optical semiconductor element. The circuit portion and the terminal portion may be connected by a rewiring pattern.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to an optical semiconductor device in which an optical semiconductor element including a light-receiving or light-emitting portion is accommodated. [0002]
  • 2. Description of the Related Art [0003]
  • Since circuit devices to be set in electronic equipment are used in a mobile phone, a portable computer, and the like, there has been a demand for reduction in size, thickness and weight of the circuit devices. Taking a semiconductor device as an example of the circuit devices, chip size packages (CSP) have been developed. The size of CSP is equal to chip size or, slightly larger than a chip size. [0004]
  • FIG. 7 shows a CSP [0005] 66 with a size slightly larger than a chip size, in which a glass epoxy substrate 65 is employed as a supporting substrate. A description will be given here assuming that a transistor chip T is mounted on the glass epoxy substrate 65.
  • First and [0006] second electrodes 67, 68 and a die pad 69 are formed on a surface of this glass epoxy substrate 65, and first and second back electrodes 70 and 71 are formed on a back of the glass epoxy substrate 65. The first electrode 67 and first back electrode 70, as well as the second electrode 68 and second back electrode 71, are electrically connected through a through-hole TH. The bare transistor chip T is fixed to the die pad 69. An emitter electrode of the transistor and the first electrode 67 are connected by a thin-metal wire 72, and a base electrode of the transistor and the second electrode 68 are connected by another thin metal wire 72. Moreover, a resin layer 73 is provided on the glass epoxy substrate 65 so as to cover the transistor chip T.
  • Although the [0007] glass epoxy substrate 65 is used in the CSP 66, the CSP 66, unlike a wafer scale CSP, has a simple elongating structure from the transistor chip T up to the back electrodes 70 and 71 for external connection, and therefore has a merit of being able to be manufactured at low costs.
  • In the CSP [0008] 66 explained above, however, the resin layer 73 covering the transistor chip T is only in contact with a surface portion of the glass epoxy substrate 65. Accordingly, during the process of mounting the CSP 66 and/or in the state where the CSP 66 is being used, water enters from the outside into the interface between the glass epoxy substrate 65 and the resin layer 73. This fact has led to degradation in the moisture resistance of the CSP 66. Moreover, from the same reason as above, there has been a problem of weak adhesion between the glass epoxy substrate 65 and the resin layer 73.
  • SUMMARY OF THE INVENTION
  • The embodiment of the present invention was accomplished in the light of the above-mentioned problems, and a primary object of the embodiment of the present invention is to provide an optical semiconductor device of which the moisture resistance and the like are improved, and a manufacturing method thereof. [0009]
  • The optical semiconductor device of the embodiment of the present invention includes an optical semiconductor element having a circuit portion including any one of a light-receiving element and a light-emitting element on a surface thereof; a terminal portion which is provided on a back of the optical semiconductor element and electrically connected with the circuit portion; a covering layer which covers the surface of the optical semiconductor element and is made of a transparent material; and sealing resin which covers side surfaces of the optical semiconductor element. [0010]
  • The method of manufacturing the optical semiconductor device of the embodiment of present invention includes: preparing a wafer having a plurality of circuit portions each including anyone of a light-receiving element and a light-emitting element on a surface thereof; separating the wafer into individual optical semiconductor elements by forming separating grooves from a back surface of the wafer so that the wafer is separated; providing terminal portions electrically connected with the circuit portions on back surface of the optical semiconductor elements; forming sealing resin so that at least the separating grooves are filled with the sealing resin; and separating individual optical semiconductor devices from each other along the separating grooves.[0011]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1A is a sectional view of an optical semiconductor device of an embodiment according to the present invention, and FIG. 1B is a sectional view of an optical semiconductor device according to another embodiment of the present invention. [0012]
  • FIGS. 2A and 2B are a plan view and a sectional view, respectively, showing a method of manufacturing the optical semiconductor device of the present invention. [0013]
  • FIGS. 3A and 3B are a plan view and a sectional view, respectively, showing the method of manufacturing the optical semiconductor device of the present invention. [0014]
  • FIGS. 4A and 4B are sectional views showing the method of manufacturing the optical semiconductor device of the present invention. [0015]
  • FIGS. 5A to [0016] 5C are sectional views showing the method of manufacturing the optical semiconductor device of the present invention.
  • FIGS. 6A to [0017] 6D are sectional views showing another method of manufacturing the optical semiconductor device of the present invention.
  • FIG. 7 is a sectional view showing a conventional optical semiconductor device.[0018]
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • A description will be given of a configuration of an optical semiconductor device [0019] 10 of the present embodiment with reference to FIGS. 1A and 1B. FIG. 1A is a sectional view of an optical semiconductor device 10A, and FIG. 1B is a sectional view of an optical semiconductor device 10B of another embodiment.
  • Referring to FIG. 1A, the [0020] optical semiconductor device 10A of the present embodiment is configured to include an optical semiconductor element 11 on a surface of which a circuit portion 21 including a light-receiving or light-emitting element is formed; terminal portions 17 which are provided on a back of the optical semiconductor element 11 and electrically connected with the circuit portion 21; a covering layer 12 which covers the surface of the optical semiconductor element 11 and is made of a transparent material; and sealing resin 16 which covers side faces of the optical semiconductor element 11. A detailed description will be given below of each of these components.
  • The covering [0021] layer 12 is adhered to the surface of the optical semiconductor element 11 with adhesive resin 13 interposed therebetween so as to protect the circuit portion 21 formed on the surface of the optical semiconductor element 11. For the material of the covering layer 12, a transparent material is used which transmits light to be inputted into the optical semiconductor element 11 or light emitted from the optical semiconductor element 11. For example, when the optical semiconductor element 11 is an element which detects visible light, a material with transparency to the visible light is employed as the covering layer 12. Specifically, glass, acrylic sheet, or the like can be employed as the covering layer 12. Further, when the optical semiconductor element 11 is an imaging device such as a CCD image sensor, a filter or the like is added.
  • For the [0022] optical semiconductor element 11, a light-receiving or light-emitting element can be employed. For the light-receiving element, a solid-state imaging device such as a charge coupled device (CCD) image sensor or complementary metal oxide semiconductor (CMOS) image sensor, or a photo sensor such as a photo diode or photo transistor can be employed as the optical semiconductor element 11. For the light-emitting element, a light-emitting diode, a semiconductor laser, or the like can be employed as the optical semiconductor element 11.
  • [0023] Rewiring patterns 15 are conductive patterns which electrically connect the circuit portion 21 of the optical semiconductor element 11 and the terminal portions 17 provided on the back surface of the optical semiconductor element 11. In this embodiment, Rewiring patterns detour along side surface portions of the optical semiconductor element 11, the rewiring patterns 15 electrically connect the circuit portion 21 and the terminal portions 17. For the material of the rewiring patterns 15, a metal mainly containing Cu, a metal mainly containing Al, or an alloy containing Au, conductive paste and the like is used. Moreover, a surface of each of the rewiring patterns 15 is covered with an insulating layer, thus achieving insulation from the optical semiconductor element 11.
  • Each of the side surface portions of the [0024] optical semiconductor element 11 is formed to be an inclined face. Specifically, an angle a between the main face of the optical semiconductor element 11 where the circuit portion 21 is formed and each side face portion thereof is an acute angle. This structure facilitates the formation of the rewiring patterns 15 on the side face portions of the optical semiconductor element 11, a detailed description of which will be given later in the description of the manufacturing method.
  • The [0025] sealing resin 16 covers the side face portions of the optical semiconductor element 11 and of the covering layer 12. Further, the back surface of the optical semiconductor element 11 is also covered with the sealing resin 16, and bump electrodes 18 are formed on the terminal portions 17 which are exposed from the sealing resin 16 at given positions. In this way, the covering layer 12 is exposed on a face of the optical semiconductor device 10A through which the optical semiconductor element 11 performs receiving light or emitting light, and the other faces of the optical semiconductor device 10A are formed of the sealing resin 16. For the sealing resin 16, it is possible to employ a light blocking material into which an inorganic filler is mixed for the improvement in mechanical strength and moisture resistance. For the inorganic filler, for example, an aluminum compound, calcium compound, kalium compound, magnesium compound, or silicon compound can be employed. For the resin used in the sealing resin 16, a thermoplastic resin or thermosetting resin can be employed generally. The thermoplastic resin applicable to the present embodiment includes, for example, ABS resin, polypropylene, polyethylene, polystyrene, acrylic, polyethylene terephthalate, polyphenylene ether, nylon, polyamide, polycarbonate, polyacetal, polybutylene terephthalate, polyphenylene sulfide, polyether ether ketone, liquid crystal polymer, fluororesin, polyurethane resin, and elastomer. The thermosetting resin applicable to the present embodiment includes, for example, urea, phenol, melamine, furan, alkyd, unsaturated polyester, diallyl phthalate, epoxy, silicon resin, and polyeurethane.
  • The [0026] adhesive resin 13 is made of epoxy resin or the like and has a function to adhere the covering layer 12 to the optical semiconductor element 11. Moreover, in order to transmit the light which the optical semiconductor element 11 emits or receives, the adhesive resin 13 has transparency at approximately the same degree as that of the covering layer 12. It is also possible to employ an adhesive tape as the adhesive resin 13. In addition, it is also possible to constitute a hollow structure by forming the adhesive resin only at the peripheral portion, of the optical semiconductor element 11.
  • An insulating [0027] layer 14 has a function to cover a face of the optical semiconductor element 11 where the circuit portion 21 is not formed. The rewiring patterns 15 are allowed to elongate to an upper face of the insulating layer 14, where the terminal portions 17 are formed on the rewiring patterns 15. For the material of the insulating layer 14, a resin or the like with insulating properties can be employed generally, and similarly to the covering layer 12, glass or acrylic resin can also be employed.
  • The [0028] terminal portions 17 have a function to electrically connect the outside and the rewiring patterns 15 elongating past the insulating layer 14 up to the back side of the optical semiconductor element 11. One end of each of the terminal portions 17 is connected to each of the rewiring patterns 15, and the other end thereof is exposed from the sealing resin 16. The terminal portions 17 are made of a conductive member, for which the same material as the rewiring patterns 15 can be employed. An outer face of the sealing resin 16 where the terminal portions 17 are exposed and the exposed faces of the terminal portions 17 are positioned on the same plane. The bump electrodes 18, which are made of a solder material, are adhered to the exposed terminal portions 17.
  • A description will be given of the [0029] optical semiconductor device 10B of another configuration with reference to FIG. 1B. A basic configuration of the optical semiconductor device 10B shown in FIG. 1B is similar to that of the optical semiconductor device 10A described above but different therefrom in the elongating structure of the rewiring patterns 15 up to the back of the optical semiconductor element 11. Focusing on this different point, the configuration of the optical semiconductor device 10B will be described below.
  • The [0030] rewiring patterns 15 are electrically connected with the circuit portion 21 provided on the surface of the optical semiconductor element 11. In this embodiment, the rewiring patterns 15 exist only on the surface of the optical semiconductor element 11. The optical semiconductor element 11 is perforated at positions where the rewiring patterns 15 are formed with via holes for penetrating electrodes which penetrate the element. These via holes are filled with a conductive material, thereby forming posts 19.
  • The posts [0031] 19 penetrate the optical semiconductor element 11 and the insulating layer 14, and one end of each of the posts 19 is electrically connected with each of the rewiring patterns 15. The other end of each of the posts 19 serves as the terminal portion 17 and is exposed from the sealing resin 16 to the outside. The bump electrodes 18 are formed on the exposed faces of the terminal portions 17. That is, since the rewiring patterns 15 and the bump electrodes 18 are electrically connected by the posts 19, they can be connected with the shortest distance therebetween. In addition, a surface of each of the posts 19 is covered with an insulating resin, thus achieving insulation from the inner wall of the optical semiconductor element 11.
  • An advantage of the embodiment exists in that the side faces of the [0032] optical semiconductor element 11 and of the covering layer 12 are covered with the sealing resin 16. To be more specific, the covering layer 12 is adhered to the surface of the optical semiconductor element 11, and the sealing resin 16 covers the side faces of both of them. Furthermore, an interface portion between the optical semiconductor element 11 and the covering layer 12 is also covered with the sealing resin 16. Accordingly, it is possible to prevent water from entering the inside of the optical semiconductor device 10 from the interface portion between the optical semiconductor element 11 and the covering layer 12.
  • Moreover, the sealing [0033] resin 16 seals the entire optical semiconductor element 11 including the back thereof. Accordingly, since the components exposed to the outside, except the covering layer 12 and the terminal portion 17, are covered with the sealing resin 16, it is possible to further improve the moisture resistance and the like of the optical semiconductor device 10.
  • Furthermore, when the [0034] rewiring patterns 15 detour along the side surfaces of the optical semiconductor element 11 and are connected to the terminal portions 17 as shown in FIG. 1A, the rewiring patterns 15 formed on the side face portions of the optical semiconductor element 11 are protected by the sealing resin 16. Accordingly, it is possible to prevent breakage of the rewiring patterns 15.
  • Next, a description will be given of a method of manufacturing the optical semiconductor device [0035] 10 with reference to FIGS. 2A to 6D. The method of manufacturing the optical semiconductor device 10 according to the present embodiment includes the steps of preparing a wafer 20 on a surface of which a plurality of the circuit portions 21 including light-receiving or light-emitting elements are formed; separating the wafer 20 into the individual optical semiconductor elements 11 by forming separating grooves 24 from the back of the wafer 20 so that the wafer 20 is separated; providing the terminal portions 17 electrically connected with the circuit portions 21 on the backs of the optical semiconductor elements 11; forming the sealing resin 16 so that at least the separating grooves 24 are filled with the sealing resin 16; and separating the individual optical semiconductor devices 10 from each other along the separating grooves 24. Each of these steps will be described below.
  • A description will be given first of a method of manufacturing the [0036] optical semiconductor device 10A shown in FIG. 1A with reference to FIGS. 2A to 5C.
  • First, referring to FIGS. 2A and 2B, the [0037] wafer 20 is prepared, on the surface of which a plurality of the circuit portions 21 including light-receiving or light-emitting elements are formed, and then the transparent covering layer 12 is adhered onto the surface of the wafer 20 so as to cover the circuit portions 21.
  • Referring to FIG. 2A, a large number of the [0038] circuit portions 21 are formed in matrix through a diffusion process and the like on the wafer 20 made of a semiconductor such as silicon. An identical circuit including a light-receiving or light-emitting element is formed for each circuit portion 21. Moreover, each of the circuit portions 21 is electrically connected with the rewiring patterns 15.
  • Referring to FIG. 2B, the covering [0039] layer 12 is adhered with the adhesive resin 13 onto the face of the wafer 20 where the circuit portions 21 are formed. For the covering layer 12, transparent glass, acrylic resin or the like can be employed. For the adhesive resin 13, transparent epoxy resin or the like can be employed. In addition, a sheet 22 is adhered onto a surface of the covering layer 12. With this sheet 22, it is possible to prevent the covering layer 12 from being damaged in the subsequent processes. Moreover, it is also possible to prevent the optical semiconductor devices 10 from coming apart until the last process. The wafer 20 may be thinned by abrading, such as grinding, or etching of the back of the wafer 20.
  • Next, referring to FIGS. 3A and 3B, the [0040] wafer 20 is separated into the individual optical semiconductor elements 11 by forming the separating grooves 24 from the back of the wafer 20 so that the wafer 20 is separated.
  • Referring to FIG. 3A, dicing is performed along dicing [0041] lines 22 that are the borders between the circuit portions 21 by use of a dicing blade 23.
  • Referring to FIG. 3B, a section which has been made by dicing will be described. The depth to be made by dicing is set to such a depth or more that at least the [0042] wafer 20 is divided to form the individual optical semiconductor elements 11. In this embodiment, dicing is performed so that both the wafer 20 and the covering layer 12 are divided. Moreover, the adhesive resin 13 and the rewiring patterns 15 are also subjected to the dicing in portions corresponding to the dicing lines 22. The side faces of the optical semiconductor elements 11 and of the covering layers 12 are formed to be inclined faces. The fact that the side faces of the optical semiconductor elements 11 are inclined faces facilitates the formation of the rewiring patterns 15 on the side face portions of the optical semiconductor elements 11 in the subsequent processes. The dicing may be performed to such an extent that the sheet 22 is partly cut. Even if the coveting layers 12 and the optical semiconductor elements 11 are separated, since the covering layers 12 are adhered to the single sheet 22, there is a merit that the devices do not come apart until the last process.
  • In addition, the back of each of the [0043] optical semiconductor elements 11 is protected by the insulating layer 14. After the insulating layer 14 is formed over all, dicing may be performed for simultaneously with the other members. Alternatively, the insulating layer 14 may be formed after dicing is performed.
  • Next, referring to FIGS. 4A and 4B, the [0044] terminal portions 17 electrically connected with the circuit portions 21 are provided on the back surface of the optical semiconductor elements 11.
  • Referring to FIG. 4A, the [0045] rewiring patterns 15 are allowed to elongate up to the upper faces of the insulating layer 14. The material of the rewiring patterns 15 is Al, Ag, Au, Pt, Pd, conductive paste, or the like, and the rewiring patterns 15 are formed by evaporation, sputtering, deposition such as CVD under low or high vacuum, electroplating, electroless plating, sintering, or the like. Here, the side face portions of the optical semiconductor elements 11 are inclined faces, which facilitates the formation of the rewiring patterns 15 using the above-mentioned method. When the rewiring patterns 15 are formed by sputtering in particular, it is possible to more surely perform the deposition of the material owing to the fact that the side faces of the optical semiconductor elements 11 are inclined faces.
  • Referring to FIG. 4B, the [0046] terminal portions 17 electrically connected with the rewiring patterns 15 are formed. The formation of the terminal portions 17 can be performed, for example, by arraying solder balls using a transfer method.
  • Next, referring to FIGS. 5A to [0047] 5C, the sealing resin 16 is formed so that at least the separating grooves 24 are filled with the sealing resin 16, and then the individual optical semiconductor devices 10 are separated from each other along the separating grooves 24.
  • Referring to FIG. 5A, the sealing [0048] resin 16 is formed so as to fill the separating grooves 24 and cover the terminal portions 17. In this embodiment, the sealing resin 16 is formed so as to cover the entire wafer 20. The formation of the sealing resin 16 can be performed by a sealing or casting method using a mold, vacuum printing, or the like.
  • Referring to FIG. 5B, the [0049] terminal portions 17 are exposed from the sealing resin 16. This process can be performed by grinding the sealing resin 16 by use of a grinding attachment. Accordingly, an upper face of the resultant, which is formed of the sealing resin 16, is formed to be a planer face, making a structure in which the terminal portions 17 are exposed from this face. The bump electrodes 18 made of solder or the like are formed on the exposed terminal portions 17. In addition, the exposed terminal portions 17 may be plated, and ball electrodes may be formed on the exposed terminal portions 17.
  • Finally, referring to FIG. 5C, dicing is performed along the separating [0050] grooves 24, thus separating the optical semiconductor devices from each other. Since only the sealing resin 16 is cut in this dicing, a process can be realized where abrasion on the dicing blade is reduced. Thereafter, a process of testing and the removal of the sheet 22 are performed to complete the optical semiconductor devices 10A, for example, as shown in FIG. 1A.
  • Additionally, when manufacturing the [0051] optical semiconductor devices 10B as shown in FIG. 1B, a process of forming the posts 19 by providing the via holes in the optical semiconductor elements 11 is added instead of the aforementioned process of allowing the rewiring patterns 15 to elongate up to the backs of the optical semiconductor elements 11. The other processes are the same as those which were described above.
  • The above description has been given of the optical semiconductor devices and the manufacturing methods thereof according to the present embodiment. However, various changes may be made without departing from,the spirit of the present embodiment. [0052]
  • For example, referring to FIGS. 6A to [0053] 6D, it is possible to provide the separating grooves 24 to such an extent that the covering layer 12 is not divided in the process of separating the wafer 20. FIG. 6A shows a process of separating the wafer 20 into the optical semiconductor elements 11 by dicing; FIG. 6B shows a process of allowing the rewiring patterns 15 to elongate up to the backs of the optical semiconductor elements 11 and providing the terminal portions 17; FIG. 6C shows a state where, after sealing with resin, the terminal portions 17 are exposed therefrom and the bump electrodes 18 are formed on the terminal portions 17; and FIG. 6D shows a state where the sealing resin 16 and the covering layer 12 are subjected to dicing at the separating grooves 24, thus separating the individual optical semiconductor devices 10 from each other.
  • The prevent embodiment can have beneficial effects as follows. [0054]
  • In the optical semiconductor device of the present embodiment, since the side faces of the [0055] covering layer 12 and of the optical semiconductor element 11 are protected by the sealing resin 16, it is possible to provide the optical semiconductor device 10 of which the moisture resistance, heat resistance, and mechanical strength are improved. Moreover, since part of the rewiring patterns 15 elongating along the side faces of the optical semiconductor element 11 is protected by the sealing resin 16, it is possible to make a structure in which the rewiring patterns 15 are prevented from breaking.
  • In the method of manufacturing the semiconductor device of the present embodiment, since the processes of dicing and like are performed after the [0056] wafer 20 is adhered onto the sheet 22 including the covering layer 12, there is a merit that the optical semiconductor devices 10 do not come apart until the last process. Moreover, since only the sealing resin 16 is subjected to dicing by use of a dicing blade in the last process of dicing to separate the optical semiconductor devices 10 from each other, it is possible to reduce the abrasion on the dicing blade. Furthermore, since the surface of the covering layer 12 is covered with the sheet 22, it is possible to prevent the surface of the covering layer 12 from being damaged. In addition, it is possible to use the single sheet 22 as a protect sheet and as a dicing sheet in common.

Claims (17)

What is clamed is:
1. An optical semiconductor device, comprising:
an optical semiconductor element having a circuit portion including any one of a light-receiving element and a light-emitting element on a surface thereof;
a terminal portion which is provided on a back of the optical semiconductor element and electrically connected with the circuit portion;
a covering layer which covers the surface of the optical semiconductor element and is made of a transparent material; and
sealing resin which covers side surfaces of the optical semiconductor element.
2. The device of claim 1, wherein the back surface of the optical semiconductor element is covered with the sealing resin, and the terminal portion is exposed from the sealing resin.
3. The device of claim 1, wherein the back surface of the optical semiconductor element is covered with an insulating layer, and the terminal portion is formed on a back of the insulating layer.
4. The device of claim 1, wherein the circuit portion of the optical semiconductor element and the terminal portion are electrically connected by a penetrating electrode provided in the optical semiconductor element.
5. The device of claim 1, wherein the circuit portion of the optical semiconductor element and the terminal portion are connected through a rewiring pattern elongating along a side surface portion of the optical semiconductor element, and the rewiring pattern is covered with the sealing resin.
6. The device of claim 1, wherein a bump electrode is formed on a back of the terminal portion.
7. The device of claim 1, wherein each of the side surfaces of the optical semiconductor element is formed to be an inclined surface.
8. The device of claim 1, wherein side surfaces of the covering layer is covered with the sealing resin.
9. A method of manufacturing an optical semiconductor device, comprising:
preparing a wafer having a plurality of circuit portions each including any one of a light-receiving element and a light-emitting element on a surface thereof;
separating the wafer into individual optical semiconductor elements by forming separating grooves from a back surface of the wafer so that the wafer is separated;
providing terminal portions electrically connected with the circuit portions on back surface of the optical semiconductor elements;
forming sealing resin so that at least the separating grooves are filled with the sealing resin; and
separating individual optical semiconductor devices from each other along the separating grooves.
10. The method of claim 9, further comprising the step of adhering a transparent covering layer onto the surface of the wafer so that the circuit portions are covered with the covering layer.
11. The method of claim 10, wherein after the wafer with a covering layer facing down is adhered onto a sheet, the separating grooves are formed.
12. The method of claim 10, wherein the separating grooves are formed so that both the wafer and the covering layer are divided, and side surfaces of the optical semiconductor elements and divided portions of the covering layer are covered with the sealing resin with which the separating grooves are filled.
13. The method of claim 9, wherein the separating grooves are formed so that the covering layer is partly divided, and side surfaces of the optical semiconductor elements and of partly divided portions of the covering layer are covered with the sealing resin with which the separating grooves are filled.
14. The method of claim 9, wherein the circuit portions of the optical semiconductor elements and the terminal portions are electrically connected by penetrating electrodes provided in the optical semiconductor elements.
15. The method of claim 9, wherein the circuit portions of the optical semiconductor elements and the terminal portions are connected through rewiring patterns elongating along side surface portions of the optical semiconductor elements, and the rewiring patterns are covered with the sealing resin.
16. The method of claim 15, wherein the rewiring patterns are formed on the side surface portions, each side surface portion being formed to be an inclined surface.
17. The method of claim 9, wherein the sealing resin is formed to cover the terminal portions and the back of the wafer, and the terminal portions are exposed by abrading the sealing resin.
US10/812,454 2003-06-05 2004-03-30 Optical semiconductor device and method of manufacturing same Abandoned US20040245530A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/537,496 US7728438B2 (en) 2003-06-05 2006-09-29 Optical semiconductor device and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003160893A JP2004363380A (en) 2003-06-05 2003-06-05 Optical semiconductor device and its fabricating process
JP2003-160893 2003-06-05

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/537,496 Division US7728438B2 (en) 2003-06-05 2006-09-29 Optical semiconductor device and method of manufacturing the same

Publications (1)

Publication Number Publication Date
US20040245530A1 true US20040245530A1 (en) 2004-12-09

Family

ID=33487495

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/812,454 Abandoned US20040245530A1 (en) 2003-06-05 2004-03-30 Optical semiconductor device and method of manufacturing same
US11/537,496 Expired - Lifetime US7728438B2 (en) 2003-06-05 2006-09-29 Optical semiconductor device and method of manufacturing the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11/537,496 Expired - Lifetime US7728438B2 (en) 2003-06-05 2006-09-29 Optical semiconductor device and method of manufacturing the same

Country Status (5)

Country Link
US (2) US20040245530A1 (en)
JP (1) JP2004363380A (en)
KR (1) KR100651105B1 (en)
CN (1) CN100397664C (en)
TW (1) TWI235622B (en)

Cited By (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060071152A1 (en) * 2004-10-04 2006-04-06 Sharp Kabushiki Kaisha Semiconductor device and method for producing same
US20070023608A1 (en) * 2005-07-15 2007-02-01 Altus Technology Inc. Image sensor chip package
US20070279504A1 (en) * 2006-05-16 2007-12-06 Nec Electronics Corporation Solid-state image sensing device
US20090096071A1 (en) * 2007-10-16 2009-04-16 Samsung Electronics Co., Ltd. Semiconductor package and electronic device having the same
EP2075840A2 (en) 2007-12-28 2009-07-01 Semiconductor Energy Laboratory Co., Ltd. Protection layer for wafer dicing and corresponding
US20090183766A1 (en) * 2008-01-22 2009-07-23 Hidekazu Takahashi Semiconductor device and method of manufacturing semiconductor device
US20090194154A1 (en) * 2008-02-01 2009-08-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
DE102008035255A1 (en) * 2008-07-29 2010-03-11 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor component
US20100167451A1 (en) * 2007-04-05 2010-07-01 Micron Technology, Inc. Methods of manufacturing imaging device packages
US20100197077A1 (en) * 2007-07-27 2010-08-05 Hynix Semiconductor Inc. Semiconductor package adapted for high-speed data processing and damage prevention of chips packaged therein and method for fabricating the same
DE102010011400A1 (en) * 2010-03-15 2011-09-15 Ses Services Gmbh LED component, has plastic secondary optical part comprising surface treatment in region of reflection surfaces lying outside such that photometric properties of component remains same during partial-or complete sealing of optical part
US20110220910A1 (en) * 2010-03-09 2011-09-15 Kabushiki Kaisha Toshiba Semiconductor light emitting device and method for manufacturing same
DE102010012039A1 (en) * 2010-03-19 2011-09-22 Osram Opto Semiconductors Gmbh Optoelectronic component and method for its production
DE102010013317A1 (en) * 2010-03-30 2011-10-06 Osram Opto Semiconductors Gmbh Optoelectronic component, housing for this and method for producing the optoelectronic component
US8102039B2 (en) 2006-08-11 2012-01-24 Sanyo Semiconductor Co., Ltd. Semiconductor device and manufacturing method thereof
CN101859847B (en) * 2009-04-13 2012-03-07 奇力光电科技股份有限公司 Light-emitting diode (LED) and manufacturing method thereof
US8232564B2 (en) 2007-01-22 2012-07-31 Cree, Inc. Wafer level phosphor coating technique for warm light emitting diodes
US8552517B1 (en) * 2010-09-14 2013-10-08 Amkor Technology, Inc. Conductive paste and mold for electrical connection of photovoltaic die to substrate
US8556672B2 (en) 2010-01-29 2013-10-15 Citizen Electronics Co., Ltd. Method of producing light-emitting device and light-emitting device
US8686526B2 (en) 2006-11-20 2014-04-01 Semiconductor Components Industries, Llc Semiconductor device and method of manufacturing the same
US8766408B2 (en) 2006-03-07 2014-07-01 Semiconductor Components Industries, Llc Semiconductor device and manufacturing method thereof
US8878219B2 (en) 2008-01-11 2014-11-04 Cree, Inc. Flip-chip phosphor coating method and devices fabricated utilizing method
US9024349B2 (en) * 2007-01-22 2015-05-05 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US9041285B2 (en) 2007-12-14 2015-05-26 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US9093616B2 (en) 2003-09-18 2015-07-28 Cree, Inc. Molded chip fabrication method and apparatus
US9159888B2 (en) 2007-01-22 2015-10-13 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US9166126B2 (en) 2011-01-31 2015-10-20 Cree, Inc. Conformally coated light emitting devices and methods for providing the same
US9196799B2 (en) 2007-01-22 2015-11-24 Cree, Inc. LED chips having fluorescent substrates with microholes and methods for fabricating
US20160197229A1 (en) * 2015-01-05 2016-07-07 Il Woo Park Semiconductor light emitting device package and method for manufacturing the same
US20180033923A1 (en) * 2013-07-08 2018-02-01 Lumileds Llc. Wavelength converted semiconductor light emitting device
CN108321215A (en) * 2018-03-07 2018-07-24 苏州晶方半导体科技股份有限公司 The encapsulating structure and preparation method thereof of optical finger print identification chip
US10381524B2 (en) 2012-04-18 2019-08-13 Nichia Corporation Semiconductor light emitting element including protective film and light shielding member
US10546846B2 (en) 2010-07-23 2020-01-28 Cree, Inc. Light transmission control for masking appearance of solid state light sources
US10665747B2 (en) 2009-08-07 2020-05-26 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor component
US10672724B2 (en) * 2016-03-31 2020-06-02 Sony Corporation Semiconductor device, manufacturing method of semiconductor device, integrated substrate, and electronic device
DE102008064956B3 (en) 2008-07-29 2023-08-24 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung OPTOELECTRONIC SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING AN OPTOELECTRONIC SEMICONDUCTOR DEVICE
US11876107B2 (en) 2018-11-20 2024-01-16 Olympus Corporation Image pickup apparatus for endoscope and endoscope

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9000461B2 (en) * 2003-07-04 2015-04-07 Epistar Corporation Optoelectronic element and manufacturing method thereof
US7419853B2 (en) * 2005-08-11 2008-09-02 Hymite A/S Method of fabrication for chip scale package for a micro component
US8063495B2 (en) * 2005-10-03 2011-11-22 Rohm Co., Ltd. Semiconductor device
KR100820913B1 (en) * 2006-08-18 2008-04-10 최현규 Semiconductor package, method of fabricating the same and semiconductor package module for image sensor
JP4951989B2 (en) 2006-02-09 2012-06-13 富士通セミコンダクター株式会社 Semiconductor device
JP5486759B2 (en) * 2006-04-14 2014-05-07 日亜化学工業株式会社 Manufacturing method of semiconductor light emitting device
JP4958273B2 (en) * 2007-01-23 2012-06-20 オンセミコンダクター・トレーディング・リミテッド Light emitting device and manufacturing method thereof
US8167674B2 (en) * 2007-12-14 2012-05-01 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US8138027B2 (en) 2008-03-07 2012-03-20 Stats Chippac, Ltd. Optical semiconductor device having pre-molded leadframe with window and method therefor
JP2010073841A (en) * 2008-09-18 2010-04-02 Sony Corp Optical package element, display device, and electronic apparatus
JP5324890B2 (en) 2008-11-11 2013-10-23 ラピスセミコンダクタ株式会社 Camera module and manufacturing method thereof
US8563963B2 (en) * 2009-02-06 2013-10-22 Evergrand Holdings Limited Light-emitting diode die packages and methods for producing same
JP5318634B2 (en) * 2009-03-30 2013-10-16 ラピスセミコンダクタ株式会社 Chip size packaged semiconductor chip and manufacturing method
JP5475363B2 (en) * 2009-08-07 2014-04-16 ラピスセミコンダクタ株式会社 Semiconductor device and manufacturing method thereof
KR101037369B1 (en) * 2009-08-19 2011-05-26 이익주 A method for manufacturing a LED chip
JP5101645B2 (en) * 2010-02-24 2012-12-19 株式会社東芝 Semiconductor light emitting device
US9039216B2 (en) 2010-04-01 2015-05-26 Lg Innotek Co., Ltd. Light emitting device package and light unit having the same
JP4875185B2 (en) * 2010-06-07 2012-02-15 株式会社東芝 Optical semiconductor device
TWI659648B (en) * 2013-03-25 2019-05-11 新力股份有限公司 Solid-state imaging device and camera module, and electronic device
JP6361374B2 (en) * 2014-08-25 2018-07-25 日亜化学工業株式会社 Light emitting device and manufacturing method thereof
JP5997327B2 (en) * 2015-07-23 2016-09-28 京セラ株式会社 Elastic wave device and circuit board
JP6500885B2 (en) * 2016-12-20 2019-04-17 日亜化学工業株式会社 Method of manufacturing light emitting device
JP2018129341A (en) * 2017-02-06 2018-08-16 株式会社ディスコ Method for manufacturing light-emitting diode chip and light-emitting diode chip
JP2018129343A (en) * 2017-02-06 2018-08-16 株式会社ディスコ Method for manufacturing light-emitting diode chip and light-emitting diode chip
JP2018129370A (en) * 2017-02-07 2018-08-16 株式会社ディスコ Method for manufacturing light-emitting diode chip and light-emitting diode chip
JP2018186168A (en) * 2017-04-25 2018-11-22 株式会社ディスコ Method for manufacturing light-emitting diode chip and light-emitting diode chip
JP2018186169A (en) * 2017-04-25 2018-11-22 株式会社ディスコ Method for manufacturing light-emitting diode chip and light-emitting diode chip
JP6609674B1 (en) * 2018-07-11 2019-11-20 浜松ホトニクス株式会社 Photodetection device and method for manufacturing photodetection device
KR20220031161A (en) 2020-09-04 2022-03-11 삼성전자주식회사 Semiconductor package
JP7404205B2 (en) 2020-09-18 2023-12-25 株式会社東芝 Semiconductor devices and systems including them
WO2022203690A1 (en) * 2021-03-26 2022-09-29 Hrl Laboratories, Llc Hybrid integrated circuit architecture

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020063218A1 (en) * 2000-11-30 2002-05-30 Ge Medical Systems Global Technology Company, Llc Protective cover and attachment method for moisture sensitive devices
US20020081838A1 (en) * 1999-06-28 2002-06-27 Bohr Mark T. Interposer and method of making same
US20030099737A1 (en) * 1999-07-30 2003-05-29 Formfactor, Inc. Forming tool for forming a contoured microelectronic spring mold
US6777767B2 (en) * 1999-12-10 2004-08-17 Shellcase Ltd. Methods for producing packaged integrated circuit devices & packaged integrated circuit devices produced thereby
US6833668B1 (en) * 1999-09-29 2004-12-21 Sanyo Electric Co., Ltd. Electroluminescence display device having a desiccant

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2626408B1 (en) * 1988-01-22 1990-05-11 Thomson Csf LOW-SIZE IMAGE SENSOR
US5324888A (en) * 1992-10-13 1994-06-28 Olin Corporation Metal electronic package with reduced seal width
JPH0823085A (en) * 1994-07-08 1996-01-23 Matsushita Electron Corp Solid state image pickup device
US5814889A (en) * 1995-06-05 1998-09-29 Harris Corporation Intergrated circuit with coaxial isolation and method
WO1997010672A1 (en) * 1995-09-11 1997-03-20 Gatan, Inc. Optically coupled large-format solid state imaging device
JP2000173766A (en) * 1998-09-30 2000-06-23 Sanyo Electric Co Ltd Display device
JP4809957B2 (en) * 1999-02-24 2011-11-09 日本テキサス・インスツルメンツ株式会社 Manufacturing method of semiconductor device
JP4234269B2 (en) * 1999-07-16 2009-03-04 浜松ホトニクス株式会社 Semiconductor device and manufacturing method thereof
JP2001339151A (en) 2000-05-26 2001-12-07 Nec Corp Method for mounting electronic component with bumps
US6503780B1 (en) * 2000-07-05 2003-01-07 Amkor Technology, Inc. Wafer scale image sensor package fabrication method
MY131962A (en) * 2001-01-24 2007-09-28 Nichia Corp Light emitting diode, optical semiconductor device, epoxy resin composition suited for optical semiconductor device, and method for manufacturing the same
JP2003124392A (en) * 2001-10-15 2003-04-25 Sony Corp Semiconductor device and manufacturing method therefor
JP2003158301A (en) * 2001-11-22 2003-05-30 Citizen Electronics Co Ltd Light emitting diode

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020081838A1 (en) * 1999-06-28 2002-06-27 Bohr Mark T. Interposer and method of making same
US6671947B2 (en) * 1999-06-28 2004-01-06 Intel Corporation Method of making an interposer
US20030099737A1 (en) * 1999-07-30 2003-05-29 Formfactor, Inc. Forming tool for forming a contoured microelectronic spring mold
US6833668B1 (en) * 1999-09-29 2004-12-21 Sanyo Electric Co., Ltd. Electroluminescence display device having a desiccant
US6777767B2 (en) * 1999-12-10 2004-08-17 Shellcase Ltd. Methods for producing packaged integrated circuit devices & packaged integrated circuit devices produced thereby
US20020063218A1 (en) * 2000-11-30 2002-05-30 Ge Medical Systems Global Technology Company, Llc Protective cover and attachment method for moisture sensitive devices

Cited By (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9105817B2 (en) 2003-09-18 2015-08-11 Cree, Inc. Molded chip fabrication method and apparatus
US10164158B2 (en) 2003-09-18 2018-12-25 Cree, Inc. Molded chip fabrication method and apparatus
US10546978B2 (en) 2003-09-18 2020-01-28 Cree, Inc. Molded chip fabrication method and apparatus
US9093616B2 (en) 2003-09-18 2015-07-28 Cree, Inc. Molded chip fabrication method and apparatus
US20060071152A1 (en) * 2004-10-04 2006-04-06 Sharp Kabushiki Kaisha Semiconductor device and method for producing same
US20070023608A1 (en) * 2005-07-15 2007-02-01 Altus Technology Inc. Image sensor chip package
US7554184B2 (en) * 2005-07-15 2009-06-30 Altus Technology Inc. Image sensor chip package
US8766408B2 (en) 2006-03-07 2014-07-01 Semiconductor Components Industries, Llc Semiconductor device and manufacturing method thereof
US20070279504A1 (en) * 2006-05-16 2007-12-06 Nec Electronics Corporation Solid-state image sensing device
US8508007B2 (en) 2006-05-16 2013-08-13 Renesas Electronics Corporation Solid-state image sensing device
US8102039B2 (en) 2006-08-11 2012-01-24 Sanyo Semiconductor Co., Ltd. Semiconductor device and manufacturing method thereof
US8686526B2 (en) 2006-11-20 2014-04-01 Semiconductor Components Industries, Llc Semiconductor device and method of manufacturing the same
US9024349B2 (en) * 2007-01-22 2015-05-05 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US9159888B2 (en) 2007-01-22 2015-10-13 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US8232564B2 (en) 2007-01-22 2012-07-31 Cree, Inc. Wafer level phosphor coating technique for warm light emitting diodes
US9196799B2 (en) 2007-01-22 2015-11-24 Cree, Inc. LED chips having fluorescent substrates with microholes and methods for fabricating
US8012776B2 (en) * 2007-04-05 2011-09-06 Micron Technology, Inc. Methods of manufacturing imaging device packages
US20100167451A1 (en) * 2007-04-05 2010-07-01 Micron Technology, Inc. Methods of manufacturing imaging device packages
US20100197077A1 (en) * 2007-07-27 2010-08-05 Hynix Semiconductor Inc. Semiconductor package adapted for high-speed data processing and damage prevention of chips packaged therein and method for fabricating the same
US8222083B2 (en) * 2007-07-27 2012-07-17 Hynix Semiconductor Inc. Semiconductor package adapted for high-speed data processing and damage prevention of chips packaged therein and method for fabricating the same
US20090096071A1 (en) * 2007-10-16 2009-04-16 Samsung Electronics Co., Ltd. Semiconductor package and electronic device having the same
US8344497B2 (en) 2007-10-16 2013-01-01 Samsung Electronics Co., Ltd. Semiconductor package and electronic device having the same
US9041285B2 (en) 2007-12-14 2015-05-26 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
EP2075840A2 (en) 2007-12-28 2009-07-01 Semiconductor Energy Laboratory Co., Ltd. Protection layer for wafer dicing and corresponding
US20090174023A1 (en) * 2007-12-28 2009-07-09 Hidekazu Takahashi Semiconductor device and method of manufacturing semiconductor device
EP2075840A3 (en) * 2007-12-28 2011-03-09 Semiconductor Energy Laboratory Co., Ltd. Protection layer for wafer dicing and corresponding
US8999818B2 (en) 2007-12-28 2015-04-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
US8878219B2 (en) 2008-01-11 2014-11-04 Cree, Inc. Flip-chip phosphor coating method and devices fabricated utilizing method
US8324079B2 (en) 2008-01-22 2012-12-04 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
US20090183766A1 (en) * 2008-01-22 2009-07-23 Hidekazu Takahashi Semiconductor device and method of manufacturing semiconductor device
US8610152B2 (en) 2008-01-22 2013-12-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
US8227886B2 (en) 2008-02-01 2012-07-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
US20090194154A1 (en) * 2008-02-01 2009-08-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
DE102008064956B3 (en) 2008-07-29 2023-08-24 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung OPTOELECTRONIC SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING AN OPTOELECTRONIC SEMICONDUCTOR DEVICE
US10580941B2 (en) 2008-07-29 2020-03-03 Osram Oled Gmbh Optoelectronic semiconductor component
US9831394B2 (en) 2008-07-29 2017-11-28 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor component
DE102008035255A1 (en) * 2008-07-29 2010-03-11 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor component
US9099622B2 (en) 2008-07-29 2015-08-04 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor component
CN101859847B (en) * 2009-04-13 2012-03-07 奇力光电科技股份有限公司 Light-emitting diode (LED) and manufacturing method thereof
US11239386B2 (en) 2009-08-07 2022-02-01 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor component
US11749776B2 (en) 2009-08-07 2023-09-05 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor component
US12002901B2 (en) 2009-08-07 2024-06-04 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor component
US10665747B2 (en) 2009-08-07 2020-05-26 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor component
US8556672B2 (en) 2010-01-29 2013-10-15 Citizen Electronics Co., Ltd. Method of producing light-emitting device and light-emitting device
US20110220910A1 (en) * 2010-03-09 2011-09-15 Kabushiki Kaisha Toshiba Semiconductor light emitting device and method for manufacturing same
US8729564B2 (en) 2010-03-09 2014-05-20 Kabushiki Kaisha Toshiba Semiconductor light emitting device and method for manufacturing same
US8445916B2 (en) 2010-03-09 2013-05-21 Kabushiki Kaisha Toshiba Semiconductor light emitting device and method for manufacturing same
DE102010011400A1 (en) * 2010-03-15 2011-09-15 Ses Services Gmbh LED component, has plastic secondary optical part comprising surface treatment in region of reflection surfaces lying outside such that photometric properties of component remains same during partial-or complete sealing of optical part
DE102010012039A1 (en) * 2010-03-19 2011-09-22 Osram Opto Semiconductors Gmbh Optoelectronic component and method for its production
DE102010013317A1 (en) * 2010-03-30 2011-10-06 Osram Opto Semiconductors Gmbh Optoelectronic component, housing for this and method for producing the optoelectronic component
DE102010013317B4 (en) 2010-03-30 2021-07-22 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Optoelectronic component, housing therefor and method for producing the optoelectronic component
US10546846B2 (en) 2010-07-23 2020-01-28 Cree, Inc. Light transmission control for masking appearance of solid state light sources
US8552517B1 (en) * 2010-09-14 2013-10-08 Amkor Technology, Inc. Conductive paste and mold for electrical connection of photovoltaic die to substrate
US9166126B2 (en) 2011-01-31 2015-10-20 Cree, Inc. Conformally coated light emitting devices and methods for providing the same
US10381524B2 (en) 2012-04-18 2019-08-13 Nichia Corporation Semiconductor light emitting element including protective film and light shielding member
US20180033923A1 (en) * 2013-07-08 2018-02-01 Lumileds Llc. Wavelength converted semiconductor light emitting device
US10790417B2 (en) 2013-07-08 2020-09-29 Lumileds Llc Wavelength converted semiconductor light emitting device
US10270013B2 (en) * 2013-07-08 2019-04-23 Lumileds Llc Wavelength converted semiconductor light emitting device
US9735313B2 (en) * 2015-01-05 2017-08-15 Samsung Electronics Co., Ltd. Semiconductor light emitting device package and method for manufacturing the same
US20160197229A1 (en) * 2015-01-05 2016-07-07 Il Woo Park Semiconductor light emitting device package and method for manufacturing the same
US10170663B2 (en) 2015-01-05 2019-01-01 Samsung Electronics Co., Ltd. Semiconductor light emitting device package and method for manufacturing the same
US10672724B2 (en) * 2016-03-31 2020-06-02 Sony Corporation Semiconductor device, manufacturing method of semiconductor device, integrated substrate, and electronic device
US11004806B2 (en) 2016-03-31 2021-05-11 Sony Corporation Semiconductor device, manufacturing method of semiconductor device, integrated substrate, and electronic device
CN108321215A (en) * 2018-03-07 2018-07-24 苏州晶方半导体科技股份有限公司 The encapsulating structure and preparation method thereof of optical finger print identification chip
US11876107B2 (en) 2018-11-20 2024-01-16 Olympus Corporation Image pickup apparatus for endoscope and endoscope

Also Published As

Publication number Publication date
JP2004363380A (en) 2004-12-24
CN100397664C (en) 2008-06-25
TWI235622B (en) 2005-07-01
KR20040105560A (en) 2004-12-16
KR100651105B1 (en) 2006-11-29
CN1574403A (en) 2005-02-02
US20070034995A1 (en) 2007-02-15
US7728438B2 (en) 2010-06-01
TW200428914A (en) 2004-12-16

Similar Documents

Publication Publication Date Title
US7728438B2 (en) Optical semiconductor device and method of manufacturing the same
KR100755165B1 (en) Semiconductor device, module for optical devices, and manufacturing method of semiconductor device
US7312521B2 (en) Semiconductor device with holding member
US6989294B1 (en) Leadless plastic chip carrier with etch back pad singulation
US7663231B2 (en) Image sensor module with a three-dimensional die-stacking structure
US7378645B2 (en) Optical sensor module with semiconductor device for drive
US7112457B2 (en) Method of manufacturing an opto-coupler
US7944015B2 (en) Semiconductor device and method of manufacturing the same
US6917090B2 (en) Chip scale image sensor package
KR100840501B1 (en) Semiconductor device and manufacturing method thereof, and camera module
US7525167B2 (en) Semiconductor device with simplified constitution
US20190096866A1 (en) Semiconductor package and manufacturing method thereof
TW201143044A (en) Wafer level compliant packages for rear-face illuminated solid state image sensors
US20090059055A1 (en) Optical device and method for fabricating the same
KR20080074773A (en) Image sensor package with die receiving opening and method of the same
US20100231766A1 (en) Imaging device
US11282879B2 (en) Image sensor packaging method, image sensor packaging structure, and lens module
JP2006191126A (en) Method for manufacturing semiconductor device
US20110083322A1 (en) Optical device and method for manufacturing the same
CN101393877A (en) Method of manufacturing a semiconductor device
US20090014827A1 (en) Image sensor module at wafer level, method of manufacturing the same, and camera module
US9219091B2 (en) Low profile sensor module and method of making same
CN116613267A (en) Fan-out packaging structure of miniature LED light-emitting device and preparation method
US9508684B2 (en) Resin-encapsulated semiconductor device and method of manufacturing the same
US20040263667A1 (en) Solid-state imaging apparatus and method for making the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: KANTO SANYO SEMICONDUCTORS CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KAMEYAMA, KOUJIRO;MITA, KIYOSHI;REEL/FRAME:014814/0074;SIGNING DATES FROM 20040413 TO 20040414

Owner name: SANYO ELECTRIC CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KAMEYAMA, KOUJIRO;MITA, KIYOSHI;REEL/FRAME:014814/0074;SIGNING DATES FROM 20040413 TO 20040414

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION