US20030146480A1 - Metal-gate field effect transistor and method for manufacturing the same - Google Patents
Metal-gate field effect transistor and method for manufacturing the same Download PDFInfo
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- US20030146480A1 US20030146480A1 US10/360,653 US36065303A US2003146480A1 US 20030146480 A1 US20030146480 A1 US 20030146480A1 US 36065303 A US36065303 A US 36065303A US 2003146480 A1 US2003146480 A1 US 2003146480A1
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- 230000005669 field effect Effects 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims description 23
- 238000009413 insulation Methods 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 239000004065 semiconductor Substances 0.000 claims abstract description 45
- 229910052751 metal Inorganic materials 0.000 claims abstract description 43
- 239000002184 metal Substances 0.000 claims abstract description 43
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 35
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000010941 cobalt Substances 0.000 claims abstract description 11
- 229910017052 cobalt Inorganic materials 0.000 claims abstract description 11
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims description 23
- 238000007254 oxidation reaction Methods 0.000 claims description 23
- 238000007789 sealing Methods 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 8
- 239000007769 metal material Substances 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 10
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
Definitions
- the present invention relates to a metal-gate field effect transistor having a low resistance source-drain region and a method for manufacturing the same.
- FIG. 1 is a sectional view showing this conventional metal-gate field effect transistor.
- FIGS. 2A through 2E are sectional views showing a method for manufacturing the metal-gate field effect transistor in the order of the steps thereof.
- a dummy gate electrode 2 is formed by the use of some material. Then, a low concentration source-drain region 5 is formed by means of ion implantation on the surface of the semiconductor substrate 1 by using this dummy gate electrode 2 as a mask. After that, a side wall insulation film 3 is formed on a side wall of the gate electrode 2 , and a high concentration source-drain region 4 is formed by means of ion implantation on the surface of the semiconductor substrate 1 by using as a mask this side wall insulation film 3 . Incidentally, the gate electrode 2 and the side wall insulation film 3 are embedded in an insulation film 7 , and the surface of the gate electrode 2 and the side wall insulation film 3 are made planar.
- the surface of the semiconductor substrate of the gate portion is subjected to oxidation thereby forming a gate insulation film 8 .
- a metal film is formed on the whole surface of the semiconductor substrate 1 to embed the gate portion with this metal film followed by patterning this metal film with a photo-resist 10 thereby forming a metal-gate electrode 9 which is embedded in the gate portion.
- a metal-gate MISFET having a structure shown in FIG. 1 is formed by removing the photo-resist 10 .
- the MISFET structure is formed in advance by using some material as the gate electrode 2 in order to form in self-alignment the gate electrode and the source-drain region.
- the gate oxidation is performed, and the metal is embedded therein to form a real metal-gate electrode 9 .
- this conventional metal-gate MISFET has a problem that a parasitic resistance of the source-drain region is large.
- the metal-made gate electrode when the metal-made gate electrode is formed followed by implanting ions to form the source-drain region by using the metal-made gate electrode as a mask for self-alignment, it is required to regulate a temperature for activating implanted ions to at most 800° C. or so in order to avoid the melting of the metal.
- the activation of the implanted ions becomes insufficient at such a temperature of heat treatment.
- the presence of the silicide film on the source-drain region at the time of the gate oxidation leads to the deterioration of the electric characteristics owing to the oxidation of the silicide film. For such a reason, the silicide film could not be formed on the source-drain region of the conventional metal-gate MISFET.
- An object of the present invention is to provide a metal-gate field effect transistor having a low parasitic resistance of the source and drain and a method for manufacturing the same.
- a metal-gate field effect transistor comprises a metal-gate electrode formed on a semiconductor substrate, and a source-drain region formed on the surface of the semiconductor substrate on both sides of the metal-gate electrode, the transistor being characterized in that a cobalt silicide film is formed on the source-drain region.
- a metal-gate field effect transistor comprises a metal-gate electrode formed on a semiconductor substrate, and a source-drain region formed on the surface of the semiconductor substrate on both sides of the metal-gate electrode, the transistor being characterized in that a conductive film formed of the same material as the metal-gate electrode is formed on the source-drain region.
- a method for forming the metal-gate field effect transistor according to the first aspect of the present invention comprises the steps of:
- sealing film such as silicon nitride or the like on the silicide film
- a method for manufacturing the metal-gate field effect transistor according to the second aspect of the present invention comprises the steps of:
- a method for manufacturing the metal-gate field effect transistor according to a third aspect of the present invention comprises the steps of:
- the silicide film since an upper portion of the silicide film is sealed with the sealing film such as silicon nitride or the like, the silicide film is not exposed to an atmosphere of the oxidation even when the silicide film is exposed to a high temperature with the result that the deterioration of the silicide film can be prevented.
- the sealing film such as silicon nitride or the like
- the silicide film is present on the source-drain region, the parasitic resistance of the source-drain region can be reduced.
- FIG. 1 is a sectional view showing a conventional metal gate MISFET
- FIGS. 2A through 2E are sectional views showing a method for manufacturing this conventional metal gate MISFET in the order of the steps thereof;
- FIG. 3 is a sectional view showing a metal gate MISFET according to a first embodiment of the present invention
- FIGS. 4A through 4E are sectional views showing a method for manufacturing the metal gate MISFET according to the first embodiment of the present invention in the order of the steps thereof;
- FIG. 5 is a sectional view showing the metal gate MISFET according to a second embodiment of the present invention.
- FIGS. 6A through 6E are sectional views showing the method for manufacturing the metal gate MISFET according to the second embodiment of the present invention in the order of the steps thereof.
- FIGS. 7A through 7G are sectional views showing a method for manufacturing the metal gate MISFET according to a third embodiment of the present invention in the order of the steps thereof.
- FIG. 3 is a sectional view showing a metal gate MISFET according to an embodiment of the present invention.
- FIGS. 4A through 4E are sectional views showing a method for manufacturing this metal gate MISFET in the order of the steps thereof.
- a metal-gate electrode 12 formed of a metal material such as tungsten W or the like is formed via a gate insulation film 15 on a semiconductor substrate 11 .
- a side wall insulation film 13 is formed on both sides of this metal gate electrode 12 .
- a low concentration source-drain region 17 is formed below the side wall insulation film 13 .
- a high concentration source-drain region 16 is formed outside of the low concentration source-drain region 17 . Then, in this embodiment, the surface of the source-drain region which surface is not covered with the side wall insulation film 13 is covered with a silicide film 18 .
- This silicide film 18 is, for example, a cobalt silicide film.
- a method for manufacturing the metal gate MISFET having the above structure will be explained.
- a dummy gate insulation film 21 is formed on the surface of the semiconductor substrate 11 .
- a dummy gate electrode 20 formed of polysilicon or the like is selectively formed, and the side wall insulation film 13 is formed on the side wall of the dummy gate electrode 20 .
- This side wall insulation film 13 can be formed of silicon nitride or the like.
- a MISFET structure by means of the dummy gate electrode is formed.
- the cobalt silicide film 18 having, for example, a thickness of 39 nm is formed.
- the whole surface of the cobalt silicide film 18 is covered with a silicon nitride film 19 having, for example, a thickness of 100 nm.
- a thick insulation film 22 is formed thereon.
- the insulation film 22 and the silicon nitride film 19 on the dummy gate electrode 20 are selectively removed with the chemical and mechanical polishing method (CMP) to make planar the surface thereof. As a consequence, the surface of the dummy gate electrode 20 is exposed.
- CMP chemical and mechanical polishing method
- a silicon oxide film is generally used as the thick insulation film 22 which is used at this step.
- the dummy gate electrode 20 is removed. Then, on the surface of the semiconductor substrate 11 of this gate portion, ion implantation 23 is performed for determining a punch-through stopper and a threshold value Vt.
- ion seeds for determining this threshold value Vt boron is generally used in the case of nMOSFET, and phosphorus is generally used in the case of pMOSFET.
- boron is generally used in the case of nMOSFET
- phosphorus is generally used in the case of pMOSFET.
- the present embodiment is not limited to the above kind of ions.
- the gate insulation film (oxide film) 15 is formed on the surface of the semiconductor substrate of the gate portion by subjecting to oxidation the surface of the semiconductor substrate in the oxidation atmosphere at a temperature of, for example, 700° C.
- a metal film such as tungsten W or the like is formed on the whole surface of the semiconductor substrate 11 , a metal film is embedded in the gate portion, and the metal film is polished with the chemical and mechanical polishing method (CMP) thereby exposing the surface of the metal gate electrode 12 and completing the metal gate MISFET.
- CMP chemical and mechanical polishing method
- the cobalt silicide film 18 is sealed with the silicon nitride film 19 so that the cobalt silicide film 18 is not exposed to the oxidation atmosphere and the characteristics thereof is not deteriorated.
- the cobalt silicide film 18 is only covered with the insulation film 22 , and a silicon oxide film is normally used in this insulation film 22 as described above. Since this silicon oxide allows the passage of the oxidation seeds, the oxidation of the silicide film 18 cannot be prevented.
- the silicon nitride film 19 in the present embodiment does not allow the passage of the oxidation seeds, the oxidation of the silicide film 18 can be prevented.
- FIG. 5 is a sectional view showing a metal-gate field effect transistor according to the second embodiment of the present invention.
- FIGS. 6A through 6F are sectional views showing the method for manufacturing the metal-gate field effect transistor according to the second embodiment in the order of the steps.
- a metal gate electrode 32 is formed via a gate insulation film 39 .
- a side wall insulation film 33 is formed on the side wall of the channel region. Outside of each of the side wall insulation films 33 , a conductive film 37 is formed via an insulation film 36 .
- This conductive film 37 is formed of the same metal material as the metal gate electrode 32 .
- the silicide film is not present on the source-drain regions 34 and 35 .
- the conductive film 37 is present thereon with the result that the parasitic resistance of the source-drain regions 34 and 35 is reduced.
- ion implantation 40 is performed to form an implantation layer, and the gate oxidation is performed with the result that a gate insulation film (oxide film) 39 is formed.
- a titanium nitride film 43 is deposited to open a region including at least portion of an area on the source-drain region 34 .
- a barrier metal film 44 is deposited.
- This barrier metal film 44 comprises, for example, a laminated body of a titanium nitride film and a titanium film located below the titanium nitride film.
- the titanium nitride film is generally used as a barrier film.
- this titanium nitride film has a poor adhesiveness with the insulation film or the like, the titanium film is used as a close contact layer.
- the barrier metal film 44 may be used as a single layer.
- the metal gate electrode 32 and the conductive film 37 are formed by simultaneously embedding the gate electrode region and the opening on the source-drain region with a metal such as tungsten or the like by means of, for example, the CVD or the like, thereby completing the metal gate MISFET.
- the conductive film 37 formed of the same metal material as the gate electrode is formed on the source-drain region at the same step as the gate electrode, the parasitic resistance of the source-drain region can be reduced, and the step thereof is simple, at the same time.
- FIGS. 7A through 7G are sectional views showing the method for manufacturing the metal-gate field effect transistor according to the third embodiment of the present invention in the order of steps.
- the third embodiment is such that an opening on the source-drain region is formed in self-alignment with respect to a gate electrode.
- a dummy gate electrode 62 and a dummy gate insulation film 68 are formed on a semiconductor substrate 60 , and a side wall insulation film 61 is formed on the side walls of the dummy gate electrode 62 with silicon nitride, and a silicon nitride cap portion 63 is formed on the dummy gate electrode 62 . Furthermore, the source-drain region 64 is formed on the surface of the semiconductor substrate, and an SiO 2 film 65 is formed on a region other than the gate portion on the semiconductor substrate.
- the Si 0 2 film 65 on the source-drain region 64 is etched and removed by using as a mask the silicon nitride side wall insulation film 61 , and the silicon nitride cap portion 63 on the dummy gate electrode 62 .
- an opening on the source-drain region 64 is opened in self-alignment with respect to the gate electrode 63 .
- a barrier metal film 72 such as titanium nitride film or the like is formed with respect to the opening on the source-drain region in the beginning. Then, the opening is embedded with a conductive film 66 such as tungsten W or the like. After that, as shown in FIG. 7D, a sealing portion 67 of the silicon nitride sealing portion 67 is formed on the surface of the conductive film 66 .
- a metal such as tungsten W or the like is embedded in the gate portion, and a metal gate electrode 70 is formed.
- a metal gage MISFET is completed.
- the conductive film 66 is formed on the source-drain region 64 , the parasitic resistance of the source-drain region 64 can be reduced.
Abstract
A metal gate MISFET comprises a metal gate electrode on a semiconductor substrate, a side wall insulation film, and a source-drain region which is formed on the surface of the semiconductor substrate on both sides of the side wall insulation film. Then, a cobalt silicide film is formed on the source-drain region. In this step of manufacturing the MISFET, since the cobalt silicide film is sealed with the silicon nitride film at the time of oxidizing the surface of the substrate of a gate portion, the property of the cobalt silicide film will never be deteriorated. As a consequence, the metal-gate field effect transistor having a low parasitic resistance of the source-drain region can be obtained.
Description
- 1. Field of the Invention
- The present invention relates to a metal-gate field effect transistor having a low resistance source-drain region and a method for manufacturing the same.
- 2. Description of the Related Art
- A structure of this kind of metal-gate MISFET and a method for manufacturing such a metal-gate MISFET are disclosed in pp. 821-824 of IEDM Tech. Dig., 1997. FIG. 1 is a sectional view showing this conventional metal-gate field effect transistor. FIGS. 2A through 2E are sectional views showing a method for manufacturing the metal-gate field effect transistor in the order of the steps thereof.
- As shown in FIG. 2A, after a dummy
gate insulation film 6 is formed on asemiconductor substrate 1, a dummy gate electrode 2 is formed by the use of some material. Then, a low concentration source-drain region 5 is formed by means of ion implantation on the surface of thesemiconductor substrate 1 by using this dummy gate electrode 2 as a mask. After that, a sidewall insulation film 3 is formed on a side wall of the gate electrode 2, and a high concentration source-drain region 4 is formed by means of ion implantation on the surface of thesemiconductor substrate 1 by using as a mask this sidewall insulation film 3. Incidentally, the gate electrode 2 and the sidewall insulation film 3 are embedded in aninsulation film 7, and the surface of the gate electrode 2 and the sidewall insulation film 3 are made planar. - Subsequently, as shown in FIG. 2B, the dummy gate electrode2 is removed.
- Then, as shown in FIG. 2C, the
gate insulation film 6 located below the gate electrode is removed. - Furthermore, as shown in FIG. 2D, the surface of the semiconductor substrate of the gate portion is subjected to oxidation thereby forming a
gate insulation film 8. - After that, as shown in FIG. 2E, a metal film is formed on the whole surface of the
semiconductor substrate 1 to embed the gate portion with this metal film followed by patterning this metal film with a photo-resist 10 thereby forming ametal-gate electrode 9 which is embedded in the gate portion. - Then, a metal-gate MISFET having a structure shown in FIG. 1 is formed by removing the photo-
resist 10. - In this manner, conventionally, in the case where this kind of metal-gate MISFET is manufactured, the MISFET structure is formed in advance by using some material as the gate electrode2 in order to form in self-alignment the gate electrode and the source-drain region. In the foregoing steps, after this dummy gate electrode 2 is removed, and the dummy
gate insulation film 6 located below the dummy gate electrode 2 is removed, the gate oxidation is performed, and the metal is embedded therein to form areal metal-gate electrode 9. - However, this conventional metal-gate MISFET has a problem that a parasitic resistance of the source-drain region is large.
- Supposing that a silicide film is formed on the source-drain region of the metal-gate field effect transistor as can be seen in the present invention, the parasitic resistance of the source-drain region can be lowered. However, in the conventional method, such a silicide film can not be formed on the source-drain region.
- In other words, in the conventional method, when the metal-made gate electrode is formed followed by implanting ions to form the source-drain region by using the metal-made gate electrode as a mask for self-alignment, it is required to regulate a temperature for activating implanted ions to at most 800° C. or so in order to avoid the melting of the metal. However, the activation of the implanted ions becomes insufficient at such a temperature of heat treatment. Besides, after the dummy gate electrode and the gate insulation film are removed, the presence of the silicide film on the source-drain region at the time of the gate oxidation leads to the deterioration of the electric characteristics owing to the oxidation of the silicide film. For such a reason, the silicide film could not be formed on the source-drain region of the conventional metal-gate MISFET.
- An object of the present invention is to provide a metal-gate field effect transistor having a low parasitic resistance of the source and drain and a method for manufacturing the same.
- A metal-gate field effect transistor according to a first aspect of the present invention comprises a metal-gate electrode formed on a semiconductor substrate, and a source-drain region formed on the surface of the semiconductor substrate on both sides of the metal-gate electrode, the transistor being characterized in that a cobalt silicide film is formed on the source-drain region.
- A metal-gate field effect transistor according to a second aspect of the present invention comprises a metal-gate electrode formed on a semiconductor substrate, and a source-drain region formed on the surface of the semiconductor substrate on both sides of the metal-gate electrode, the transistor being characterized in that a conductive film formed of the same material as the metal-gate electrode is formed on the source-drain region.
- A method for forming the metal-gate field effect transistor according to the first aspect of the present invention comprises the steps of:
- forming a source-drain region of the surface of the semiconductor substrate, a dummy gate electrode and a dummy gate insulation film on the semiconductor substrate, and a silicide film on the source-drain region;
- forming a sealing film such as silicon nitride or the like on the silicide film;
- removing the dummy electrode and the dummy gate insulation film;
- subjecting to oxidation the surface of the semiconductor substrate of the gate portion to form a gate oxide film; and
- embedding a metal material in the gate portion to form the metal-gate electrode.
- A method for manufacturing the metal-gate field effect transistor according to the second aspect of the present invention comprises the steps of:
- forming a source-drain region of the surface of a semiconductor substrate, and a dummy gate electrode and a dummy gate insulation film on the semiconductor substrate;
- removing the dummy gate electrode and the dummy gate insulation film;
- subjecting to oxidation the surface of the substrate of the gate portion to form a gate oxide film;
- depositing a titanium nitride film;
- opening a region including at least a portion of an area on the source-drain region;
- depositing a barrier metal film; and
- simultaneously embedding the gate port-ion and the opening on the source-drain region to form the metal-gate electrode.
- A method for manufacturing the metal-gate field effect transistor according to a third aspect of the present invention comprises the steps of:
- forming the source-drain region of the surface of the semiconductor substrate, and a dummy gate electrode, a dummy gate insulation film and a silicon dioxide film on the semiconductor substrate;
- forming a first sealing film such as silicon nitride or the like on the dummy gate electrode;
- etching in self-alignment the silicon dioxide film on the source-drain region with respect to the gate electrode by using as a mask the side wall insulation film and the sealing film;
- embedding an opening on the source-drain region with a metal to form a conductive film;
- forming a second sealing film such as silicon nitride or the like on the surface of this conductive film;
- exposing the surface of the dummy gate electrode;
- removing the dummy gate electrode and the dummy gate insulation film and subjecting to oxidation the surface of the semiconductor substrate of the gate portion thereby forming a gate oxide film and embedding the gate portion with a metal to form a metal-gate electrode.
- According to the present invention, since an upper portion of the silicide film is sealed with the sealing film such as silicon nitride or the like, the silicide film is not exposed to an atmosphere of the oxidation even when the silicide film is exposed to a high temperature with the result that the deterioration of the silicide film can be prevented.
- Then, since the silicide film is present on the source-drain region, the parasitic resistance of the source-drain region can be reduced.
- Furthermore, in the place of the silicide film, even when the conductive film formed of the same metal material as the gate electrode is formed on the source-drain region, the parasitic resistance of the source-drain region can be reduced.
- FIG. 1 is a sectional view showing a conventional metal gate MISFET;
- FIGS. 2A through 2E are sectional views showing a method for manufacturing this conventional metal gate MISFET in the order of the steps thereof;
- FIG. 3 is a sectional view showing a metal gate MISFET according to a first embodiment of the present invention;
- FIGS. 4A through 4E are sectional views showing a method for manufacturing the metal gate MISFET according to the first embodiment of the present invention in the order of the steps thereof;
- FIG. 5 is a sectional view showing the metal gate MISFET according to a second embodiment of the present invention;
- FIGS. 6A through 6E are sectional views showing the method for manufacturing the metal gate MISFET according to the second embodiment of the present invention in the order of the steps thereof; and
- FIGS. 7A through 7G are sectional views showing a method for manufacturing the metal gate MISFET according to a third embodiment of the present invention in the order of the steps thereof.
- Hereinafter, preferred embodiments of the present invention will be specifically explained by referring to the accompanied drawings. FIG. 3 is a sectional view showing a metal gate MISFET according to an embodiment of the present invention. FIGS. 4A through 4E are sectional views showing a method for manufacturing this metal gate MISFET in the order of the steps thereof. A
metal-gate electrode 12 formed of a metal material such as tungsten W or the like is formed via agate insulation film 15 on asemiconductor substrate 11. On both sides of thismetal gate electrode 12, a sidewall insulation film 13 is formed. Then, on the surface of thesemiconductor substrate 11, a low concentration source-drain region 17 is formed below the sidewall insulation film 13. Furthermore, outside of the low concentration source-drain region 17, a high concentration source-drain region 16 is formed. Then, in this embodiment, the surface of the source-drain region which surface is not covered with the sidewall insulation film 13 is covered with asilicide film 18. Thissilicide film 18 is, for example, a cobalt silicide film. - Subsequently, a method for manufacturing the metal gate MISFET having the above structure will be explained. As shown in FIG. 4A, on the surface of the
semiconductor substrate 11, a dummygate insulation film 21 is formed. Furthermore, adummy gate electrode 20 formed of polysilicon or the like is selectively formed, and the sidewall insulation film 13 is formed on the side wall of thedummy gate electrode 20. This sidewall insulation film 13 can be formed of silicon nitride or the like. - In this manner, a MISFET structure by means of the dummy gate electrode is formed. Then, on a high concentration source-
drain region 16 which is not covered with the sidewall insulation film 13 out of the source-drain region, thecobalt silicide film 18 having, for example, a thickness of 39 nm is formed. Furthermore, the whole surface of thecobalt silicide film 18 is covered with asilicon nitride film 19 having, for example, a thickness of 100 nm. Furthermore, in order to make planar the surface of the device, athick insulation film 22 is formed thereon. After that, theinsulation film 22 and thesilicon nitride film 19 on thedummy gate electrode 20 are selectively removed with the chemical and mechanical polishing method (CMP) to make planar the surface thereof. As a consequence, the surface of thedummy gate electrode 20 is exposed. As thethick insulation film 22 which is used at this step, a silicon oxide film is generally used. - Subsequently, as shown in FIG. 4B, the
dummy gate electrode 20 is removed. Then, on the surface of thesemiconductor substrate 11 of this gate portion,ion implantation 23 is performed for determining a punch-through stopper and a threshold value Vt. As ion seeds for determining this threshold value Vt, boron is generally used in the case of nMOSFET, and phosphorus is generally used in the case of pMOSFET. There is a case in which other kind of ions are used depending on the manufacturing steps. The present embodiment is not limited to the above kind of ions. - After that, as shown in FIG. 4C, the dummy
gate insulation film 21 is removed. - Subsequently, as shown in FIG. 4D, the gate insulation film (oxide film)15 is formed on the surface of the semiconductor substrate of the gate portion by subjecting to oxidation the surface of the semiconductor substrate in the oxidation atmosphere at a temperature of, for example, 700° C.
- After that, a metal film such as tungsten W or the like is formed on the whole surface of the
semiconductor substrate 11, a metal film is embedded in the gate portion, and the metal film is polished with the chemical and mechanical polishing method (CMP) thereby exposing the surface of themetal gate electrode 12 and completing the metal gate MISFET. - In the present embodiment, at the step of gate oxidation (FIG. 4D), the
cobalt silicide film 18 is sealed with thesilicon nitride film 19 so that thecobalt silicide film 18 is not exposed to the oxidation atmosphere and the characteristics thereof is not deteriorated. In the absence of thissilicon nitride film 19, thecobalt silicide film 18 is only covered with theinsulation film 22, and a silicon oxide film is normally used in thisinsulation film 22 as described above. Since this silicon oxide allows the passage of the oxidation seeds, the oxidation of thesilicide film 18 cannot be prevented. On the other hand, since thesilicon nitride film 19 in the present embodiment does not allow the passage of the oxidation seeds, the oxidation of thesilicide film 18 can be prevented. - As a consequence, even when the
silicide film 18 is exposed to a high temperature in the gate oxidation treatment, thesilicide film 18 is not exposed to the oxidation atmosphere with the result that the deterioration of thesilicide film 18 can be prevented. Then, since thesilicide film 18 is present on the source-drain region, the parasitic resistance of the source-drain region can be reduced. - Subsequently, a second embodiment of the present invention will be explained. FIG. 5 is a sectional view showing a metal-gate field effect transistor according to the second embodiment of the present invention. FIGS. 6A through 6F are sectional views showing the method for manufacturing the metal-gate field effect transistor according to the second embodiment in the order of the steps. In the second embodiment, on a region surrounded by a device
isolation insulation film 38 on the surface of thesemiconductor substrate 31, a low concentration source-drain region 35 and a high concentration source-drain region 34 are formed. On an area above a channel region, ametal gate electrode 32 is formed via agate insulation film 39. On the side wall of the channel region, a sidewall insulation film 33 is formed. Outside of each of the sidewall insulation films 33, aconductive film 37 is formed via aninsulation film 36. Thisconductive film 37 is formed of the same metal material as themetal gate electrode 32. - In the second embodiment, the silicide film is not present on the source-
drain regions conductive film 37 is present thereon with the result that the parasitic resistance of the source-drain regions - Subsequently, the method for manufacturing this metal-gate field effect transistor will be explained. In the beginning, as shown in FIG. 6A, a
dummy gate electrode 41 and a dummygate insulation film 42 are formed. - After that, as shown in FIG. 6B, after the
dummy gate electrode 41 and thedummy insulation film 42 are removed,ion implantation 40 is performed to form an implantation layer, and the gate oxidation is performed with the result that a gate insulation film (oxide film) 39 is formed. - After that, as shown in FIG. 6C, a
titanium nitride film 43 is deposited to open a region including at least portion of an area on the source-drain region 34. - Subsequently, as shown in FIG. 6E, a
barrier metal film 44 is deposited. Thisbarrier metal film 44 comprises, for example, a laminated body of a titanium nitride film and a titanium film located below the titanium nitride film. The titanium nitride film is generally used as a barrier film. However, since this titanium nitride film has a poor adhesiveness with the insulation film or the like, the titanium film is used as a close contact layer. However, it goes without saying that thebarrier metal film 44 may be used as a single layer. - After that, as shown in FIG. 6F, the
metal gate electrode 32 and theconductive film 37 are formed by simultaneously embedding the gate electrode region and the opening on the source-drain region with a metal such as tungsten or the like by means of, for example, the CVD or the like, thereby completing the metal gate MISFET. - In this embodiment, the
conductive film 37 formed of the same metal material as the gate electrode is formed on the source-drain region at the same step as the gate electrode, the parasitic resistance of the source-drain region can be reduced, and the step thereof is simple, at the same time. - Subsequently, a third embodiment of the present invention will be explained. FIGS. 7A through 7G are sectional views showing the method for manufacturing the metal-gate field effect transistor according to the third embodiment of the present invention in the order of steps. The third embodiment is such that an opening on the source-drain region is formed in self-alignment with respect to a gate electrode.
- As shown in FIG. 7A, a
dummy gate electrode 62 and a dummygate insulation film 68 are formed on asemiconductor substrate 60, and a side wall insulation film 61 is formed on the side walls of thedummy gate electrode 62 with silicon nitride, and a silicon nitride cap portion 63 is formed on thedummy gate electrode 62. Furthermore, the source-drain region 64 is formed on the surface of the semiconductor substrate, and an SiO2 film 65 is formed on a region other than the gate portion on the semiconductor substrate. - After that, as shown in FIG. 7B, the Si0 2 film 65 on the source-
drain region 64 is etched and removed by using as a mask the silicon nitride side wall insulation film 61, and the silicon nitride cap portion 63 on thedummy gate electrode 62. As a consequence, an opening on the source-drain region 64 is opened in self-alignment with respect to the gate electrode 63. - Subsequently, as shown in FIG. 7C, a
barrier metal film 72 such as titanium nitride film or the like is formed with respect to the opening on the source-drain region in the beginning. Then, the opening is embedded with aconductive film 66 such as tungsten W or the like. After that, as shown in FIG. 7D, a sealingportion 67 of the siliconnitride sealing portion 67 is formed on the surface of theconductive film 66. - After that, as shown in FIG. 7E, and the surface of the
dummy gate electrode 62 is exposed by polishing the surface of the sealingportion 67, thedummy gate electrode 62 is removed, and the dummygate insulation film 68 is removed, andion implantation 73 is performed. - After that, as shown in FIG. 7F, the surface of the semiconductor substrate of the exposed gate portion is subjected to oxidation with the result that a
gate oxide film 69 is formed. - After that, as shown in FIG. 7G, after a
barrier metal film 71 covers the gate portion, a metal such as tungsten W or the like is embedded in the gate portion, and ametal gate electrode 70 is formed. As a consequence, a metal gage MISFET is completed. In the third embodiment, theconductive film 66 is formed on the source-drain region 64, the parasitic resistance of the source-drain region 64 can be reduced.
Claims (7)
1. A metal-gate field effect transistor comprising:
a semiconductor substrate;
a metal-gate electrode on the semiconductor substrate;
a source-drain region formed on the surface of the semiconductor substrate on both sides of the metal-gate electrode; and
a cobalt silicide film formed on the source-drain region.
2. A metal-gate field effect transistor comprising:
a semiconductor substrate;
a metal-gate electrode on the semiconductor substrate;
a source-drain region formed on the surface of the semiconductor substrate on both sides of the metal-gate electrode; and
a conductive film formed of the same material as the metal gate electrode which is formed on the source-drain region.
3. A method for manufacturing a metal-gate field effect transistor comprising the steps of:
forming a source-drain region on a surface of a semiconductor substrate, a dummy gate electrode and a dummy gate insulation film on the semiconductor substrate, and a silicide film on the source-drain region;
forming a sealing film on the silicide film;
removing the dummy gate electrode and the dummy gate insulation film;
subjecting to oxidation the surface of the semiconductor substrate of the gate portion to form a gate oxide film; and
embedding a metal material in the gate portion to form a metal-gate electrode.
4. A metal-gate field effect transistor according to claim 3 , wherein the sealing film is formed of silicon nitride.
5. A method for manufacturing a metal-gate field effect transistor comprising the steps of:
forming a source-drain region of the surface of a semiconductor substrate, and a dummy gate electrode and a dummy gate insulation film on the semiconductor substrate;
removing the dummy gate electrode and the dummy gate insulation film;
subjecting to oxidation the surface of the substrate of the gate portion to form a gate oxide film;
depositing a titanium nitride film;
opening a region including at least portion of an area on the source-drain region;
depositing a barrier metal film; and
simultaneously embedding the gate portion and the opening on the source-drain region with metal to form a metal-gate electrode.
6. A method for manufacturing a metal-gate field effect transistor comprising the steps of:
forming a source-drain region of a surface of a semiconductor substrate, and a dummy gate electrode, a dummy gate insulation film and an silicon oxide film on the semiconductor substrate;
forming a first sealing film on the dummy gate electrode;
etching in self-alignment a silicon oxide film on the source-drain region with respect to the gate electrode by using as a mask the side wall insulation film and the sealing film;
embedding an opening on the source-drain region with metal to form a conductive film;
forming a second sealing film on the surface of the conductive film;
exposing the surface of the dummy gate electrode;
removing the dummy gate electrode and the dummy gate insulation film and subjecting to oxidation the surface of the semiconductor substrate of the gate portion thereby forming a gate oxide film and embedding the gate portion to form a metal-gate electrode.
7. A method for manufacturing the metal-gate field effect transistor according to claim 6 , wherein the first and the second sealing portions are formed of silicon nitride.
Priority Applications (1)
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US10/360,653 US20030146480A1 (en) | 1998-08-24 | 2003-02-10 | Metal-gate field effect transistor and method for manufacturing the same |
Applications Claiming Priority (5)
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JP23776998A JP3175700B2 (en) | 1998-08-24 | 1998-08-24 | Method of manufacturing metal gate field effect transistor |
JP10-237769 | 1998-08-24 | ||
US37935999A | 1999-08-23 | 1999-08-23 | |
US09/895,168 US6544827B2 (en) | 1998-08-24 | 2001-07-02 | Metal-gate field effect transistor and method for manufacturing the same |
US10/360,653 US20030146480A1 (en) | 1998-08-24 | 2003-02-10 | Metal-gate field effect transistor and method for manufacturing the same |
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US09/895,168 Division US6544827B2 (en) | 1998-08-24 | 2001-07-02 | Metal-gate field effect transistor and method for manufacturing the same |
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US20030146480A1 true US20030146480A1 (en) | 2003-08-07 |
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US09/895,168 Expired - Fee Related US6544827B2 (en) | 1998-08-24 | 2001-07-02 | Metal-gate field effect transistor and method for manufacturing the same |
US10/360,653 Abandoned US20030146480A1 (en) | 1998-08-24 | 2003-02-10 | Metal-gate field effect transistor and method for manufacturing the same |
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FR2810157B1 (en) * | 2000-06-09 | 2002-08-16 | Commissariat Energie Atomique | METHOD FOR PRODUCING AN ELECTRONIC COMPONENT WITH SOURCE, DRAIN AND SELF-ALLOCATED GRID, IN DAMASCENE ARCHITECTURE |
US6562718B1 (en) * | 2000-12-06 | 2003-05-13 | Advanced Micro Devices, Inc. | Process for forming fully silicided gates |
US6534390B1 (en) * | 2002-01-16 | 2003-03-18 | Chartered Semiconductor Manufacturing Ltd. | Salicide method for producing a semiconductor device using silicon/amorphous silicon/metal structure |
FR2844396B1 (en) * | 2002-09-06 | 2006-02-03 | St Microelectronics Sa | METHOD FOR PRODUCING AN INTEGRATED ELECTRONIC COMPONENT AND ELECTRICAL DEVICE INCORPORATING AN INTEGRATED COMPONENT THUS OBTAINED |
KR100486654B1 (en) | 2003-08-07 | 2005-05-03 | 동부아남반도체 주식회사 | Method for formating triple gate oxide in semiconductor |
US6921711B2 (en) * | 2003-09-09 | 2005-07-26 | International Business Machines Corporation | Method for forming metal replacement gate of high performance |
US6908850B2 (en) * | 2003-09-10 | 2005-06-21 | International Business Machines Corporation | Structure and method for silicided metal gate transistors |
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US20060068556A1 (en) | 2004-09-27 | 2006-03-30 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
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US7262997B2 (en) * | 2005-07-25 | 2007-08-28 | Freescale Semiconductor, Inc. | Process for operating an electronic device including a memory array and conductive lines |
US7619275B2 (en) * | 2005-07-25 | 2009-11-17 | Freescale Semiconductor, Inc. | Process for forming an electronic device including discontinuous storage elements |
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US8993428B2 (en) * | 2009-10-05 | 2015-03-31 | International Business Machines Corporation | Structure and method to create a damascene local interconnect during metal gate deposition |
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JP3029653B2 (en) | 1990-09-14 | 2000-04-04 | 株式会社東芝 | Method for manufacturing semiconductor device |
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JPH07231092A (en) | 1993-12-22 | 1995-08-29 | Toshiba Corp | Semiconductor device and its manufacture |
JP3336604B2 (en) | 1996-12-13 | 2002-10-21 | ソニー株式会社 | Method for manufacturing semiconductor device |
JPH10200096A (en) | 1997-01-06 | 1998-07-31 | Sony Corp | Mos field-effect transistor and its manufacturing method |
JPH10198866A (en) | 1997-01-14 | 1998-07-31 | Tec Corp | Commodity sales data registration processor |
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1998
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2001
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-
2003
- 2003-02-10 US US10/360,653 patent/US20030146480A1/en not_active Abandoned
Cited By (4)
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US20060084247A1 (en) * | 2004-10-20 | 2006-04-20 | Kaiping Liu | Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation |
US7611943B2 (en) | 2004-10-20 | 2009-11-03 | Texas Instruments Incorporated | Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation |
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TWI789342B (en) * | 2015-12-29 | 2023-01-11 | 荷蘭商露明控股公司 | Flip chip led with side reflectors and phosphor |
Also Published As
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US6544827B2 (en) | 2003-04-08 |
JP2000068507A (en) | 2000-03-03 |
US20010038136A1 (en) | 2001-11-08 |
JP3175700B2 (en) | 2001-06-11 |
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