US20030048123A1 - Integrated circuit and method of adjusting capacitance of a node of an integrated circuit - Google Patents

Integrated circuit and method of adjusting capacitance of a node of an integrated circuit Download PDF

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Publication number
US20030048123A1
US20030048123A1 US09/942,354 US94235401A US2003048123A1 US 20030048123 A1 US20030048123 A1 US 20030048123A1 US 94235401 A US94235401 A US 94235401A US 2003048123 A1 US2003048123 A1 US 2003048123A1
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United States
Prior art keywords
transistor
integrated circuit
capacitance
output
inverter
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US09/942,354
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English (en)
Inventor
Robert Drost
Robert Bosnyak
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Sun Microsystems Inc
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Sun Microsystems Inc
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Priority to US09/942,354 priority Critical patent/US20030048123A1/en
Assigned to SUN MICROSYSTEMS, INC. reassignment SUN MICROSYSTEMS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BOSNYAK, ROBERT J., DROST, ROBERT J.
Priority to EP02255978A priority patent/EP1292031A3/de
Priority to US10/247,401 priority patent/US6867629B2/en
Publication of US20030048123A1 publication Critical patent/US20030048123A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H01L27/0808—Varactor diodes

Definitions

  • the present invention relates generally to integrated circuits and more particularly to methods of digitally adjusting capacitance of a node of an integrated circuit.
  • the present invention relates to an integrated circuit device and method of adjusting capacitance of a node of an integrated circuit
  • the device comprises a first digital input, a first parasitic capacitance block, a first output, a second digital input, a second parasitic capacitance block, and a second output.
  • the first parasitic capacitance block includes an inverter, a variable capacitance element, and a wire capacitance element.
  • the first parasitic capacitance block has a capacitance that is a function of the first digital input.
  • the first output is responsive to the first parasitic capacitance block, and the second output is responsive to the second parasitic capacitance block.
  • the integrated circuit comprises a digital inverter, a circuit node responsive to the digital inverter, a first transistor having a first terminal coupled to the circuit node and a second terminal coupled to a voltage source, a second transistor having a first terminal coupled to the circuit node and a second terminal coupled to ground, a capacitor element responsive to the circuit node, and an output coupled to the capacitor element.
  • the integrated circuit comprises a digital inverter, an intermediate circuit node responsive to the digital inverter, a transistor having a first terminal coupled to the intermediate node and a second terminal coupled to ground, a capacitor element responsive to the intermediate node, and an output coupled to the capacitor element.
  • the integrated circuit comprises a digital inverter, an intermediate circuit node responsive to an output terminal of the digital inverter, a transistor having a first terminal coupled to the intermediate node and a second terminal coupled to a voltage source, a capacitor element responsive to the intermediate node, and an output coupled to the capacitor element.
  • the integrated circuit comprises a digital input, a parasitic capacitance block containing a first intermediate node, and circuit logic.
  • the circuit logic contains a second intermediate node.
  • the parasitic capacitance block provides an output having a selectable capacitance, the output having a first capacitance when the digital input is in a first logic state and a second capacitance when the digital input is in a second logic state.
  • the method includes selecting a logic state of a digital input; applying the digital input to a parasitic capacitance block having an output, the output having a first capacitance when the digital input is in a first logic state and a second capacitance when the digital input is in a second logic state; and adjusting a capacitance with respect to a second circuit node within the integrated circuit by applying the output to the second circuit node.
  • FIG. 1 is a general block diagram of a system that incorporates an embodiment in accordance with the present invention.
  • FIG. 2 is a circuit diagram that illustrates an embodiment of the parasitic capacitance block of FIG. 1.
  • FIG. 3 is circuit diagram that illustrates another embodiment of the parasitic capacitance block of FIG. 1
  • FIG. 4 is a is circuit diagram that illustrates another embodiment of the parasitic capacitance block of FIG. 1
  • FIG. 5 is a circuit diagram that illustrates a particular implementation of the system of FIG. 1.
  • FIG. 6 is a circuit diagram that illustrates another particular implementation of the system of FIG. 1.
  • FIG. 7 is a general block diagram that illustrates an embodiment of an integrated circuit incorporating a parasitic capacitance block.
  • the device 100 includes a first digital input 102 , a second digital input 104 , a first parasitic capacitance block 106 , a second parasitic capacitance block 108 , a first output 110 and a second output 112 .
  • the first parasitic capacitance block 106 includes an inverter 114 , a variable capacitance element and intermediate circuit node 116 , and a wire capacitance 118 .
  • the second parasitic capacitance block 108 includes inverter 120 , variable capacitance element and intermediate circuit node 122 , and wire capacitance 124 . While the device 100 in FIG. 1 only shows first and second parasitic capacitance blocks 106 and 108 , it is intended that a plurality of parasitic capacitance blocks may be used.
  • a digital input logic state is selected for the digital inputs 102 , 104 .
  • the digital input logic state may be either a first state, representing logic 0, or a second logic state, representing logic 1.
  • the digital logic input 102 is fed to digital inverter 114 .
  • the output of digital inverter 114 is applied to variable capacitance element 116 .
  • the variable capacitance element 116 produces one of two selectable capacitance levels to wire capacitance 118 .
  • the wire capacitor 118 provides a substantially constant capacitance level.
  • the addition of the substantially constant wire capacitance 118 and the variable capacitance selected by variable capacitance element 116 is combined to then provide a selectable capacitance level at output node 110 .
  • digital input 104 provides a logic level to inverter 120 feeding variable capacitance element 122 .
  • the output of variable capacitance element 122 is combined with wire capacitance 124 in series to form a combined and selectable capacitance presented at output node 112 .
  • the parasitic capacitance block 106 includes inverter 114 , wire capacitance 118 , and transistor logic implementing the variable capacitance element 116 .
  • the inverter 114 has an input to receive digital input 102 , a terminal coupled to ground 138 , and another terminal coupled to voltage supply V DD 136 .
  • the inverter 114 has an output that is coupled to an intermediate node 130.
  • the intermediate node 130 is coupled to a first transistor 132 and to a second transistor 134 .
  • the first transistor 132 labeled P X is a PMOS type transistor having its gate terminal coupled to intermediate node 130 and its drain and source terminals coupled to supply voltage V DD 136 .
  • the second transistor 134 is an NMOS type of transistor having its gate terminal coupled to intermediate node 130 and having its drain and source terminals coupled to ground 138 .
  • the digital input 102 When the digital input 102 is set to the logic 1 level, the voltage at node 130 is at ground (also referred to as “GND”), the first transistor 132 is in the active (or “on” state), and the second transistor 134 is deactive (or in the “off” state). In this configuration, the output 110 is terminated to supply voltage V DD 136 . As shown for the circuit of FIG. 2, the digital input 102 may be used to select a logic 0 level where the output 110 terminates to ground, or may be used to select a logic 1 level where the output 110 is terminated to the supply voltage. Thus, the digital input 102 may be used to direct termination of the output 110 .
  • the parasitic capacitance block is composed of two series elements and a weak inverter driving the node between the two series elements.
  • One series element is a wire capacitance connected to the output node and to the intermediate node in the block.
  • a digital selection signal is fed to a weak inverter (minimum width transistors with extra long lengths, e.g., 0.8/2.0 um in a 0.4 um minimum feature length technology).
  • the inverter's output is connected to the intermediate node 130.
  • the inverter biases node 130 to V DD or GND depending on the digital selection signal, but does so with a very high resistance (because its width is small and length is long).
  • the inverter 114 takes a long time (where long time is just set to be long enough such that the noise pulse or frequency is much shorter than this time) to react to the high frequency noise on node 130.
  • the other series element in the block is composed of a PMOS and NMOS transistor.
  • the NMOS transistor 134 has its gate connected to node 130, and its source, drain, and bulk connected to GND.
  • the PMOS transistor 132 has its gate connected to node 130 and its source, drain, and bulk connected to GND.
  • the voltage on node 130 determines whether the transistor has a channel formed under its gate or not. If the voltage on node 130 is driven by the inverter to GND, then the NMOS transistor has no channel, and the PMOS transistor does have a channel. If the voltage on node 130 is driven by the inverter to V DD , then the NMOS transistor has a channel formed, while the PMOS transistor does not. The channel strongly affects the capacitance of the gate to the source drain connections of the transistor.
  • the capacitor divider formed by the NMOS and PMOS device then can have a 300 fF to 100 fF ratio between V DD and GND if node 130 is set to GND, or a 100 fF to 300 fF ratio if node 130 is set to V DD .
  • the wire capacitance 118 connecting node 130 to the output node 110 can be set to a smaller value than that of the PMOS and NMOS capacitances, for instance 50 fF.
  • the block present to the output node is a 44.4 fF capacitor which tracks 3 ⁇ 4 of the high frequency noise on V DD (and 1 ⁇ 4 of the noise on GND), or 3 ⁇ 4 of the high frequency noise on GND (and 1 ⁇ 4 of the noise on V DD ).
  • the output capacitance is 44.4 fF since the 50 fF wire capacitance is in series with 100 fF+300 fF.
  • the parasitic capacitance block 106 includes inverter 114 , wire capacitance 118 , and a single transistor for the variable capacitance element 116 .
  • the inverter 114 is coupled to the intermediate node 130.
  • the transistor 134 which is an NMOS type of transistor, has a gate terminal coupled to intermediate node 130.
  • the drain and source terminals for transistor 134 are coupled to ground 138 .
  • a first state i.e., the logic 0 state
  • the transistor 134 is active (in the “on” state) and the output 110 is terminated to ground 138 .
  • the digital input is set to a second state (i.e., the logic 1 state)
  • the voltage at node 130 is set to ground
  • the transistor 134 is in the deactive (or “off” state)
  • the output 110 is in a floating state. In the floating state, even though transistor 134 is deactive, certain parasitic capacitance will be present on node 130.
  • intermediate node 130 will have one of two different capacitances. Where the transistor 134 is active and a channel is formed, the gate capacitance between intermediate node 130 and ground is at a higher level. But, where transistor 134 is deactive, the gate channel is not formed within transistor 134 , and the intermediate node 130 is presented with a lower capacitance with respect to ground 138 . The variable capacitance nature of transistor configuration 134 then presents, in combination with substantially constant capacitor 118 , a variable combined capacitance to the output 110 . TABLE 2 VOLTAGE AT INPUT NODE 130 NX OUTPUT 0 V DD ON TERMINATES TO GROUND 1 GND OFF FLOATING
  • the parasitic capacitance block 106 includes inverter 114 , wire capacitance 118 , and a single PMOS transistor 132 .
  • the PMOS transistor 132 has its gate terminal coupled to intermediate node 130 , and has its drain and source terminals coupled to voltage supply source V DD 136 .
  • the output 110 is floating.
  • the digital input 102 is set to the logic 1 state
  • the voltage at node 130 is at ground
  • the transistor 132 is in an active (or “on” state)
  • the output 110 terminates to the supply voltage V DD 136 .
  • the output 110 is presented with two distinct levels of capacitance based on the binary logic states of digital input 102 .
  • variable capacitance is produced by the transistor 132 where in one state a channel is formed and an increased capacitance is present, and in another logic state, no channel is formed and a lower capacitance is present.
  • the wire capacitance may be sized to be large (at least a comparable size to the capacitance of the NMOS or PMOS transistor). For instance, if the NMOS transistor has 100 fF and 300 fF off and on capacitances, respectively, then the wire capacitance could be set to 300 fF. Then if node 130 is driven to GND, the output node is loaded by an effective 75 fF of capacitance to GND. If node 130 is driven to V DD , then the output node is loaded by an effective 150 fF of capacitance to GND. This gives 2:1 ratio for the capacitance. To achieve nearer to a 3:1 ratio, the capacitance of the wire capacitance needs to be larger than 300 fF.
  • the bulk node under the gate of the transistor presents a large capacitance which connects to the gate of the transistor when there is no channel formed. At low frequencies this capacitance would prevent any appreciably different total capacitance on the gate of the transistor whether there was a channel or not.
  • the bulk of the transistor is composed of a weakly resistive p- (in NMOS) or n- (in PMOS) semiconductor. The resistance of the bulk node is high enough so that the bulk capacitance is effectively removed at high frequencies (because its RC delay time is long). To enhance the resistance of the bulk node, any substrate may be placed as far away as possible (given latch-up design rules) from the NMOS and PMOS transistors.
  • FIG. 5 a further detailed circuit that includes a plurality of different parasitic capacitance blocks is shown.
  • the integrated circuit includes a plurality of digital inputs labeled 1 - 8 , a plurality of inverters, a plurality of different parasitic capacitance blocks (each providing different levels of selective capacitance), a plurality of wire capacitances, and a plurality of different outputs.
  • each of the parasitic capacitance blocks uses the two-transistor configuration illustrated in FIG. 2.
  • different capacitance and output termination levels may be selected for each of the plurality of outputs.
  • particular outputs may be terminated to either ground or to the supply voltage and particular selectable capacitances may be applied.
  • capacitances may be added to form a matching capacitance to compensate for noise on either the ground or the supply voltage input to the integrated circuit.
  • FIG. 6 shows another particular implementation of an integrated circuit device including a plurality of different parasitic capacitance blocks.
  • a combination of single transistor variable capacitance elements is used. Both the P-channel type transistor configuration and the N-channel type transistor configurations are shown.
  • the integrated circuit 700 includes parasitic capacitance blocks 106 , circuit logic module 702 and routing connection 706 .
  • the integrated circuit has a ground 138 and a supply voltage 136 .
  • Integrated circuit 700 includes digital input selection such as digital input 102 .
  • the parasitic capacitance block includes intermediate node 130, and the circuit logic module 702 includes at least one node such as node 704 .
  • Routing connection 706 may be used to apply an output 110 from the parasitic capacitance block 106 to adjust an effective capacitance for nodes within the circuit logic 702 .
  • the output 110 may be adjusted to have a programmed and predetermined capacitance level.
  • the selected capacitance level may then be applied to an internal node within the circuit logic, such as node 704 , so that the particular circuit node within the circuit logic has a desired capacitance with respect to either ground 138 or supply voltage 136 .
  • the effective capacitance to supply voltage 136 or ground 138 may be selectively modified and matched so that noise present on voltage supply 136 or ground 138 may be managed effectively.
  • a use of a digitally selectable and modifiable capacitance is to match the response of two nodes to high frequency noise on the high and low power supplies of an integrated circuit (IC). For instance, if the V DD supply of the IC undergoes a 0.5 volt voltage step, then depending on the parasitic capacitance from a node to V DD and to GND, the node will step somewhere from 0.5 to 0.0 volts. For instance, if the node has 100 fF of parasitic capacitance to V DD and no capacitance to GND, then the node will undergo a 0.5-volt noise step. But, if the node also has 100 fF of parasitic capacitance to GND, then the node will only undergo a 0.25 noise step.
  • IC integrated circuit
  • additional capacitance could be added to nodeA to match the ratio of parasitic capacitances seen on nodeB so that it also has a 500 mV noise bounce and there would be substantially no voltage difference between the two nodes.
  • the power supply noise bounce can be at a very high frequency ( ⁇ 200 picosecond (Ps) transition time); thus, the added parasitic capacitance needs to have very low series resistance so that its RC time constant is less than the noise's highest frequency.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Networks Using Active Elements (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
US09/942,354 2001-08-29 2001-08-29 Integrated circuit and method of adjusting capacitance of a node of an integrated circuit Abandoned US20030048123A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US09/942,354 US20030048123A1 (en) 2001-08-29 2001-08-29 Integrated circuit and method of adjusting capacitance of a node of an integrated circuit
EP02255978A EP1292031A3 (de) 2001-08-29 2002-08-28 Integrierte Schaltung und Verfahren zur Einstellung der Kapazität eines Knotens in einer integrierten Schaltung
US10/247,401 US6867629B2 (en) 2001-08-29 2002-09-19 Integrated circuit and method of adjusting capacitance of a node of an integrated circuit

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Application Number Priority Date Filing Date Title
US09/942,354 US20030048123A1 (en) 2001-08-29 2001-08-29 Integrated circuit and method of adjusting capacitance of a node of an integrated circuit

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US10/247,401 Continuation US6867629B2 (en) 2001-08-29 2002-09-19 Integrated circuit and method of adjusting capacitance of a node of an integrated circuit

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Publication number Priority date Publication date Assignee Title
US7057450B2 (en) * 2003-07-30 2006-06-06 Winbond Electronics Corp. Noise filter for an integrated circuit
KR100753032B1 (ko) * 2004-07-14 2007-08-30 주식회사 하이닉스반도체 입력단 회로
KR100558600B1 (ko) * 2005-02-02 2006-03-13 삼성전자주식회사 반도체 장치의 지연회로
EP1760887A3 (de) * 2005-08-18 2017-01-04 Linear Technology Corporation Schaltungen und Methoden zur Kompensation signalabhängiger Kapazitäten
TW200807872A (en) * 2006-07-25 2008-02-01 Princeton Technology Corp Delay circuit
TWI330946B (en) * 2007-03-12 2010-09-21 Via Tech Inc Phase-locked loop and compound mos capacitor thereof
CN101056105B (zh) * 2007-04-11 2011-05-11 威盛电子股份有限公司 复合式金属氧化物半导体电容以及锁相环

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JPS5931083B2 (ja) * 1975-09-19 1984-07-31 セイコーエプソン株式会社 半導体集積回路
JP2951802B2 (ja) * 1992-08-07 1999-09-20 シャープ株式会社 クロック発生回路
FR2696061B1 (fr) * 1992-09-22 1994-12-02 Rainard Jean Luc Procédé pour retarder temporellement un signal et circuit à retard correspondant.
US5825217A (en) * 1996-05-29 1998-10-20 Amir Lehavot Low power accelerated switching for MOS circuits
US5714907A (en) * 1996-07-29 1998-02-03 Intel Corporation Apparatus for providing digitally-adjustable floating MOS capacitance
KR100206707B1 (ko) * 1996-09-06 1999-07-01 윤종용 반도체 메모리 장치의 지연회로
JP3338758B2 (ja) * 1997-02-06 2002-10-28 日本電気株式会社 遅延回路
US5900766A (en) * 1997-07-11 1999-05-04 Hewlett-Packard Company Coupling charge compensation device for VLSI circuits
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US6150862A (en) * 1998-10-15 2000-11-21 Intel Corporation Stable delay buffer

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EP1292031A2 (de) 2003-03-12
US20030048124A1 (en) 2003-03-13
US6867629B2 (en) 2005-03-15
EP1292031A3 (de) 2003-10-22

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Owner name: SUN MICROSYSTEMS, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DROST, ROBERT J.;BOSNYAK, ROBERT J.;REEL/FRAME:012142/0565

Effective date: 20010827

STCB Information on status: application discontinuation

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