US20030030127A1 - Bipolar transistor and method of manufacturing same - Google Patents

Bipolar transistor and method of manufacturing same Download PDF

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US20030030127A1
US20030030127A1 US10/211,897 US21189702A US2003030127A1 US 20030030127 A1 US20030030127 A1 US 20030030127A1 US 21189702 A US21189702 A US 21189702A US 2003030127 A1 US2003030127 A1 US 2003030127A1
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region
collector
doping
bipolar transistor
semiconductor
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Hendrik Huizing
Jan Slotboom
Igor Lyuboshenko
Johan Klootwijk
Freerk Van Rijs
Joost Melai
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NXP BV
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Assigned to KONINKLIJE PHILIPS ELECTRONICS N.V. reassignment KONINKLIJE PHILIPS ELECTRONICS N.V. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: VAN RIJS, FREERK, KLOOTWIJK, JOHAN HENDRIK, MELAI, JOOST, HUIZING, HENDRIK GEZIENUS ALBERT, LYUBOSHENKO, IGOR, SLOTBOOM, JAN WILLEM
Publication of US20030030127A1 publication Critical patent/US20030030127A1/en
Assigned to KONINKLIJKE PHILIPS ELECTRONICS N.V. reassignment KONINKLIJKE PHILIPS ELECTRONICS N.V. CORRECTED RECORDATION FORM COVER SHEET TO CORRECT EXECUTION DATES, PREVIOUSLY RECORDED AT REEL/FRAME 013395/0512 (ASSIGNMENT OF ASSIGNOR'S INTEREST) Assignors: VAN RIJS, FREERK, LYUBOSHENKO, IGOR, MELAI, JOOST, HUIZING, HENDRIK GEZIENUS ALBERT, KLOOTWIJK, JOHAN HENDRIK, SLOTBOOM, JAN WILLEM
Assigned to NXP B.V. reassignment NXP B.V. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KONINKLIJKE PHILIPS ELECTRONICS N.V.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H01L29/7378—Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors

Definitions

  • the invention relates to a bipolar transistor comprising
  • the invention also relates to a method of manufacturing a bipolar transistor comprising a collector region of a semiconductor material with a first doping type onto which a base region of a semiconductor material with a second doping type, opposite to the first doping type, is provided.
  • JP-A 5-74800 discloses a bipolar transistor comprising SiGe as the semiconductor material in the base region.
  • Bipolar transistors are used in a large number of applications, inter alia high-frequency RF applications, such as low-noise amplifiers, multiplexers and demultiplexers. Bipolar transistors with a cutoff frequency of typically 100 GHz can suitably be used as a component in optical communications networks for transferring typically 40 Gb/s.
  • the design of such bipolar transistors is a trade-off between a large number of parameters.
  • An important parameter is the breakdown voltage between the collector and the base or the emitter.
  • the speed of the transistor decreases as the breakdown voltage increases.
  • the speed of the transistor is expressed in a different, important parameter, namely the cutoff frequency.
  • the cutoff frequency is defined as the frequency at which the transistor ceases amplifying the current and the current gain has become equal to 1.
  • the known heterojunction bipolar transistor comprises SiGe in the base region.
  • the extremely thin SiGe base region is surrounded, on the side of the collector, by an area of semiconductor material.
  • Said area of semiconductor material is an intrinsic or lightly doped material with a doping level of maximally 5 ⁇ 10 16 cm ⁇ 3 .
  • the collector region Adjacent to this area, the collector region comprises a part that is comparatively lightly n-type doped with typically 1 ⁇ 10 17 cm ⁇ 3 and a part that is comparatively heavily n-type doped with 1 ⁇ 10 20 cm ⁇ 3 .
  • the stepwise build-up of the doping in the collector region leads to a stepwise increase of the electric field in the collector. As a result of this gradient in the electric field, the breakdown voltage is comparatively high.
  • the semiconductor material of the area on the side of the collector is SiGe or Si. If said semiconductor material is SiGe, then the cutoff frequency is reduced at high current densities as a result of high injection (Kirk effect). If said semiconductor material is Si, i.e. when the doping level of the area is increased to a concentration of maximally 5 ⁇ 10 16 cm ⁇ 3 , the cutoff frequency does not decrease at high current densities because the doping of the collector is sufficiently high to ensure that the Kirk effect does not occur anymore.
  • the emitter-collector breakdown voltage is negatively influenced by the increase of the doping in the area.
  • this object is achieved in that the collector region is doped such that the semiconductor area is fully depleted and the size of the intrinsic electric field in the semiconductor area is at least substantially independent of the doping types used and the concentration of the doping in the semiconductor area.
  • the semiconductor area typically has a lower doping concentration than the collector, base or emitter regions, so that the area is depleted of charge carriers. Consequently, the semiconductor area is a depletion region.
  • the collector region comprises only one part of heavily doped semiconductor material.
  • the comparatively high doping of the collector region causes the intrinsic electric field in the fully depleted semiconductor area to be very high, typically >10 5 V/cm for Si.
  • the intrinsic electric field in the fully depleted semiconductor area typically >10 5 V/cm for Si.
  • the value of the electric field is approximately a factor of 10 higher.
  • Even if no reverse voltage is applied across the collector base, the built-in voltage is sufficiently high to generate this very high intrinsic electric field.
  • An additional electric field caused by doping atoms in the semiconductor area has hardly any influence on the total electric field, which remains substantially equal to the intrinsic field.
  • the semiconductor area may thus be n-type as well as p-type with a random doping level, the level of the doping being smaller than that of the base and collector regions.
  • a large number of parameters of the transistor depend substantially on the electric field in the semiconductor area.
  • the electric field is at least substantially independent of the level and type of the doping
  • the cutoff frequency and the breakdown voltage are at least substantially independent of the level and type of the doping.
  • the bipolar transistor is a vertical transistor, i.e. the charge carriers are injected from the emitter region into the base region after which they drift through the depleted semiconductor area and, in the collector region, to a collector contact.
  • the charge carrier transport in the semiconductor area is vertical owing to the very large strength of the electric field. Therefore it is useful to take the width of the semiconductor area into consideration, which is defined as the distance between the base region and the collector region. If the transistor is switched off, the integral of the electric field across the depletion region is the built-in voltage. The value of the electric field increases as the width of the semiconductor area decreases.
  • the electric field is substantially constant in the semiconductor area if the distance between the base region and the collector region is comparatively small relative to the maximally depletable distance at the given doping of the semiconductor area and the built-in voltage of the base-collector junction.
  • the depletion region of the base-collector junction is largely situated in the semiconductor area.
  • the built-in voltage applied across the base collector junction is the product of the electric field in the semiconductor area and the width of the semiconductor area.
  • the strength of the electric field is further increased by applying a reverse base-collector voltage.
  • the comparatively small width of the completely depleted semiconductor area has the important advantage that the cutoff frequency is very high as the presence of the charge carriers in the semiconductor area is limited to a minimum amount of time because, owing to the very strong, substantially constant electric field throughout the area, they move at the saturated drift velocity.
  • the small width has the advantage that comparatively few charge carriers acquire sufficient kinetic energy in the electric field in the semiconductor area to bring about impact ionization that leads to breakdown.
  • the base-collector breakdown voltage and the related emitter-collector breakdown voltage can be increased.
  • the doping concentration in the base region is optimized for a certain current setting and a short base transit time.
  • the doping concentration in the collector region is limited by the solubility product of doping atoms, there is a maximum distance over which the semiconductor area can be depleted of charge carriers.
  • the collector region is comparatively heavily doped, i.e. typically in excess of 5 ⁇ 10 18 cm ⁇ 3 for Si, the depletion region of the base-collector junction always lies in the semiconductor area, even if the semiconductor area has the same doping type as the base region.
  • the semiconductor area is depleted.
  • the maximum distance over which the semiconductor area can be depleted is approximately 170 nm, at the given values for Si.
  • the electric field must be very strong to be independent of the level and type of the doping, typically >10 5 V/cm.
  • the width of the semiconductor area is comparable due to the comparable value of the built-in voltage and comparable electric fields.
  • the cutoff frequency is largely determined by the transit time of charge carriers through the semiconductor area.
  • the electric field always is very strong, independent of the doping of the semiconductor area.
  • the charge carriers in the semiconductor area move at the saturated drift velocity.
  • the transit time is determined only by the width of the semiconductor area, not by the doping level.
  • An additional advantage of the depleted semiconductor area is that the small signal behavior of the transistor is linear, also at high current densities. For small currents, the collector-base capacitance is constant. At large currents, the charge storage in the collector is dominant and hence limits the velocity of the transistor. As the electric field is very strong in the semiconductor area, the charge carriers always move at the saturated drift velocity, independent of the applied voltage. Thus, the stored charge scales linearly with the current. By virtue of this linear behavior, the transistor can very suitably be operated at high currents and high frequencies.
  • the distribution of the electric field takes place in a very narrow area.
  • the collector-base junction breaks down as a result of impact ionization.
  • Impact ionization is not a localized effect.
  • the charge carriers need some time and space to warm up in the electric field before they have acquired sufficient energy to cause impact ionization.
  • the relaxation length for Si is approximately 65 nm. This non-local avalanche effect causes a comparatively high collector-base breakdown voltage.
  • the collector-emitter breakdown voltage is a function of the collector-base voltage and the current amplification of the transistor. Due to the comparatively high collector-base voltage, the collector-emitter breakdown voltage is comparatively high too relative to transistors without a depleted semiconductor area. At a very small width of the semiconductor area of approximately 35 nm for Si, the collector-emitter breakdown voltage converges to a value that is independent of the doping. The collector-emitter breakdown voltage BVceo then depends only on the width of the area, and not on the doping. In this case, the collector-emitter breakdown voltage is never below 1.8 V for Si. Thus, at extremely small widths of the semiconductor area, the collector-emitter breakdown voltage remains comparatively high.
  • the width of the semiconductor area is very small, typically below 35 nm for Si.
  • the collector-emitter breakdown voltage is comparatively high.
  • Both the collector-emitter breakdown voltage BVceo and the cutoff frequency are independent of the doping in the semiconductor area and are only a function of the width of the depleted semiconductor area.
  • the invention enables ultra rapid bipolar transistors having a comparatively very high collector-emitter breakdown voltage to be obtained.
  • the Johnson limit of 200 VGHz in silicon is exceeded at a width of typically 35 nm.
  • the base region of the bipolar transistor is made of a semiconductor material that differs from that used for the collector and the emitter, the bipolar transistor forming a heterojunction bipolar transistor.
  • the bipolar transistor may be a heterostructure comprising, for example, AlGaAs, InAlAs or SiC as the semiconductor material in the emitter and collector regions, and GaAs, InGaAs or Si as the semiconductor material in the base region.
  • the doping level in the base region may be higher, which can be attributed to the difference in bandgap. This has the favorable effect that the resistance in the base region is smaller than in homojunction bipolar transistors. Besides, the mobility of charge carriers in for example GaAs is much higher than in Si, resulting in a substantially reduced charge storage in the base region. In general, the speed of heterojunction bipolar transistors is much higher than that of homojunction transistors. Charge storage in the collector is generally responsible for the limitation in speed. The invention enables charge storage in the collector to be reduced substantially and the speed of the transistor to be increased.
  • the transistor is advantageously made of Si.
  • the semiconductor material of the emitter and collector regions is silicon, and the semiconductor material of the base region comprises SiGe.
  • Said SiGe is deposited as a layer by means of, for example, CVD, with the percentage of Ge determining the size of the bandgap.
  • the doping of the base region remains within the Si—Ge layer, so as to preclude that a parasitic energy barrier forms on the emitter side as well as the collector side.
  • a parasitic energy barrier reduces the advantageous effect of the SiGe layer.
  • the built-in voltage is sufficient to counteract the disadvantageous effect of the parasitic energy barrier on the collector side.
  • the bipolar transistor in accordance with the invention is less sensitive to process variations in the base region.
  • the invention also aims at providing a method of manufacturing the bipolar transistor of the type described in the opening paragraph, which method enables a comparatively thin layer of semiconductor material with an accurately adjustable doping concentration to be reliably obtained between the base and collector regions.
  • the object of the invention regarding the method is achieved in accordance with the invention in that semiconductor material is epitaxially provided over the collector region so as to form an epitaxial layer, and the epitaxial layer is doped in situ, and, subsequently, the base region is epitaxially provided.
  • the collector region may be a semiconductor substrate, a semiconductor body or a layer or region formed on a substrate.
  • the layer of semiconductor material typically has a lower doping concentration than the collector, base or emitter regions, so that the semiconductor layer is depleted of charge carriers.
  • the cutoff frequency and the collector-emitter breakdown voltage depend substantially on the thickness of the semiconductor layer, it is important that diffusion of the doping of the collector region and base region is limited as much as possible during the manufacturing process.
  • the collector region, the layer of semiconductor material, the base region and the emitter region are successively epitaxially provided and doped in situ, instead of providing the doping by means of ion implantation and electrically activating said doping in a high-temperature step.
  • the semiconductor material of the bipolar transistor may be crystalline silicon, III-V semiconductors, Si—Ge, Si—C layers or other compounds.
  • the thickness of the layer of semiconductor material is below 100 nm.
  • the doping concentration profiles of the base region and the collector region bounding the in situ-doped semiconductor layer must be steeper as the thickness of the layer of semiconductor material is smaller.
  • Autodoping and outdiffusion of the doping from the base region or collector region into the semiconductor layer can reduce the thickness of the in situ-doped semiconductor layer.
  • a bipolar transistor that can be manufactured comparatively readily comprises a silicon collector region on which an epitaxial layer of Si is deposited and doped in situ with As by means of CVD at temperatures around 700° C. Outdiffusion of doping atoms is reduced substantially by adding a small quantity of C, typically 0.2-0.3 at. %, to Si and Si—Ge layers.
  • the base region is situated in a layer of SiGe semiconductor material.
  • the in situ-doped Si semiconductor layer has been deposited, it is possible to start depositing SiGe in the layer of semiconductor material.
  • the layer of semiconductor material also comprises SiGe.
  • Transistors made of silicon generally comprise a base region that is p-type doped with B and a collector region that is n-type doped with, for example, As or Sb.
  • B p-type doped with B
  • collector region that is n-type doped with, for example, As or Sb.
  • An emitter region can be formed by applying a polysilicon layer with doping atoms of a first doping type and, subsequently, diffusing the doping atoms in the base region. Also in this diffusion step, the temperature preferably remains below 900° C. and the duration of the heating process is very short. This can be achieved using, for example, rapid thermal annealing (RTA) or laser annealing.
  • RTA rapid thermal annealing
  • laser annealing laser annealing
  • FIG. 1 diagrammatically shows the bipolar transistor in accordance with the invention
  • FIG. 2 diagrammatically shows the operation of the bipolar transistor in accordance with the invention, wherein
  • FIG. 2 a shows the doping concentration as a function of the position for an NPN transistor comprising n-type or p-type doping atoms in the semiconductor area;
  • FIG. 2 b shows the electric field in the semiconductor area for n-type or p-type doping atoms and different doping concentrations
  • FIG. 2 c shows the whole electric field in the semiconductor area at a reverse voltage across the collector-base junction, and different current densities.
  • FIG. 3 shows data regarding the cutoff frequency as a function of the width of the semiconductor area for the bipolar transistor in accordance with the first embodiment.
  • the n-type doping concentration in the semiconductor area varies;
  • FIG. 4 shows data regarding the cutoff frequency as a function of the collector-emitter breakdown voltage at different n-type doping concentrations for the bipolar transistor in accordance with the first embodiment.
  • the width of the semiconductor area varies from 30-100 nm in steps of 10 nm;
  • FIG. 5 shows a doping profile of a bipolar transistor wherein the layer of semiconductor material is situated between the base region and the collector region, said bipolar transistor being manufactured by means of the method in accordance with the invention.
  • the bipolar transistor shown in FIG. 1 comprises a collector region 1 , an emitter region 2 and a base region 3 that is situated between the emitter region 2 and the collector region 1 . Said regions are made of a semiconductor material.
  • the base region 3 has a second doping type, opposite to a first doping type of the emitter region and the collector region.
  • a semiconductor area 4 extends between the collector region 1 and the base region 3 . The semiconductor area is more lightly doped than the collector region 1 , base region 3 and emitter region 2 .
  • the different transistor regions can be made of, for example, crystalline silicon, III-V semiconductors, Si—Ge, Si—C layers or other compounds. It is of essential importance that the semiconductor area 4 is fully depleted.
  • the strength of the intrinsic electric field in the semiconductor area 4 is at least substantially independent of the doping type and the level of the doping in the semiconductor area 4 . Depletion of the semiconductor area has the advantage that, in the switched-off state of the transistor, the semiconductor area can be more heavily doped than in a situation where the semiconductor area is not depleted. The higher doping leads to an increase of the maximum current density when the device is in operation.
  • the bipolar transistor is suitable for operation at high frequencies and, in particular, enables the breakdown voltage to be increased without influencing the cutoff frequency. As a result of non-local avalanche effects, the highest possible product of the cutoff frequency and the collector-emitter breakdown voltage can exceed the Johnson limit.
  • the bipolar transistor is an NPN heterojunction bipolar transistor with a p-type base and an n-type emitter and collector.
  • the p-type doping of the base region lies entirely in an SiGe layer.
  • the doping in the semiconductor area is generally lower than the doping in the base region or collector region.
  • the n-type doping of the collector region exceeds 5 ⁇ 10 18 cm ⁇ 3 .
  • the doping of the base region typically exceeds 5 ⁇ 10 17 cm ⁇ 3 .
  • the semiconductor area may be n-type doped, as indicated on the left-hand side in FIG. 2 a , or p-type doped as indicated on the right-hand side.
  • the arrow at the donor and acceptor concentration indicates that the concentration can be varied over a wide range, as long as the semiconductor area is depleted.
  • the semiconductor area is depleted. In this case, the maximum distance over which the semiconductor area can be depleted is approximately 170 nm.
  • the intrinsic electric field shown in FIG. 2 b is very strong, typically >10 5 V/cm, in the fully depleted semiconductor area.
  • the built-in voltage across the collector-base junction is sufficient to generate this very strong intrinsic electric field.
  • An additional electric field resulting from doping atoms in the semiconductor area causes the electric field to be tilted in the direction indicated by the arrows.
  • the very strong electric field resulting from the built-in voltage of the base-collector junction is influenced to a comparatively small extent by the type of doping atoms and the doping level, and is further increased by a reverse voltage applied across the collector-base junction.
  • the integral across the electric field and the width of the semiconductor area corresponds approximately to the sum of the built-in voltage V BI and the reverse voltage V CB applied across the collector-base.
  • FIG. 2 c shows that as a result of the increase in current density I, the maximum in the overall electric field can shift from the border between the base region and the semiconductor area to the border between the semiconductor area and the collector region (see left drawing in FIG. 2 c ). However, the change of the overall electric field is small due to the applied current.
  • Cutoff frequency calculations are performed for a bipolar transistor comprising an n-type collector region with a doping of 2 ⁇ 10 21 cm ⁇ 3 , a thin SiGe layer comprising 20% Ge with a p-type doping having a doping concentration of 1 ⁇ 10 18 cm ⁇ 3 , which serves as the base region.
  • the emitter region has a doping concentration of 2 ⁇ 10 21 cm ⁇ 3 .
  • the emitter region is provided with an emitter contact.
  • the calculations are performed at a collector-base voltage of 0 V.
  • the simulated data clearly show the favorable influence that the reduction of the width of the semiconductor area from 100 nm to 30 nm, in steps of 10 nm, has on the cutoff frequency.
  • the increase of the doping concentration from 1 ⁇ 10 15 cm ⁇ 3 to 5 ⁇ 10 17 cm ⁇ 3 leads to an increase of the cutoff frequency due to the smaller charge storage.
  • a reduction of the width of the semiconductor area from 100 nm to 30 nm causes the influence of the doping level on the cutting frequency to become smaller and smaller.
  • the maximum cutoff frequency is 110 GHz at a width of the semiconductor area of 30 nm, and independent of the doping level. The charge carriers move through the depleted semiconductor area at saturated drift velocity.
  • the maximum cutoff frequency is attained at high current densities of typically 5 mA/ ⁇ m 2 .
  • the current intensity can be much higher than in conventional devices as a result of the fact that the doping concentration in the semiconductor area can be higher.
  • the cutoff frequency increases linearly at a linear decrease of the width 5 of the semiconductor area 4 at a value of approximately 60 nm.
  • the invention enables the standard limit of the product of the cutoff frequency and the collector-emitter breakdown voltage to be exceeded.
  • the influence of the level of the n-type doping in the semiconductor area on the cutoff frequency as a function of the collector-emitter breakdown voltage is shown in FIG. 4.
  • the simulated transistor has the same doping concentrations as in the calculations mentioned hereinabove.
  • the collector-base breakdown voltage decreases if the doping concentration increases from 1 ⁇ 10 15 cm ⁇ 3 to 5 ⁇ 10 17 cm ⁇ 3 .
  • the simulated data clearly show the favorable influence of the increase of the doping concentration from 1 ⁇ 10 15 cm ⁇ 3 to 5 ⁇ 10 17 cm ⁇ 3 on the cutoff frequency for widths of the semiconductor area of 100 nm.
  • the width decreases, i.e.
  • the solid line shown in FIG. 4 indicates the Johnson limit of 200 VGHz.
  • the Figure clearly shows that if the width of the semiconductor area is reduced from 100 nm to 30 nm in steps of 10 nm, corresponding to the same symbols extending from the bottom right to the top left in FIG. 4, the Johnson limit is exceeded. At a doping concentration of, for example, 3 ⁇ 10 17 cm ⁇ 3 , the Johnson limit is exceeded at a width of the semiconductor area below 40 nm.
  • the invention enables an SiGe HBT bipolar transistor having a breakdown voltage of 2 V and a cutoff frequency of 110 GHz to be obtained.
  • the emitter region and the base region are not optimized.
  • the invention and an optimized emitter and base region it is possible to attain a cutoff frequency of 210 GHz at a breakdown voltage of 1.8 V.
  • the Johnson limit of 200 VGHz is amply exceeded and is 378 VGHz for this optimized transistor.
  • a layer 6 of a semiconductor material is provided over a collector region 1 of Si semiconductor material with an n-type doping of 1 ⁇ 10 20 cm ⁇ 3 .
  • the epitaxial layer 6 is doped in situ.
  • the epi layer is n-type doped with P atoms in a concentration of 10 17 cm ⁇ 3 .
  • the layer of semiconductor material 6 has a thickness 7 below 100 nm.
  • the thickness of the epi layer after the epitaxial growth is 80 nm and is doped with phosphor atoms in a doping concentration of 10 17 cm ⁇ 3 .
  • the isolation is provided in the form of shallow trench isolation, the temperature being kept below 900° C.
  • the base region 3 is formed by epitaxially providing an Si or SiGe layer and subsequently doping it in situ with B atoms.
  • the Si or SiGe layer is epitaxially grown on the layer 6 of semiconductor material by means of chemical vapor deposition at a temperature of approximately 700° C.
  • the B concentration in the base region is 2 ⁇ 10 18 cm ⁇ 3
  • the thickness of the Si base region is 200 nm.
  • the base region is situated in a layer of SiGe semiconductor material.
  • the base region comprises, for example, a differentially, epitaxially grown layer packet of 20 nm intrinsic SiGe (18% Ge), 5 nm SiGe (18% Ge) doped with boron in a concentration of 6 ⁇ 10 19 cm ⁇ 3 , and 10 nm intrinsic SiGe (18% Ge).
  • the layer of semiconductor material also comprises SiGe.
  • the emitter region is formed on the base region.
  • the emitter region 2 is formed by providing a typically 200 nm thick polysilicon layer 8 by means of a CVD process at a temperature of typically 600-700° C.
  • N-type doping atoms such as P or As, are provided in situ during the growth process.
  • As is implanted in a concentration of 2 ⁇ 10 15 cm ⁇ 3 in the polysilicon layer 8 .
  • the doping atoms are diffused in the base region 3 .
  • a bipolar transistor in, for example, a BiCMOS process, it is important to keep the temperature below 900° C.
  • the duration of the heating process is very short, typically 10 s at 1000° C. in a rapid thermal anneal process.
  • the width 5 of the semiconductor area 4 is reduced from 80 nm to 30-40 nm, as is shown in the concentration profile of the transistor shown in FIG. 5. Although diffusion of doping atoms is limited by a minimum thermal budget, the width 5 of the semiconductor area is reduced in the embodiment shown in FIG. 5.
  • a typical value of the gradient of the electric field on the side of the collector of the semiconductor area is 0.1 V/cm 2 at a doping level of the collector of 1 ⁇ 10 20 cm ⁇ 3 .
  • all regions are epitaxially grown and deposited in situ in a CVD process.
  • the thermal budget is minimized during the growth of the regions that are doped in situ.
  • the steep doping profiles are advantageous.
  • the comparatively low solubility and electrical activation of the doping atoms at the relevant deposition temperatures are disadvantageous.
  • the isolation between the bipolar transistors and other semiconductor devices can be provided in a trench by means of a low-temperature deposition technique, such as high density plasma oxide or a spin-on-glass technique.
  • the invention is not limited to the examples described hereinabove, and that it can also be used in each bipolar transistor or other heterostructure bipolar transistor.
  • the invention is not limited to n-type transistors and can also be used for PNP transistors.
  • the device is not limited to silicon; use can also be made of germanium, germanium silicon, III-V and SiC bipolar devices.
US10/211,897 2001-08-07 2002-08-02 Bipolar transistor and method of manufacturing same Abandoned US20030030127A1 (en)

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WO2005098960A2 (de) * 2004-04-02 2005-10-20 Prema Semiconductor Gmbh Bipolar-transistor und verfahren zur herstellung eines bipolar-transistors
US7750371B2 (en) 2007-04-30 2010-07-06 International Business Machines Corporation Silicon germanium heterojunction bipolar transistor structure and method
US7900167B2 (en) 2007-10-24 2011-03-01 International Business Machines Corporation Silicon germanium heterojunction bipolar transistor structure and method
US11335794B2 (en) * 2013-03-15 2022-05-17 Matthew H. Kim Advanced wafer bonded heterojunction bipolar transistors and methods of manufacture of advanced wafer bonded heterojunction bipolar transistors

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WO2006061731A1 (en) 2004-12-06 2006-06-15 Koninklijke Philips Electronics N.V. Method of producing an epitaxial layer on a semiconductor substrate and device produced with such a method
JP2006303222A (ja) * 2005-04-21 2006-11-02 Mitsubishi Electric Corp ヘテロ接合バイポーラトランジスタおよびそれを備える増幅器
TWI559532B (zh) * 2007-04-30 2016-11-21 烏翠泰克股份有限公司 矽鍺異質接面雙極電晶體結構與方法（一）

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JP3074834B2 (ja) * 1991-09-17 2000-08-07 日本電気株式会社 シリコンヘテロ接合バイポーラトランジスタ
EP0818829A1 (en) * 1996-07-12 1998-01-14 Hitachi, Ltd. Bipolar transistor and method of fabricating it
JP3189878B2 (ja) * 1997-07-16 2001-07-16 日本電気株式会社 バイポーラトランジスタ
JP3658745B2 (ja) * 1998-08-19 2005-06-08 株式会社ルネサステクノロジ バイポーラトランジスタ

Cited By (8)

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WO2005098960A2 (de) * 2004-04-02 2005-10-20 Prema Semiconductor Gmbh Bipolar-transistor und verfahren zur herstellung eines bipolar-transistors
WO2005098960A3 (de) * 2004-04-02 2006-04-20 Prema Semiconductor Gmbh Bipolar-transistor und verfahren zur herstellung eines bipolar-transistors
US20070273007A1 (en) * 2004-04-02 2007-11-29 Hartmut Grutzediek Bipolar-Transistor And Method For The Production Of A Bipolar-Transistor
US7563685B2 (en) 2004-04-02 2009-07-21 Prema-Semiconductor GmbH Bipolar-transistor and method for the production of a bipolar-transistor
US7750371B2 (en) 2007-04-30 2010-07-06 International Business Machines Corporation Silicon germanium heterojunction bipolar transistor structure and method
US9450069B2 (en) 2007-04-30 2016-09-20 Ultratech, Inc. Silicon germanium heterojunction bipolar transistor structure and method
US7900167B2 (en) 2007-10-24 2011-03-01 International Business Machines Corporation Silicon germanium heterojunction bipolar transistor structure and method
US11335794B2 (en) * 2013-03-15 2022-05-17 Matthew H. Kim Advanced wafer bonded heterojunction bipolar transistors and methods of manufacture of advanced wafer bonded heterojunction bipolar transistors

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