US20030025698A1 - Programmed stall cycles slow-down video processor - Google Patents

Programmed stall cycles slow-down video processor Download PDF

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Publication number
US20030025698A1
US20030025698A1 US09/920,042 US92004201A US2003025698A1 US 20030025698 A1 US20030025698 A1 US 20030025698A1 US 92004201 A US92004201 A US 92004201A US 2003025698 A1 US2003025698 A1 US 2003025698A1
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US
United States
Prior art keywords
processor
clock cycles
bus
facility
coprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US09/920,042
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English (en)
Inventor
Abraham Riemens
Nathan Woods
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
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Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US09/920,042 priority Critical patent/US20030025698A1/en
Assigned to KONINKLIJKE PHILIPS ELECTRONICS N.V. reassignment KONINKLIJKE PHILIPS ELECTRONICS N.V. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WOODS, NATHAN, RIEMENS, ABRAHAM KAREL
Priority to PCT/IB2002/003195 priority patent/WO2003012631A1/fr
Priority to EP02755453A priority patent/EP1425657B1/fr
Priority to KR1020047001372A priority patent/KR100984636B1/ko
Priority to AT02755453T priority patent/ATE467866T1/de
Priority to CNB02814998XA priority patent/CN1329820C/zh
Priority to US10/207,507 priority patent/US6917365B2/en
Priority to DE60236362T priority patent/DE60236362D1/de
Priority to EP10158063A priority patent/EP2204732A1/fr
Priority to JP2003517741A priority patent/JP3987032B2/ja
Publication of US20030025698A1 publication Critical patent/US20030025698A1/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Definitions

  • the invention relates to a processor according to the preamble of claim 1 hereafter appended.
  • DVP Digital Video Platform
  • Such functions may be effected in hardware, in software, or in a mixture thereof, such choice depending on the processing function itself, and/or on the manufacturing volume of the function and/or circuit in question.
  • the multimedia may include video, graphics, audio, or other.
  • the present invention is directed to solving a problem that has been recognized when designing a multi-processor coprocessor that is able to perform both Motion Estimation (ME) and Motion Compensation (MC).
  • ME Motion Estimation
  • MC Motion Compensation
  • the prevailing bandwidth on the shared bus is a prime design issue, and the various processors should maintain synchronization on the time slot level of the processing of an entire field or frame.
  • the programming means are arranged according to claim 7. This is a straightforward and hardware-efficient solution.
  • FIG. 1 a general block diagram of a video processing system
  • FIG. 2 a multiprocessor chip embodying the present invention
  • FIG. 3 a programmable video processor according to the present invention
  • FIG. 4 an embodiment of a programming accumulator.
  • FIG. 5 a Table showing Highway Transfer Data for a standard-size scalable pixel block
  • FIG. 6 a further Table showing Data Rates during ME/MC for implementing such scalability.
  • FIG. 1 illustrates a general block diagram of a video processing system.
  • signal sources and in particular, video sources 42 , 44
  • video sources 42 , 44 will present video images for processing onto input communication facility 41 that may be a bus or another sharing organization among various stations.
  • Item 20 is a processing chip, which will be discussed more in detail hereinafter, and which will process the images as received.
  • chip 20 is associated to RAM 22 that may store an appropriate amount of information to smoothingly cope with peak flows from sources 42 , 44 , and as the case may be, with peak requests from video users 46 , 48 .
  • the latter will use video images as having been processed by chip 20 .
  • items 20 , 46 , 48 are mutually interconnected through output communication facility 45 that may be a bus or may be sharing among stations in another manner.
  • FIG. 2 illustrates a multiprocessor chip that is arranged for executing the processing and therewith embodying the present invention. Apart from the Random Access Memory 22 , the remainder of the Figure has been compacted into a Single Solid State chip 20 . Within this chip, interfacing between bus-facility or Onchip Data HighWay 28 and memory 22 is by way of Main Memory Interface 24 and Bus Arbiter 26 . Further bus-connected subsystems are Video Input Interface 30 , Memory Based Scaler 32 , Video Output Interface 34 , Central Processing Unit 38 and Processor 36 that executes both Motion Estimation and Motion Compensation. By themselves, M.E. and M.C. are common features of processing a multi-image sequence such as a film or animation, and the associated procedures will not be discussed herein for reasons of brevity. The same applies to the overall image processing functionality to be provided by processor 36 and the hardware and software facilities necessary therefor.
  • the processor 36 may operate in a time-multiplexed manner on three prime tasks. First, it calculates the motion vectors of an applicable image (ME), then it performs motion compensation on the luminance signal (MC-Y), and finally, it performs motion compensation on the chrominance signal (MC-UV).
  • the processing block in question may handle an image of arbitrary size, but in the embodiment the maximum throughput is two video streams of 512*240 pixels at 60 Hz, or alternatively 512*288 pixels at 50 Hz. A particular standardized stream amounts to 720*240 pixels at 60 Hz, or alternatively, 720*288 pixels at 50 Hz.
  • the actual display mode determines which conversion must be executed, which is usually a fixed property of a particular video product once it has been designed, inasmuch as changing of the display scan format is often unviable.
  • the display mode has the following parameter values for determining the actual conversion. Note that the selecting and management among all of these cases is controlled by the CPU, and some of these selection and management functionalities may even be changed dynamically, during run-time.
  • the scalability mode allows the application to effect a trade-off between image quality and the amount of resources used, such as highway bandwidth and available amount of background memory. This effectively controls the quality attained versus the resources that are availble.
  • Various possibilities are as follows:
  • frm frm—fld—fld, previous frame, current field, and next field
  • the data mode controls the amount of video that must be processed, such as only one main widow, as distinct from a background combined with a picture-in-picture display.
  • Various possibilities are:
  • the block 36 has been designed in the embodiment with the following properties:
  • the clock frequency is 150 MHz.
  • FIG. 3 illustrates a programmable video processor according to the present invention.
  • processor 50 there is an interface for communicating with other subsystems such as those shown in FIG. 2. Internal communication is effected by internal local bus 60 .
  • the various stations or facilities connected thereto are program ROM 54 , programmable PROM 54 for storing program and/or data, data RAM 58 , and finally processing element 56 that has both input and output coupled to the local bus 60 .
  • program ROM 54 program ROM 54
  • programmable PROM 54 for storing program and/or data
  • data RAM 58 data RAM 58
  • processing element 56 that has both input and output coupled to the local bus 60 .
  • Various control, address, and data interconnection lines have been ignored for brevity, inasmuch as they would represent straightforward solutions to persons skilled in the art.
  • FIG. 4 illustrates an embodiment of a programming accumulator.
  • a programming register 72 is loaded via line 70 with a first number.
  • the register content is forwarded to adder 74 for addition to the content of accumulator register 76 , the content being retrocoupled through interconnection 78 .
  • the sum of the two data is written back to accumulator storage facility 76 .
  • the higher the content of register 72 the more frequently carry output 80 from accumulator 76 will generate a carry signal.
  • the carry signal will then control an effective clock cycle for therewith having execute the processor of the present invention an image processing operation.
  • FIG. 5 is a Table showing Highway Transfer Data for a standard-size scalable pixel block of 128 ⁇ 8 pixels, during motion estimation and motion compensation for the various display modes. Motion estimation and motion compensation require approximately the same input data but produce different output data, and also different amounts of output data. Clearly, the total variation is about +50% in the rightmost column.
  • FIG. 6 is a further Table showing Data Rates during ME/MC for such scalability, and in particular, the consequences arising for the highway bandwidth during ME and MC for the various display modes recited supra.
  • the memory is operating at 166 MHz, 32 bits dual data rate, which results in a theoretical maximum highway bandwidth of
  • the throughput requirement is 732 Mbyte/sec. This bandwidth should therefore in principle being continually available, even in a relatively slow 50i/60i system.
  • the present invention offers a programmable slow down facility, inasmuch as the optimum would depend on the actual display mode.
  • a further requirement is to have the present invention introduce a facility to save bandwidth also for the processing of smaller images.
  • the present invention will therefore offer a programmable slowdown factor in the digital circuitry of the coprocessor.
  • a slowdown factor of S that is any real number, ⁇ 1 the following holds:
  • Motion Estimation requires S*1024 cycles to process 128*8 pixels
  • Motion Compensation requires S*1600 cycles to process 128*8 pixels.
  • the slowdown factor will be easily set in this manner.
  • An advantageous embodiment is through an accumulator that periodically accumulates an appropriate operand. The carry output will rise to high whenever the accumulator overflows. The carry out will be controlled by the overflows/wraps, for thereby controlling the stalling of the overall processor. Giving a few embodiments hereinafter for Motion Estimation would render the presenting of similar measures for Motion Compensation superfluous.
  • a further advantage of the programmable stalling according to the preceding is that it will allow other bus master stations, such as other coprocessors that have a lower priority than memory, to have relatively smaller buffers than would have been the case otherwise. Especially in the interval during which the stalling processor does not access the bus, lower priority master stations will be periodically allowed to temporarily grab the bus. In fact, this feature leads to smaller IC area, and inherently, to lower manufacturing costs.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Image Processing (AREA)
  • Control Of Stepping Motors (AREA)
  • Executing Machine-Instructions (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
US09/920,042 2001-08-01 2001-08-01 Programmed stall cycles slow-down video processor Abandoned US20030025698A1 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
US09/920,042 US20030025698A1 (en) 2001-08-01 2001-08-01 Programmed stall cycles slow-down video processor
JP2003517741A JP3987032B2 (ja) 2001-08-01 2002-07-29 プログラムされたストールサイクルの間スローダウンする機能を備えたプロセッサ
AT02755453T ATE467866T1 (de) 2001-08-01 2002-07-29 Prozessor mit geschwindigkeitsverringerung durch programmierten haltzyklus
EP02755453A EP1425657B1 (fr) 2001-08-01 2002-07-29 Processeur ayant une fonction de ralentissement grace a des cycles de temporisation programmes
KR1020047001372A KR100984636B1 (ko) 2001-08-01 2002-07-29 디지털 신호 처리 실행 프로세서
PCT/IB2002/003195 WO2003012631A1 (fr) 2001-08-01 2002-07-29 Processeur ayant une fonction de ralentissement grace a des cycles de temporisation programmes
CNB02814998XA CN1329820C (zh) 2001-08-01 2002-07-29 一种带有编程延缓周期的延迟设备的处理器
US10/207,507 US6917365B2 (en) 2001-08-01 2002-07-29 Processor provided with a slow-down facility through programmed stall cycles
DE60236362T DE60236362D1 (de) 2001-08-01 2002-07-29 Prozessor mit geschwindigkeitsverringerung durch programmierten haltzyklus
EP10158063A EP2204732A1 (fr) 2001-08-01 2002-07-29 Processeur doté d'une fonctionnalité de ralentissement via des cycles de blocage programmés

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/920,042 US20030025698A1 (en) 2001-08-01 2001-08-01 Programmed stall cycles slow-down video processor

Related Child Applications (1)

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US10/207,507 Continuation-In-Part US6917365B2 (en) 2001-08-01 2002-07-29 Processor provided with a slow-down facility through programmed stall cycles

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US09/920,042 Abandoned US20030025698A1 (en) 2001-08-01 2001-08-01 Programmed stall cycles slow-down video processor
US10/207,507 Expired - Lifetime US6917365B2 (en) 2001-08-01 2002-07-29 Processor provided with a slow-down facility through programmed stall cycles

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US10/207,507 Expired - Lifetime US6917365B2 (en) 2001-08-01 2002-07-29 Processor provided with a slow-down facility through programmed stall cycles

Country Status (8)

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US (2) US20030025698A1 (fr)
EP (2) EP1425657B1 (fr)
JP (1) JP3987032B2 (fr)
KR (1) KR100984636B1 (fr)
CN (1) CN1329820C (fr)
AT (1) ATE467866T1 (fr)
DE (1) DE60236362D1 (fr)
WO (1) WO2003012631A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005003961A2 (fr) * 2003-07-07 2005-01-13 Koninklijke Philips Electronics N.V. Systeme et procede pour le traitement de donnees
US20050156930A1 (en) * 2004-01-20 2005-07-21 Matsushita Electric Industrial Co., Ltd. Rendering device and rendering method
US20070136729A1 (en) * 2005-12-14 2007-06-14 Darren Neuman Method and system for efficient audio scheduling for dual-decode digital signal processor (DSP)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008097214A (ja) * 2006-10-10 2008-04-24 Hitachi Ltd アクセス権管理方法、管理計算機、及び管理プログラム
CN102097050B (zh) * 2009-12-11 2016-03-09 康佳集团股份有限公司 一种实现显示信号无缝切换的装置和方法

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US5175844A (en) * 1989-10-11 1992-12-29 Nec Corporation Execution rate controlling device
US5719800A (en) * 1995-06-30 1998-02-17 Intel Corporation Performance throttling to reduce IC power consumption
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US6674479B2 (en) * 2000-01-07 2004-01-06 Intel Corporation Method and apparatus for implementing 4:2:0 to 4:2:2 and 4:2:2 to 4:2:0 color space conversion
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005003961A2 (fr) * 2003-07-07 2005-01-13 Koninklijke Philips Electronics N.V. Systeme et procede pour le traitement de donnees
WO2005003961A3 (fr) * 2003-07-07 2005-03-31 Koninkl Philips Electronics Nv Systeme et procede pour le traitement de donnees
US20050156930A1 (en) * 2004-01-20 2005-07-21 Matsushita Electric Industrial Co., Ltd. Rendering device and rendering method
US20080158248A1 (en) * 2004-01-20 2008-07-03 Matsushita Electric Industrial Co., Ltd. Rendering device and rendering method
US20070136729A1 (en) * 2005-12-14 2007-06-14 Darren Neuman Method and system for efficient audio scheduling for dual-decode digital signal processor (DSP)
US7877752B2 (en) * 2005-12-14 2011-01-25 Broadcom Corp. Method and system for efficient audio scheduling for dual-decode digital signal processor (DSP)

Also Published As

Publication number Publication date
WO2003012631A1 (fr) 2003-02-13
ATE467866T1 (de) 2010-05-15
US6917365B2 (en) 2005-07-12
EP1425657A1 (fr) 2004-06-09
CN1537269A (zh) 2004-10-13
JP2005500601A (ja) 2005-01-06
US20030070107A1 (en) 2003-04-10
CN1329820C (zh) 2007-08-01
EP2204732A1 (fr) 2010-07-07
KR20040018534A (ko) 2004-03-03
KR100984636B1 (ko) 2010-10-05
EP1425657B1 (fr) 2010-05-12
JP3987032B2 (ja) 2007-10-03
DE60236362D1 (de) 2010-06-24

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