US20020142569A1 - Method for fabricating a nitride read-only -memory (nrom) - Google Patents
Method for fabricating a nitride read-only -memory (nrom) Download PDFInfo
- Publication number
- US20020142569A1 US20020142569A1 US09/820,305 US82030501A US2002142569A1 US 20020142569 A1 US20020142569 A1 US 20020142569A1 US 82030501 A US82030501 A US 82030501A US 2002142569 A1 US2002142569 A1 US 2002142569A1
- Authority
- US
- United States
- Prior art keywords
- layer
- oxide layer
- nrom
- ono
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 5
- 238000000034 method Methods 0.000 title claims description 38
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000004020 conductor Substances 0.000 claims abstract description 6
- HSXKFDGTKKAEHL-UHFFFAOYSA-N tantalum(v) ethoxide Chemical compound [Ta+5].CC[O-].CC[O-].CC[O-].CC[O-].CC[O-] HSXKFDGTKKAEHL-UHFFFAOYSA-N 0.000 claims abstract description 6
- 230000008569 process Effects 0.000 claims description 19
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000012159 carrier gas Substances 0.000 claims description 3
- 239000001272 nitrous oxide Substances 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 2
- 239000001307 helium Substances 0.000 claims description 2
- 229910052734 helium Inorganic materials 0.000 claims description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims 1
- 229910001882 dioxygen Inorganic materials 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052710 silicon Inorganic materials 0.000 abstract description 11
- 239000010703 silicon Substances 0.000 abstract description 11
- 239000004065 semiconductor Substances 0.000 abstract description 9
- 230000008878 coupling Effects 0.000 abstract description 5
- 238000010168 coupling process Methods 0.000 abstract description 5
- 238000005859 coupling reaction Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 3
- 238000006731 degradation reaction Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000009279 wet oxidation reaction Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- -1 nitride compound Chemical class 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- XUIMIQQOPSSXEZ-RNFDNDRNSA-N silicon-32 atom Chemical compound [32Si] XUIMIQQOPSSXEZ-RNFDNDRNSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
Definitions
- the present invention provides a method of fabricating a gate in a nitride read only memory (NROM).
- NROM nitride read only memory
- a read only memory (ROM) device composed of a plurality of memory cells, is a kind of semiconductor wafer device that functions in data storage.
- the ROM device is widely applied to computer data storage and memory.
- the ROM can be divided into several types such as a mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM), and an electrically erasable programmable ROM (EEPROM).
- PROM programmable ROM
- EPROM erasable programmable ROM
- EEPROM electrically erasable programmable ROM
- a nitride read only memory uses an insulating dielectric layer as a charge-trapping medium. Due to the highly-compacted nature of the silicon nitride layer, hot electrons tunneling from the MOS transistor into the silicon nitride layer are trapped within to form an unequal concentration distribution to hasten data reading speed and to avoid current leakage.
- An annealing process is then used under a high temperature of 950° C. for a duration of 30 minutes to repair the structure of the silicon nitride layer 36 .
- water steam is injected to perform a wet oxidation process to form a silicon oxy-nitride layer with a thickness of the 50-150 angstroms as a top oxide layer 38 .
- the bottom oxide layer 34 , the silicon nitride layer 36 and the top oxide layer 38 compose the ONO dielectric structure 40 on the surface of the silicon substrate 32 .
- a photolithographic and etching process is performed to form a gate pattern in the top oxide layer 38 and silicon nitride layer 36 .
- An ion implantation process is then performed to form a plurality of doped areas 42 as a source and drain in the MOS transistor.
- a thermal oxidation process is used to form a field oxide (FOX) 44 on the surface of the source/drain to isolate each silicon nitride layer 36 .
- a doped polysilicon layer 46 is deposited as a gate conductor layer.
- the method first forms a bottom oxide layer and a silicon nitride layer on the surface of a silicon substrate in the semiconductor wafer, respectively, followed by injecting a tantalum penta ethoxide (Ta(OC 2 H 5 ) 5 ), under the condition of 300 mTorr and 200-650° C., to deposit a tantalum pentoxde (Ta 2 O 5 ) layer as a top oxide layer.
- Ta 2 O 5 tantalum pentoxde
- the top oxide layer, silicon nitride layer and the bottom oxide layer compose an oxide-nitride-oxide (ONO) dielectric structure.
- a gate conductor layer is formed on the surface of the ONO structure to complete the fabrication of the NROM according to the present invention.
- the present invention uses tantalum pentaoxide, having a high dielectric constant, as a top oxide layer of the ONO dielectric layer, to thereby increase the coupling ratio, reduce both the control gate voltage and thermal budget of the fabrication, and to avoid the problem of gate oxide degradation due to high temperature so as to improve the production yield of the semiconductor wafer.
- FIG. 1 is a schematic diagram of a standard structure of an NROM according to the prior art.
- FIG. 2 and FIG. 3 are schematic diagrams of a method for fabricating an NROM using the standard structure shown in FIG. 1.
- the present invention first forms an ONO dielectric layer 60 with a thickness of 150-250 angstroms on the surface of the silicon substrate 52 .
- the method of fabricating an ONO dielectric structure 60 according to the present invention first involves performing a high temperature oxidation process to form an oxide layer with a thickness of 50-150 angstroms as a bottom oxide layer 54 on the surface of the substrate 52 .
- a LPCVD process is then performed by injecting a reaction gas mixture of dichlorosilane (SiH 2 Cl 2 ) and ammonia (NH 3 ) under the condition of 700-800° C. temperature and low pressure to form a silicon nitride layer 56 with a thickness of 50-150 angstroms on the surface of the bottom oxide layer 54 .
- a chemical vapor deposition (CVD) process is used under the condition of 200-650° C. temperature and 200-600 mTorr by injecting tantalum penta ethoxide (Ta(OC 2 H 5 ) 5 ) with a flowrate of 5-20 mg/min, oxygen with a flowrate of 500-2000 sccm(standard cubic centimeter per minute) and helium gas (He) as a carrier gas with a flowrate of 200-600 sccm, to form a tantalum pentaoxide layer(Ta 2 O 5 ) with a thickness of 60-800 angstroms as a top oxide layer 58 on the surface of the silicon nitride layer 56 .
- the reaction step is as follows:
- a reaction is performed at a temperature of 480° C., a pressure of 300 mTorr and a carrier gas (He) flowrate of 300 sccm, and tantalum penta ethoxide is injected at 7.5 mg/min and oxygen is injected at 1000 sccm to a form tantalum pentaoxide layer via CVD deposition with a thickness of 100 angstroms.
- the bottom oxide layer 54 , silicon nitride 56 and the top oxide layer 58 compose an ONO dielectric structure 60 on the surface of the substrate 52 .
- the tantalum pentaoxide which functions as a top oxide layer 58 , is of a high dielectric constant of 25, or equal to 6-fold of silicon oxide (dielectric constant 3.9) and 3-fold of silicon nitride (dielectric constant 7.5), the control gate voltage is efficiently reduced and both the coupling ratio and charge gain are increased.
- nitrous oxide N 2 O
- RTN rapid thermal nitridation
- TDDB time-dependent dielectric breakdown
- a photoresist layer (not shown) is formed on the surface of the ONO dielectric structure 60 , followed by a photolithographic and etching process to form a column pattern in the photoresist layer on the surface of the ONO dielectric layer 60 . Then, the photoresist layer is used as a mask to perform a ion implantation process 62 so as to form a plurality of doped area 64 functioning as a drain (i.e. bit line) and source. As shown in FIG. 6, after removing the photoresist layer, a thermal oxidation process is used to form an oxide layer 66 on the surface of the doped area 64 to isolate each silicon nitride layer 56 . Finally, a doped polysilicon layer 68 is deposited as a gate conductor layer (i.e. Word line).
- a gate conductor layer i.e. Word line
- the present invention uses a simpler process requiring a lower temperature to replace the higher-temperature wet oxidation.
- the thermal budget of NROM fabrication is reduced and the degradation of the gate oxide due to high temperature is prevented so as to improve the problems caused by the prior art.
- both the coupling ratio and charge gain greatly increase and both the gate control voltage and the defect density decrease so as to improve both the production yield of NROM and fabrication cost.
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
The present invention provides a method of fabricating an improved gate of a nitride read only memory (NROM) in a semiconductor wafer. A bottom oxide and a silicon nitride layer are first formed on the surface of a silicon substrate in the semiconductor wafer, respectively, followed by injecting a tantalum penta ethoxide (Ta(OC2H5)5), under the condition of 300 mTorr and 200-650° C., to form a tantalum pentaoxide (Ta2O5) layer as a top oxide layer. The top oxide layer, silicon nitride layer and the bottom oxide layer compose an oxide-nitride-oxide (ONO) dielectric structure. Finally, a gate conductor layer is formed on the surface of the ONO structure to complete the fabrication of the NROM of the present invention. The tantalum pentaoxide has a high dielectric constant and is used to reduce the control gate voltage and thermal budget so as to increase the coupling ratio and yield of the semiconductor wafer.
Description
- 1. Field of the Invention
- The present invention provides a method of fabricating a gate in a nitride read only memory (NROM).
- 2. Description of the Prior Art
- A read only memory (ROM) device, composed of a plurality of memory cells, is a kind of semiconductor wafer device that functions in data storage. The ROM device is widely applied to computer data storage and memory. Depending on the method of storing data, the ROM can be divided into several types such as a mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM), and an electrically erasable programmable ROM (EEPROM).
- Differing from other types of ROMs that use a polysilicon or metal floating gate, a nitride read only memory (NROM) uses an insulating dielectric layer as a charge-trapping medium. Due to the highly-compacted nature of the silicon nitride layer, hot electrons tunneling from the MOS transistor into the silicon nitride layer are trapped within to form an unequal concentration distribution to hasten data reading speed and to avoid current leakage.
- Please refer to FIG. 1. FIG. 1 is a schematic diagram of a standard structure of an NROM according to the prior art. A
semiconductor wafer 10 comprises a P-type silicon substrate 12, two N-type dopedareas silicon substrate 12, an ONOdielectric structure 24, and agate conductor layer 26 positioned on the ONOdielectric structure 24. The ONOdielectric structure 24 is composed of a bottom oxide layer 18, a silicon nitride layer 20 and atop oxide layer 22. - Please refer to FIG. 2 and FIG. 3. FIG. 2 and FIG. 3 are schematic diagrams of a method for fabricating an NROM using the standard structure shown in FIG. 1. As shown in FIG. 2, according to the prior art for fabricating a gate of the NROM, a
semiconductor wafer 30 comprising a P-type silicon 32 is first provided. A high temperature oxidation process is then performed to form an oxide layer with a thickness of 50-150 angstroms as abottom oxide layer 34 on the surface of thesilicon substrate 32. Next, a low-pressure chemical vapor deposition (LPCVD) is used to deposit asilicon nitride layer 36 with a thickness of 50-150 angstroms on thebottom oxide layer 34. An annealing process is then used under a high temperature of 950° C. for a duration of 30 minutes to repair the structure of thesilicon nitride layer 36. As well, water steam is injected to perform a wet oxidation process to form a silicon oxy-nitride layer with a thickness of the 50-150 angstroms as atop oxide layer 38. Thebottom oxide layer 34, thesilicon nitride layer 36 and thetop oxide layer 38 compose the ONOdielectric structure 40 on the surface of thesilicon substrate 32. - As shown in FIG. 3, a photolithographic and etching process is performed to form a gate pattern in the
top oxide layer 38 andsilicon nitride layer 36. An ion implantation process is then performed to form a plurality of dopedareas 42 as a source and drain in the MOS transistor. Thereafter, a thermal oxidation process is used to form a field oxide (FOX) 44 on the surface of the source/drain to isolate eachsilicon nitride layer 36. Finally, a dopedpolysilicon layer 46 is deposited as a gate conductor layer. - According to the prior art for forming a top oxide layer, the process requires higher temperature and thermal budget to form an oxide layer on the surface of the nitride compound. Thus, not only is greater cost needed, but the higher temperature may lead to the degradation of the gate oxide layer and affect the reliability of the NROM. Moreover, because of the low dielectric constant of silicon oxide, the top oxide layer comprises lower coupling ratio and higher control gate voltage.
- It is therefore a primary objective of the present invention to provide a gate fabrication method of an NROM with high dielectric constant of the top oxide layer to solve the above-mentioned problems.
- In accordance with the claim invention, the method first forms a bottom oxide layer and a silicon nitride layer on the surface of a silicon substrate in the semiconductor wafer, respectively, followed by injecting a tantalum penta ethoxide (Ta(OC2H5)5), under the condition of 300 mTorr and 200-650° C., to deposit a tantalum pentoxde (Ta2O5) layer as a top oxide layer. The top oxide layer, silicon nitride layer and the bottom oxide layer compose an oxide-nitride-oxide (ONO) dielectric structure. Finally, a gate conductor layer is formed on the surface of the ONO structure to complete the fabrication of the NROM according to the present invention. It is an advantage of the present invention that the present invention uses tantalum pentaoxide, having a high dielectric constant, as a top oxide layer of the ONO dielectric layer, to thereby increase the coupling ratio, reduce both the control gate voltage and thermal budget of the fabrication, and to avoid the problem of gate oxide degradation due to high temperature so as to improve the production yield of the semiconductor wafer.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
- FIG. 1 is a schematic diagram of a standard structure of an NROM according to the prior art.
- FIG. 2 and FIG. 3 are schematic diagrams of a method for fabricating an NROM using the standard structure shown in FIG. 1.
- FIG. 4 to FIG. 6 are schematic diagrams of a method for fabricating an NROM according to the prior invention.
- Please refer to FIG. 4 to FIG. 6. FIG. 4 to FIG. 6 are the schematic diagrams of a method for fabricating an NROM according to the present invention. As shown in FIG. 4, the NROM according to the present invention is fabricated on the surface of the
silicon substrate 52 in asemiconductor wafer 50. Thesilicon substrate 52 is a P-type silicon substrate, but the present invention is not limited to only this substrate type. - The present invention first forms an ONO
dielectric layer 60 with a thickness of 150-250 angstroms on the surface of thesilicon substrate 52. The method of fabricating an ONOdielectric structure 60 according to the present invention first involves performing a high temperature oxidation process to form an oxide layer with a thickness of 50-150 angstroms as abottom oxide layer 54 on the surface of thesubstrate 52. A LPCVD process is then performed by injecting a reaction gas mixture of dichlorosilane (SiH2Cl2) and ammonia (NH3) under the condition of 700-800° C. temperature and low pressure to form asilicon nitride layer 56 with a thickness of 50-150 angstroms on the surface of thebottom oxide layer 54. - Next, a chemical vapor deposition (CVD) process is used under the condition of 200-650° C. temperature and 200-600 mTorr by injecting tantalum penta ethoxide (Ta(OC2H5)5) with a flowrate of 5-20 mg/min, oxygen with a flowrate of 500-2000 sccm(standard cubic centimeter per minute) and helium gas (He) as a carrier gas with a flowrate of 200-600 sccm, to form a tantalum pentaoxide layer(Ta2O5) with a thickness of 60-800 angstroms as a
top oxide layer 58 on the surface of thesilicon nitride layer 56. The reaction step is as follows: - 2Ta(OC2H5)5+3002→Ta2O5+20CO2+25H2O
- In the preferred embodiment of the present invention, a reaction is performed at a temperature of 480° C., a pressure of 300 mTorr and a carrier gas (He) flowrate of 300 sccm, and tantalum penta ethoxide is injected at 7.5 mg/min and oxygen is injected at 1000 sccm to a form tantalum pentaoxide layer via CVD deposition with a thickness of 100 angstroms. The
bottom oxide layer 54,silicon nitride 56 and thetop oxide layer 58 compose an ONOdielectric structure 60 on the surface of thesubstrate 52. Since the tantalum pentaoxide, which functions as atop oxide layer 58, is of a high dielectric constant of 25, or equal to 6-fold of silicon oxide (dielectric constant 3.9) and 3-fold of silicon nitride (dielectric constant 7.5), the control gate voltage is efficiently reduced and both the coupling ratio and charge gain are increased. - Next, nitrous oxide (N2O) is injected at a temperature of 800° C. for a duration of 30 seconds to perform a rapid thermal nitridation (RTN)process, functioning as an annealing process, to repair the ONO dielectric structure, and thereby reduce the probability of current leakage of the tantalum pentaoxide and achieve an improved time-dependent dielectric breakdown (TDDB) characteristic of the tantalum pentaoxide film.
- As shown in FIG. 5, a photoresist layer (not shown) is formed on the surface of the ONO
dielectric structure 60, followed by a photolithographic and etching process to form a column pattern in the photoresist layer on the surface of the ONOdielectric layer 60. Then, the photoresist layer is used as a mask to perform aion implantation process 62 so as to form a plurality of dopedarea 64 functioning as a drain (i.e. bit line) and source. As shown in FIG. 6, after removing the photoresist layer, a thermal oxidation process is used to form anoxide layer 66 on the surface of thedoped area 64 to isolate eachsilicon nitride layer 56. Finally, a dopedpolysilicon layer 68 is deposited as a gate conductor layer (i.e. Word line). - In contrast to the prior art method for fabricating a gate of an NROM, the present invention uses a simpler process requiring a lower temperature to replace the higher-temperature wet oxidation. As a result, the thermal budget of NROM fabrication is reduced and the degradation of the gate oxide due to high temperature is prevented so as to improve the problems caused by the prior art. Moreover, because of the high dielectric constant property of tantalum pentaoxide, both the coupling ratio and charge gain greatly increase and both the gate control voltage and the defect density decrease so as to improve both the production yield of NROM and fabrication cost.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (7)
1. A method for fabricating a nitride read only memory (NROM), the method comprising:
providing a substrate;
forming a oxide-nitride-oxide (ONO) layer on the surface of the substrate, the ONO layer composed of a bottom oxide layer, a silicon nitride layer and a top oxide layer; and
forming a gate conductor layer on the surface of the ONO layer;
wherein, the top oxide layer is composed of tantalum pentaoxide (Ta2O5), deposited by a chemical vapor deposition (CVD) method.
2. The method of claim 1 wherein the fabrication temperature of the CVD method is between 200-650° C. and the pressure is between 200-600 mTorr.
3. The method of claim 1 wherein the thickness of the top oxide layer is between 60-800 angstroms.
4. The method of claim 1 wherein the top oxide layer is formed by the reaction of tantalum penta ethoxide (Ta(OC2H5)5) with oxygen, and the flow rate of the tantalum penta ethoxide is about 5-20 mg/min, and the flow rate of the oxygen gas is about 500-2000 mg/min.
5. The method of claim 4 wherein the reaction uses helium (He) as a carrier gas, and the flow rate of He is about 200-600 mg/min.
6. The method of claim 1 wherein the method further comprises an anneal process after forming the top oxide layer.
7. The method of claim 7 wherein the annealing process is a rapid thermal nitridation (RTN) process, performed by using nitrous oxide gas at a temperature of 800° C. for a duration of 60 seconds.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/820,305 US6461949B1 (en) | 2001-03-29 | 2001-03-29 | Method for fabricating a nitride read-only-memory (NROM) |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/820,305 US6461949B1 (en) | 2001-03-29 | 2001-03-29 | Method for fabricating a nitride read-only-memory (NROM) |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020142569A1 true US20020142569A1 (en) | 2002-10-03 |
US6461949B1 US6461949B1 (en) | 2002-10-08 |
Family
ID=25230434
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/820,305 Expired - Lifetime US6461949B1 (en) | 2001-03-29 | 2001-03-29 | Method for fabricating a nitride read-only-memory (NROM) |
Country Status (1)
Country | Link |
---|---|
US (1) | US6461949B1 (en) |
Cited By (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020105591A1 (en) * | 2001-02-06 | 2002-08-08 | Olympus Optical Co., Ltd. | Solid-state image pickup apparatus and fabricating method thereof |
US20030235075A1 (en) * | 2002-06-21 | 2003-12-25 | Micron Technology, Inc. | Vertical NROM having a storage density of 1bit per 1F2 |
US20040070049A1 (en) * | 2001-11-14 | 2004-04-15 | Anderson David K. | Fuse structure and method to form the same |
US20040130934A1 (en) * | 2002-06-21 | 2004-07-08 | Micron Technology, Inc. | NROM memory cell, memory array, related devices and methods |
US6830963B1 (en) | 2003-10-09 | 2004-12-14 | Micron Technology, Inc. | Fully depleted silicon-on-insulator CMOS logic |
US20050030794A1 (en) * | 2003-08-07 | 2005-02-10 | Micron Technology, Inc. | Method for erasing an NROM cell |
US20050030792A1 (en) * | 2003-08-07 | 2005-02-10 | Micron Technology, Inc. | Method for programming and erasing an nrom cell |
US6878991B1 (en) | 2004-01-30 | 2005-04-12 | Micron Technology, Inc. | Vertical device 4F2 EEPROM memory |
US20050106811A1 (en) * | 2003-11-17 | 2005-05-19 | Micron Technology, Inc. | NROM flash memory devices on ultrathin silicon |
US20050105341A1 (en) * | 2003-11-04 | 2005-05-19 | Micron Technology, Inc. | NROM flash memory with self-aligned structural charge separation |
US20050128804A1 (en) * | 2003-12-16 | 2005-06-16 | Micron Technology, Inc. | Multi-state NROM device |
US20050140462A1 (en) * | 2003-05-22 | 2005-06-30 | Micron Technology, Inc. | High permeability layered magnetic films to reduce noise in high speed interconnection |
US20050173755A1 (en) * | 2004-02-10 | 2005-08-11 | Micron Technology, Inc. | NROM flash memory with a high-permittivity gate dielectric |
US20050174847A1 (en) * | 2004-02-10 | 2005-08-11 | Micron Technology, Inc. | Nrom flash memory cell with integrated dram |
US20050185466A1 (en) * | 2004-02-24 | 2005-08-25 | Micron Technology, Inc. | Multi-state memory cell with asymmetric charge trapping |
US20050205969A1 (en) * | 2004-03-19 | 2005-09-22 | Sharp Laboratories Of America, Inc. | Charge trap non-volatile memory structure for 2 bits per transistor |
US20050212033A1 (en) * | 2004-03-24 | 2005-09-29 | Micron Technology, Inc. | Memory device with high dielectric constant gate dielectrics and metal floating gates |
US20050247972A1 (en) * | 2004-05-06 | 2005-11-10 | Micron Technology, Inc. | Ballistic direct injection NROM cell on strained silicon structures |
US20050253186A1 (en) * | 2003-09-05 | 2005-11-17 | Micron Technology, Inc. | Trench corner effect bidirectional flash memory cell |
US20050277243A1 (en) * | 2003-12-18 | 2005-12-15 | Micron Technology, Inc. | Flash memory having a high-permittivity tunnel dielectric |
US20060128104A1 (en) * | 2003-12-16 | 2006-06-15 | Micron Technology, Inc. | NROM memory cell, memory array, related devices and methods |
US7670646B2 (en) | 2002-05-02 | 2010-03-02 | Micron Technology, Inc. | Methods for atomic-layer deposition |
US7719046B2 (en) | 2003-07-01 | 2010-05-18 | Micron Technology, Inc. | Apparatus and method for trench transistor memory having different gate dielectric thickness |
US8154066B2 (en) | 2004-08-31 | 2012-04-10 | Micron Technology, Inc. | Titanium aluminum oxide films |
US8501563B2 (en) | 2005-07-20 | 2013-08-06 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
CN107591449A (en) * | 2016-07-08 | 2018-01-16 | 瑞萨电子株式会社 | Semiconductor devices and its manufacture method |
US11587863B2 (en) * | 2018-07-27 | 2023-02-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method of forming semiconductor package |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100438403B1 (en) * | 2001-09-05 | 2004-07-02 | 동부전자 주식회사 | Method for manufacturing a flat cell memory device |
TW544866B (en) * | 2002-05-06 | 2003-08-01 | Macronix Int Co Ltd | Fabrication method for a mask read only memory device |
CN100389491C (en) * | 2002-11-12 | 2008-05-21 | 旺宏电子股份有限公司 | Method for fabricating silicon nitride ROM |
US6906959B2 (en) * | 2002-11-27 | 2005-06-14 | Advanced Micro Devices, Inc. | Method and system for erasing a nitride memory device |
KR100482752B1 (en) * | 2002-12-26 | 2005-04-14 | 주식회사 하이닉스반도체 | Method of manufacturing of non-volatile memory device |
US6979857B2 (en) | 2003-07-01 | 2005-12-27 | Micron Technology, Inc. | Apparatus and method for split gate NROM memory |
US6808991B1 (en) * | 2003-11-19 | 2004-10-26 | Macronix International Co., Ltd. | Method for forming twin bit cell flash memory |
US7241654B2 (en) | 2003-12-17 | 2007-07-10 | Micron Technology, Inc. | Vertical NROM NAND flash memory array |
US7075146B2 (en) | 2004-02-24 | 2006-07-11 | Micron Technology, Inc. | 4F2 EEPROM NROM memory arrays with vertical devices |
US20080277766A1 (en) * | 2004-07-20 | 2008-11-13 | Robin Harold Cantor | Polymer membranes for microcalorimeter devices |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR960004462B1 (en) * | 1992-08-07 | 1996-04-06 | 삼성전자주식회사 | Process for producing memory capacitor in semiconductor device |
US6251761B1 (en) * | 1998-11-24 | 2001-06-26 | Texas Instruments Incorporated | Process for polycrystalline silicon gates and high-K dielectric compatibility |
-
2001
- 2001-03-29 US US09/820,305 patent/US6461949B1/en not_active Expired - Lifetime
Cited By (125)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020105591A1 (en) * | 2001-02-06 | 2002-08-08 | Olympus Optical Co., Ltd. | Solid-state image pickup apparatus and fabricating method thereof |
US6924185B2 (en) * | 2001-11-14 | 2005-08-02 | International Business Machines Corporation | Fuse structure and method to form the same |
US20040070049A1 (en) * | 2001-11-14 | 2004-04-15 | Anderson David K. | Fuse structure and method to form the same |
US7670646B2 (en) | 2002-05-02 | 2010-03-02 | Micron Technology, Inc. | Methods for atomic-layer deposition |
US6853587B2 (en) | 2002-06-21 | 2005-02-08 | Micron Technology, Inc. | Vertical NROM having a storage density of 1 bit per 1F2 |
US20040066672A1 (en) * | 2002-06-21 | 2004-04-08 | Micron Technology, Inc. | Vertical NROM having a storage density of 1 bit per IF2 |
US7230848B2 (en) | 2002-06-21 | 2007-06-12 | Micron Technology, Inc. | Vertical NROM having a storage density of 1 bit per 1F2 |
US6842370B2 (en) | 2002-06-21 | 2005-01-11 | Micron Technology, Inc. | Vertical NROM having a storage density of 1 bit per 1F2 |
US20040130934A1 (en) * | 2002-06-21 | 2004-07-08 | Micron Technology, Inc. | NROM memory cell, memory array, related devices and methods |
US20090010075A9 (en) * | 2002-06-21 | 2009-01-08 | Micron Technologies, Inc. | NROM memory cell, memory array, related devices and methods |
US20090072303A9 (en) * | 2002-06-21 | 2009-03-19 | Micron Technology, Inc. | Nrom memory cell, memory array, related devices and methods |
US20040202032A1 (en) * | 2002-06-21 | 2004-10-14 | Micron Technology, Inc. | Vertical NROM having a storage density of 1 bit per 1F2 |
US8441056B2 (en) | 2002-06-21 | 2013-05-14 | Micron Technology, Inc. | NROM memory cell, memory array, related devices and methods |
US20030235075A1 (en) * | 2002-06-21 | 2003-12-25 | Micron Technology, Inc. | Vertical NROM having a storage density of 1bit per 1F2 |
US20060124998A1 (en) * | 2002-06-21 | 2006-06-15 | Micron Technology, Inc. | NROM memory cell, memory array, related devices and methods |
US20060126398A1 (en) * | 2002-06-21 | 2006-06-15 | Micron Technologies, Inc. | NROM memory cell, memory array, related devices and methods |
US6906953B2 (en) | 2002-06-21 | 2005-06-14 | Micron Technology, Inc. | Vertical NROM having a storage density of 1 bit per 1F2 |
US20050255647A1 (en) * | 2002-06-21 | 2005-11-17 | Micron Technology, Inc. | Vertical NROM having a storage density of 1 bit per 1F2 |
US20050140462A1 (en) * | 2003-05-22 | 2005-06-30 | Micron Technology, Inc. | High permeability layered magnetic films to reduce noise in high speed interconnection |
US7719046B2 (en) | 2003-07-01 | 2010-05-18 | Micron Technology, Inc. | Apparatus and method for trench transistor memory having different gate dielectric thickness |
US20050141278A1 (en) * | 2003-08-07 | 2005-06-30 | Micron Technology, Inc. | Method for programming and erasing an NROM cell |
US7277321B2 (en) | 2003-08-07 | 2007-10-02 | Micron Technology, Inc. | Method for programming and erasing an NROM cell |
US7272045B2 (en) | 2003-08-07 | 2007-09-18 | Micron Technology, Inc. | Method for programming and erasing an NROM cell |
US20050174855A1 (en) * | 2003-08-07 | 2005-08-11 | Micron Technology, Inc. | Method for erasing an NROM cell |
US7227787B2 (en) | 2003-08-07 | 2007-06-05 | Micron Technology, Inc. | Method for erasing an NROM cell |
US7986555B2 (en) | 2003-08-07 | 2011-07-26 | Micron Technology, Inc. | Method for programming and erasing an NROM cell |
US20070070700A1 (en) * | 2003-08-07 | 2007-03-29 | Micron Technology, Inc. | Method for programming and erasing an NROM cell |
US20070064466A1 (en) * | 2003-08-07 | 2007-03-22 | Micron Technology, Inc. | Method for programming and erasing an NROM cell |
US20050030794A1 (en) * | 2003-08-07 | 2005-02-10 | Micron Technology, Inc. | Method for erasing an NROM cell |
US20050030792A1 (en) * | 2003-08-07 | 2005-02-10 | Micron Technology, Inc. | Method for programming and erasing an nrom cell |
US6873550B2 (en) | 2003-08-07 | 2005-03-29 | Micron Technology, Inc. | Method for programming and erasing an NROM cell |
US7088619B2 (en) | 2003-08-07 | 2006-08-08 | Micron Technology, Inc. | Method for programming and erasing an NROM cell |
US7085170B2 (en) | 2003-08-07 | 2006-08-01 | Micron Technology, Ind. | Method for erasing an NROM cell |
US7075832B2 (en) | 2003-08-07 | 2006-07-11 | Micron Technology, Inc. | Method for erasing an NROM cell |
US7075831B2 (en) | 2003-08-07 | 2006-07-11 | Micron Technology, Inc. | Method for erasing an NROM cell |
US7639530B2 (en) | 2003-08-07 | 2009-12-29 | Micron Technology, Inc. | Method for programming and erasing an NROM cell |
US20060133152A1 (en) * | 2003-08-07 | 2006-06-22 | Micron Technology, Inc. | Method for programming and erasing an NROM cell |
US20100067307A1 (en) * | 2003-08-07 | 2010-03-18 | Micron Technology, Inc. | Method for programming and erasing an nrom cell |
US7161217B2 (en) | 2003-09-05 | 2007-01-09 | Micron Technology, Inc. | Trench corner effect bidirectional flash memory cell |
US7535054B2 (en) | 2003-09-05 | 2009-05-19 | Micron Technology, Inc. | Trench corner effect bidirectional flash memory cell |
US7283394B2 (en) | 2003-09-05 | 2007-10-16 | Micron Technology, Inc. | Trench corner effect bidirectional flash memory cell |
US20050258480A1 (en) * | 2003-09-05 | 2005-11-24 | Micron Technology, Inc. | Trench corner effect bidirectional flash memory cell |
US6977412B2 (en) | 2003-09-05 | 2005-12-20 | Micron Technology, Inc. | Trench corner effect bidirectional flash memory cell |
US20050255638A1 (en) * | 2003-09-05 | 2005-11-17 | Micron Technology, Inc. | Trench corner effect bidirectional flash memory cell |
US7285821B2 (en) | 2003-09-05 | 2007-10-23 | Micron Technology, Inc. | Trench corner effect bidirectional flash memory cell |
US20050269625A1 (en) * | 2003-09-05 | 2005-12-08 | Micron Technology, Inc. | Trench corner effect bidirectional flash memory cell |
US20050253186A1 (en) * | 2003-09-05 | 2005-11-17 | Micron Technology, Inc. | Trench corner effect bidirectional flash memory cell |
US7329920B2 (en) | 2003-09-05 | 2008-02-12 | Micron Technology, Inc. | Trench corner effect bidirectional flash memory cell |
US7078770B2 (en) | 2003-10-09 | 2006-07-18 | Micron Technology, Inc. | Fully depleted silicon-on-insulator CMOS logic |
US7973370B2 (en) | 2003-10-09 | 2011-07-05 | Micron Technology, Inc. | Fully depleted silicon-on-insulator CMOS logic |
US20050077564A1 (en) * | 2003-10-09 | 2005-04-14 | Micron Technology, Inc. | Fully depleted silicon-on-insulator CMOS logic |
US20110204431A1 (en) * | 2003-10-09 | 2011-08-25 | Micron Technology, Inc. | Fully depleted silicon-on-insulator cmos logic |
US6830963B1 (en) | 2003-10-09 | 2004-12-14 | Micron Technology, Inc. | Fully depleted silicon-on-insulator CMOS logic |
US8174081B2 (en) | 2003-10-09 | 2012-05-08 | Micron Technology, Inc. | Fully depleted silicon-on-insulator CMOS logic |
US20050105341A1 (en) * | 2003-11-04 | 2005-05-19 | Micron Technology, Inc. | NROM flash memory with self-aligned structural charge separation |
US7480186B2 (en) | 2003-11-04 | 2009-01-20 | Micron Technology, Inc. | NROM flash memory with self-aligned structural charge separation |
US7184315B2 (en) | 2003-11-04 | 2007-02-27 | Micron Technology, Inc. | NROM flash memory with self-aligned structural charge separation |
US20070109871A1 (en) * | 2003-11-04 | 2007-05-17 | Micron Technology, Inc. | NROM flash memory with self-aligned structural charge separation |
US7202523B2 (en) | 2003-11-17 | 2007-04-10 | Micron Technology, Inc. | NROM flash memory devices on ultrathin silicon |
US20050280089A1 (en) * | 2003-11-17 | 2005-12-22 | Micron Technology, Inc. | NROM flash memory devices on ultrathin silicon |
US7276413B2 (en) | 2003-11-17 | 2007-10-02 | Micron Technology, Inc. | NROM flash memory devices on ultrathin silicon |
US20100270610A1 (en) * | 2003-11-17 | 2010-10-28 | Micron Technology, Inc. | Nrom flash memory devices on ultrathin silicon |
US8183625B2 (en) | 2003-11-17 | 2012-05-22 | Micron Technology, Inc. | NROM flash memory devices on ultrathin silicon |
US7915669B2 (en) | 2003-11-17 | 2011-03-29 | Micron Technology, Inc. | NROM flash memory devices on ultrathin silicon |
US20080203467A1 (en) * | 2003-11-17 | 2008-08-28 | Micron Technology, Inc. | Nrom flash memory devices on ultrathin silicon |
US7276762B2 (en) | 2003-11-17 | 2007-10-02 | Micron Technology, Inc. | NROM flash memory devices on ultrathin silicon |
US7768058B2 (en) | 2003-11-17 | 2010-08-03 | Micron Technology, Inc. | NROM flash memory devices on ultrathin silicon |
US20050280094A1 (en) * | 2003-11-17 | 2005-12-22 | Micron Technology, Inc. | NROM flash memory devices on ultrathin silicon |
US20110163321A1 (en) * | 2003-11-17 | 2011-07-07 | Micron Technology, Inc. | Nrom flash memory devices on ultrathin silicon |
US20050282334A1 (en) * | 2003-11-17 | 2005-12-22 | Micron Technology, Inc. | NROM flash memory devices on ultrathin silicon |
US20070170496A1 (en) * | 2003-11-17 | 2007-07-26 | Micron Technology, Inc. | Nrom flash memory devices on ultrathin silicon |
US20070166927A1 (en) * | 2003-11-17 | 2007-07-19 | Micron Technology, Inc. | Nrom flash memory devices on ultrathin silicon |
US20050106811A1 (en) * | 2003-11-17 | 2005-05-19 | Micron Technology, Inc. | NROM flash memory devices on ultrathin silicon |
US7244987B2 (en) | 2003-11-17 | 2007-07-17 | Micron Technology, Inc. | NROM flash memory devices on ultrathin silicon |
US20060128103A1 (en) * | 2003-12-16 | 2006-06-15 | Micron Technology, Inc. | NROM memory cell, memory array, related devices and methods |
US20060124992A1 (en) * | 2003-12-16 | 2006-06-15 | Micron Technology, Inc. | NROM memory cell, memory array, related devices and methods |
US20060124967A1 (en) * | 2003-12-16 | 2006-06-15 | Micron Technology, Inc. | NROM memory cell, memory array, related devices and methods |
US20060128104A1 (en) * | 2003-12-16 | 2006-06-15 | Micron Technology, Inc. | NROM memory cell, memory array, related devices and methods |
US20050128804A1 (en) * | 2003-12-16 | 2005-06-16 | Micron Technology, Inc. | Multi-state NROM device |
US7750389B2 (en) | 2003-12-16 | 2010-07-06 | Micron Technology, Inc. | NROM memory cell, memory array, related devices and methods |
US20060152978A1 (en) * | 2003-12-16 | 2006-07-13 | Micron Technology, Inc. | Multi-state NROM device |
US20060166443A1 (en) * | 2003-12-16 | 2006-07-27 | Micron Technology, Inc. | Multi-state NROM device |
US7528037B2 (en) | 2003-12-18 | 2009-05-05 | Micron Technology, Inc. | Flash memory having a high-permittivity tunnel dielectric |
US7157769B2 (en) | 2003-12-18 | 2007-01-02 | Micron Technology, Inc. | Flash memory having a high-permittivity tunnel dielectric |
US20050277243A1 (en) * | 2003-12-18 | 2005-12-15 | Micron Technology, Inc. | Flash memory having a high-permittivity tunnel dielectric |
US6878991B1 (en) | 2004-01-30 | 2005-04-12 | Micron Technology, Inc. | Vertical device 4F2 EEPROM memory |
US20050240867A1 (en) * | 2004-02-10 | 2005-10-27 | Micron Technology, Inc. | NROM flash memory cell with integrated DRAM |
US6952366B2 (en) | 2004-02-10 | 2005-10-04 | Micron Technology, Inc. | NROM flash memory cell with integrated DRAM |
US20050173755A1 (en) * | 2004-02-10 | 2005-08-11 | Micron Technology, Inc. | NROM flash memory with a high-permittivity gate dielectric |
US7479428B2 (en) | 2004-02-10 | 2009-01-20 | Leonard Forbes | NROM flash memory with a high-permittivity gate dielectric |
US20050174847A1 (en) * | 2004-02-10 | 2005-08-11 | Micron Technology, Inc. | Nrom flash memory cell with integrated dram |
US7319613B2 (en) | 2004-02-10 | 2008-01-15 | Micron Technology, Inc. | NROM flash memory cell with integrated DRAM |
US20060019453A1 (en) * | 2004-02-10 | 2006-01-26 | Micron Technology, Inc. | NROM flash memory with a high-permittivity gate dielectric |
US7072213B2 (en) | 2004-02-10 | 2006-07-04 | Micron Technology, Inc. | NROM flash memory cell with integrated DRAM |
US20050275011A1 (en) * | 2004-02-10 | 2005-12-15 | Micron Technology, Inc. | NROM flash memory with a high-permittivity gate dielectric |
US7221018B2 (en) | 2004-02-10 | 2007-05-22 | Micron Technology, Inc. | NROM flash memory with a high-permittivity gate dielectric |
US7577027B2 (en) | 2004-02-24 | 2009-08-18 | Micron Technology, Inc. | Multi-state memory cell with asymmetric charge trapping |
US7616482B2 (en) | 2004-02-24 | 2009-11-10 | Micron Technology, Inc. | Multi-state memory cell with asymmetric charge trapping |
US7072217B2 (en) | 2004-02-24 | 2006-07-04 | Micron Technology, Inc. | Multi-state memory cell with asymmetric charge trapping |
US20100039869A1 (en) * | 2004-02-24 | 2010-02-18 | Micron Technology, Inc. | Multi-state memory cell with asymmetric charge trapping |
US20050185466A1 (en) * | 2004-02-24 | 2005-08-25 | Micron Technology, Inc. | Multi-state memory cell with asymmetric charge trapping |
US20060203554A1 (en) * | 2004-02-24 | 2006-09-14 | Micron Technology, Inc. | Multi-state memory cell with asymmetric charge trapping |
US7911837B2 (en) | 2004-02-24 | 2011-03-22 | Micron Technology, Inc. | Multi-state memory cell with asymmetric charge trapping |
US20060203555A1 (en) * | 2004-02-24 | 2006-09-14 | Micron Technology, Inc. | Multi-state memory cell with asymmetric charge trapping |
US20050205969A1 (en) * | 2004-03-19 | 2005-09-22 | Sharp Laboratories Of America, Inc. | Charge trap non-volatile memory structure for 2 bits per transistor |
US7102191B2 (en) | 2004-03-24 | 2006-09-05 | Micron Technologies, Inc. | Memory device with high dielectric constant gate dielectrics and metal floating gates |
US20060237775A1 (en) * | 2004-03-24 | 2006-10-26 | Micron Technology, Inc. | Memory device with high dielectric constant gate dielectrics and metal floating gates |
US7268031B2 (en) | 2004-03-24 | 2007-09-11 | Micron Technology, Inc. | Memory device with high dielectric constant gate dielectrics and metal floating gates |
US20050280048A1 (en) * | 2004-03-24 | 2005-12-22 | Micron Technology, Inc. | Memory device with high dielectric constant gate dielectrics and metal floating gates |
US8076714B2 (en) | 2004-03-24 | 2011-12-13 | Micron Technology, Inc. | Memory device with high dielectric constant gate dielectrics and metal floating gates |
US20090294830A1 (en) * | 2004-03-24 | 2009-12-03 | Micron Technology, Inc. | Memory device with high dielectric constant gate dielectrics and metal floating gates |
US7586144B2 (en) | 2004-03-24 | 2009-09-08 | Micron Technology, Inc. | Memory device with high dielectric constant gate dielectrics and metal floating gates |
US20050212033A1 (en) * | 2004-03-24 | 2005-09-29 | Micron Technology, Inc. | Memory device with high dielectric constant gate dielectrics and metal floating gates |
US7550339B2 (en) | 2004-03-24 | 2009-06-23 | Micron Technology, Inc. | Memory device with high dielectric constant gate dielectrics and metal floating gates |
US7274068B2 (en) | 2004-05-06 | 2007-09-25 | Micron Technology, Inc. | Ballistic direct injection NROM cell on strained silicon structures |
US7683424B2 (en) | 2004-05-06 | 2010-03-23 | Micron Technology, Inc. | Ballistic direct injection NROM cell on strained silicon structures |
US20060214220A1 (en) * | 2004-05-06 | 2006-09-28 | Micron Technology, Inc. | Ballistic direct injection NROM cell on strained silicon structures |
US7859046B2 (en) | 2004-05-06 | 2010-12-28 | Micron Technology, Inc. | Ballistic direct injection NROM cell on strained silicon structures |
US20050247972A1 (en) * | 2004-05-06 | 2005-11-10 | Micron Technology, Inc. | Ballistic direct injection NROM cell on strained silicon structures |
US8154066B2 (en) | 2004-08-31 | 2012-04-10 | Micron Technology, Inc. | Titanium aluminum oxide films |
US8541276B2 (en) | 2004-08-31 | 2013-09-24 | Micron Technology, Inc. | Methods of forming an insulating metal oxide |
US8501563B2 (en) | 2005-07-20 | 2013-08-06 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
US8921914B2 (en) | 2005-07-20 | 2014-12-30 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
CN107591449A (en) * | 2016-07-08 | 2018-01-16 | 瑞萨电子株式会社 | Semiconductor devices and its manufacture method |
US11587863B2 (en) * | 2018-07-27 | 2023-02-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method of forming semiconductor package |
Also Published As
Publication number | Publication date |
---|---|
US6461949B1 (en) | 2002-10-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6461949B1 (en) | Method for fabricating a nitride read-only-memory (NROM) | |
US7432546B2 (en) | Apparatus having a memory device with floating gate layer grain boundaries with oxidized portions | |
US6559007B1 (en) | Method for forming flash memory device having a tunnel dielectric comprising nitrided oxide | |
US6380033B1 (en) | Process to improve read disturb for NAND flash memory devices | |
US6235586B1 (en) | Thin floating gate and conductive select gate in situ doped amorphous silicon material for NAND type flash memory device applications | |
US8481387B2 (en) | Method of forming an insulation structure and method of manufacturing a semiconductor device using the same | |
US20220278214A1 (en) | Semiconductor devices with liners and related methods | |
KR101217260B1 (en) | Method for fabricating a memory cell structure having nitride layer with reduced charge loss | |
KR100695820B1 (en) | Non-volatile semiconductor device and method of manufcaturing the same | |
KR100587670B1 (en) | Method for forming dielectric layer for use in non-volatile memory cell | |
US6548425B2 (en) | Method for fabricating an ONO layer of an NROM | |
US20020168869A1 (en) | Method for fabricating an ONO layer | |
US7829936B2 (en) | Split charge storage node inner spacer process | |
US6284602B1 (en) | Process to reduce post cycling program VT dispersion for NAND flash memory devices | |
US7132328B2 (en) | Method of manufacturing flash memory device | |
US6620705B1 (en) | Nitriding pretreatment of ONO nitride for oxide deposition | |
US6709927B1 (en) | Process for treating ONO dielectric film of a floating gate memory cell | |
JP2000208645A (en) | Forming method for silicon group dielectric film and manufacture of nonvolatile semiconductor storage device | |
TWI226107B (en) | Method of manufacturing nitride read only memory | |
KR100274352B1 (en) | Method of manufacturing a flash memory cell | |
US6858496B1 (en) | Oxidizing pretreatment of ONO layer for flash memory | |
KR20030040733A (en) | Method for forming dielectric layer in semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MACRONIX INTERNATIONAL CO. LTD., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHANG, KENT KUOHUA;CHEN, CHIA-HSING;REEL/FRAME:011659/0670 Effective date: 20010302 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |