CN100389491C

CN100389491C - Method for fabricating silicon nitride ROM

Info

Publication number: CN100389491C
Application number: CNB021493944A
Authority: CN
Inventors: 刘承杰; 熊黛良; 陈家兴
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2002-11-12
Filing date: 2002-11-12
Publication date: 2008-05-21
Anticipated expiration: 2022-11-12
Also published as: CN1501478A

Abstract

The present invention relates to a method for manufacturing a silicon nitride ROM, which can prevent the occurrence of a state of excess etching during the process period. The method comprises the following steps: a silicon oxide/silicon nitride/silicon oxide stacking layer is firstly formed on a substrate, and then, a protective layer is formed on the stacking layer; afterwards, an etching process is carried out to pattern the protective layer and the stacking layer, and part of the substrate is exposed out; subsequently, a cleaning process is carried out to remove the protective layer, and an ion implantation process is implemented to expose an adulterating region formed in the substrate; then, an insulator is formed on the adulterating region, and a character line is formed on the substrate.

Description

Make the method for silicon nitride ROM

Technical field

The invention relates to a kind of manufacturing read-only memory method of (read only memory is called for short ROM), and be particularly to the method for a kind of manufacturing silicon nitride ROM (nitride ROM).

Background technology

The practice of silicon nitride ROM is to form one deck earlier to catch layer (trapping layer) in substrate, catching layer is silicon oxide/silicon nitride/silicon oxide (oxide-nitride-oxide, be called for short ONO) laminated construction that stack layer (stacked layer) is constituted, be called silicon nitride ROM with this kind material as the read-only memory of catching layer.Then, etching defines this silicon oxide/silicon nitride/silicon oxide stack layer, again an ion implantation technology is carried out in substrate, to form doped region in substrate.Then, on doped region, form layer of oxide layer, on the silicon oxide/silicon nitride/silicon oxide stack layer, form the polysilicon character line again.

And when being known in etching definition silicon oxide/silicon nitride/silicon oxide stack layer, normally utilize a photoresist layer as etch mask, again the silicon oxide/silicon nitride/silicon oxide stack layer is carried out etching.Yet, as shown in Figure 1, when etch process proceeds to back segment, be positioned at the silicon oxide/silicon nitride/silicon oxide stack layer 108 top layers in the substrate 100 top oxide layer (top oxide layer) 106 Chang Yinwei its be lower than the etching selectivity (etching selectivity) of silicon nitride, make top oxide layer 106 during etch process, be caused its corner to lose (loss) by over etching (over-etch), even make top oxide layer 106 unfilled corners, and then 110 electrical problem takes place in the unfilled corner position.

At present also proposing a kind of method that solves above-mentioned over etching, mainly is to increase the top thickness of oxide layer, to prevent because of oxide layer corner, top is etched the unfilled corner problem that is caused.If but, the trend of the miniaturization of components of running counter to development is arranged probably again with the thickening of top oxide layer.

Summary of the invention

Therefore, the purpose of this invention is to provide a kind of method of making silicon nitride ROM, to prevent having the situation of over etching to take place during the technology.

A further object of the present invention provides a kind of method of making silicon nitride ROM, can reduce the loss in the oxide layer corner, top of silicon oxide/silicon nitride/silicon oxide stack layer.

Another object of the present invention provides a kind of method of making silicon nitride ROM, can prevent because of over etching, and by the electrical problem of over etching place generation.

Another purpose of the present invention provides a kind of method of making silicon nitride ROM, can prevent because of oxide layer corner, top is etched the unfilled corner problem that is caused simultaneously under the trend of miniaturization of components development.

According to above-mentioned and other purpose; the present invention proposes a kind of method of making silicon nitride ROM; be included in and form silicon oxide/silicon nitride/silicon oxide stack layer (ONOstacked layer) in the substrate earlier; forming one deck again on this stack layer compares less than 1 with the selection of oxide layer; and thickness is less than the protective layer (protective layer) of 50 dusts, and its material for example is a silicon nitride.Then, carry out a lithography technology,, and expose the part substrate with patterning protective layer and stack layer.Then, carry out a cleaning protective layer is removed, implement an ion implantation technology again, in the substrate that exposes, to form doped region as embedded type bit line (buried bit line).Then, on doped region, form an insulator, in substrate, form a polysilicon layer again as character line (word line).

The present invention proposes a kind of method of making silicon nitride ROM in addition; the difference of the method maximum of its technology and the invention described above is after carrying out etch process; keep the protective layer that is positioned on the silicon oxide/silicon nitride/silicon oxide stack layer; wherein the material of protective layer is a silicon nitride for example, and its thickness is less than 50 dusts.

The present invention is because form protective layer on the silicon oxide/silicon nitride/silicon oxide stack layer before etching, and protective layer compares less than 1 with the selection of oxide layer.Therefore, can reduce the loss problem in top oxide layer corner during etch process of silicon oxide/silicon nitride/silicon oxide stack layer, so avoid known because of the top oxide layer by electrical problem that over etching took place.

Description of drawings

Fig. 1 is the generalized section of the top oxide layer unfilled corner of known a kind of silicon nitride ROM; And

Fig. 2 A to Fig. 2 E is the manufacturing process profile according to the silicon nitride ROM of a preferred embodiment of the present invention.

100,200: substrate

106,206: the top oxide layer

108,208: the silicon oxide/silicon nitride/silicon oxide stack layer

110: the unfilled corner position

202: bottom oxide

204: silicon nitride layer

210: protective layer

212: doped region

214: insulator

216: character line

Embodiment

Fig. 2 A to Fig. 2 E is the manufacturing process profile of the silicon nitride ROM (nitride read only memory) according to a preferred embodiment of the present invention.

Please refer to Fig. 2 A, in substrate 200, form silicon oxide/silicon nitride/silicon oxide (oxide-nitride-oxide, be called for short ONO) stack layer 208 (stacked layer), the nesting structural embedded control that it constituted is made up of one deck bottom oxide (bottom oxide layer) 202, one deck silicon nitride layer 204 and one deck top oxide layer (top oxide layer) 206, and the thickness of each layer to be respectively bottom oxide 202 be about between the 50-100 dust, silicon nitride layer 204 between the 55-80 dust and top oxide layer 206 between the 70-120 dust.

Then, please refer to Fig. 2 B, form layer protective layer (protective layer) 210 on silicon oxide/silicon nitride/silicon oxide stack layer 208, wherein protective layer 210 compares less than 1 with the selection of silica, and its material for example is a silicon nitride, and thickness is approximately less than 50 dusts.

Then, please refer to Fig. 2 C, carry out a lithography technology,, and expose part substrate 200 with patterning protective layer 210 and stack layer 208.In addition, also can be when patterning stack layer 208, not etching is near the bottom oxide 202 of substrate, so as to prevent the follow-up channelling effect that is taken place (channeling effect) when carrying out ion implantation technology.

Subsequently; please refer to Fig. 2 D; carry out a cleaning protective layer 210 (asking for an interview Fig. 2 C) is removed, implement an ion implantation technology again, to form doped region 212 in the substrate between patterning stack layer 208 200 as embedded type bit line (buried bit line).In addition, protective layer 210 (asking for an interview Fig. 2 C) also can keep and omit above-mentioned cleaning.Afterwards, if previous step keeps near the bottom oxide 202 of substrate, then need remove the bottom oxide 202 that exposes.

Then, please refer to Fig. 2 E, form an insulator (insulator) 214 in doped region 212 surfaces, its material is a silica for example.Subsequently, form one deck conductor layer in substrate 200, and defined, with the character line (wordline) 216 as silicon nitride ROM, its material can be polysilicon (polysilicon).

Because:

1. the present invention forms protective layer before by etching on the silicon oxide/silicon nitride/silicon oxide stack layer, and the selection of protective layer and oxide layer is than less than 1.Therefore, can reduce the loss problem in top oxide layer corner during etch process of silicon oxide/silicon nitride/silicon oxide stack layer.

2. the present invention is owing to reduce the loss problem in top oxide layer corner during etch process of silicon oxide/silicon nitride/silicon oxide stack layer, and avoid known because of the top oxide layer by electrical problem that over etching took place.

3. the present invention is because of the existence of protective layer, so need can not prevent because of oxide layer corner, top is etched the unfilled corner problem that is caused simultaneously under the trend of miniaturization of components development via thickening top oxide layer.

Claims

1. a method of making silicon nitride ROM is characterized in that, this method comprises:

Form silicon monoxide/nitrogenize silicon/oxidative silicon stack layer in a substrate, this silicon oxide/silicon nitride/silicon oxide stack layer has a bottom oxide, a silicon nitride layer and a top oxide layer;

On this silicon oxide/silicon nitride/silicon oxide stack layer, form a protective layer, and this protective layer compares less than 1 with the selection of silica, and the thickness of this protective layer is less than 50 dusts;

Carry out a lithography technology, with this protective layer of patterning and this silicon oxide/silicon nitride/silicon oxide stack layer; And

After this lithography technology, carry out a cleaning to remove this protective layer.

2. the method for manufacturing silicon nitride ROM as claimed in claim 1 is characterized in that, this method more comprises:

Implement an ion implantation technology, to form a doped region in this substrate between this silicon oxide/silicon nitride/silicon oxide stack layer of patterning;

Form an insulator in this doped region surface; And

In this substrate, form a character line.

3. the method for manufacturing silicon nitride ROM as claimed in claim 2 is characterized in that, the material of this insulator comprises silica.

4. the method for manufacturing silicon nitride ROM as claimed in claim 2 is characterized in that, the material of this character line comprises polysilicon.

5. the method for manufacturing silicon nitride ROM as claimed in claim 1 is characterized in that, the thickness of this bottom oxide is between the 50-100 dust.

6. the method for manufacturing silicon nitride ROM as claimed in claim 1 is characterized in that, the thickness of this silicon nitride layer is between the 55-80 dust.

7. the method for manufacturing silicon nitride ROM as claimed in claim 1 is characterized in that, this top thickness of oxide layer is between the 70-120 dust.

8. the method for manufacturing silicon nitride ROM as claimed in claim 1 is characterized in that, the material of this protective layer comprises silicon nitride.

9. the method for manufacturing silicon nitride ROM as claimed in claim 1 is characterized in that, the step of carrying out this lithography technology comprises this silicon oxide/silicon nitride/silicon oxide stack layer of patterning, to expose this bottom oxide of part.

10. a method of making silicon nitride ROM is characterized in that, this method comprises:

Form silicon monoxide/nitrogenize silicon/oxidative silicon stack layer in a substrate, wherein this silicon oxide/silicon nitride/silicon oxide stack layer has a bottom oxide, a silicon nitride layer and a top oxide layer;

On this silicon oxide/silicon nitride/silicon oxide stack layer, form a protective layer, and the selection of this protective layer and silica than less than 1 and thickness less than 50 dusts;

Carry out a lithography technology,, expose this bottom oxide of part with this protective layer of patterning and this silicon oxide/silicon nitride/silicon oxide stack layer;

After this lithography technology, carry out a cleaning to remove this protective layer;

This bottom oxide that removal exposes;

Form an insulator in this doped region surface; And

In this substrate, form a character line.

11. the method for manufacturing silicon nitride ROM as claimed in claim 10 is characterized in that, the thickness of this bottom oxide is between the 50-100 dust.

12. the method for manufacturing silicon nitride ROM as claimed in claim 10 is characterized in that, the thickness of this silicon nitride layer is between the 55-80 dust.

13. the method for manufacturing silicon nitride ROM as claimed in claim 10 is characterized in that, this top thickness of oxide layer is between the 70-120 dust.

14. the method for manufacturing silicon nitride ROM as claimed in claim 10 is characterized in that, the material of this protective layer comprises silicon nitride.

15. the method for manufacturing silicon nitride ROM as claimed in claim 10 is characterized in that, the material of this insulator comprises silica.

16. the method for manufacturing silicon nitride ROM as claimed in claim 10 is characterized in that, the material of this character line comprises polysilicon.