CN115701214A

CN115701214A - Method for manufacturing bit line structure and method for manufacturing data storage array

Info

Publication number: CN115701214A
Application number: CN202110855234.4A
Authority: CN
Inventors: 孙正庆; 赵行乐; 李昇; 金星
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-07-28
Filing date: 2021-07-28
Publication date: 2023-02-07

Abstract

The present application provides a method for manufacturing a bit line structure, comprising: providing a substrate comprising a first region and a second region; forming a metal layer, a first mask stack and a second mask stack on the substrate; patterning the second mask stack to form a first mandrel; depositing a first medium layer on the first mandrel in a conformal manner, etching the first mandrel and part of the first medium layer, and forming a second mandrel between the rest first medium layers; covering the second mandrel of the first region with photoresist; removing the second mandrel which is not covered by the photoresist; and sequentially etching the first mask lamination and the metal layer of the first area along the second mandrel, and simultaneously etching and removing the first mask lamination and the metal layer of the second area, so that bit line structures arranged at intervals are formed only in the first area. By the technical scheme, the bit line structure failure is improved, and the manufacturing yield of the bit line structure is improved.

Description

Method for manufacturing bit line structure and method for manufacturing data storage array

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a method for fabricating a bit line structure and a method for fabricating a data storage array.

Background

In the fabrication of semiconductor materials, various techniques are used to remove thin films from a substrate and patterns of desired materials are formed on the substrate surface by the removal process. However, in the conventional self-aligned dual imaging process, the mask layer is damaged by the etching process to cause over-etching, and the mask layer is damaged during the pattern down-shift and the subsequent wet etching process, especially in the complicated manufacturing process, the etching step needs to be repeated, which easily causes the mask pattern to tilt or collapse, and finally causes the bit line structure to fail.

Therefore, how to reduce the malformation or collapse of the bit line structure (bit line) in the pattern transfer is a problem to be solved in the prior art.

Disclosure of Invention

The present application provides a method for fabricating a bit line structure and a method for fabricating a data storage array, which can reduce the malformation or collapse of the bit line structure during the pattern transfer.

In order to solve the above problems, the present application provides a method for manufacturing a bit line structure, comprising: providing a substrate comprising a first region and a second region; forming a metal layer on the substrate and a first mask lamination layer and a second mask lamination layer which are positioned on the metal layer; patterning the second mask lamination to form first mandrels arranged at intervals; depositing a first medium layer on the first mandrel in a shape following manner by adopting a self-alignment double-imaging process, etching the first mandrel and part of the first medium layer, forming second mandrels arranged at intervals on the rest first medium layer, wherein the number of the second mandrels is more than that of the first mandrels; covering the second mandrel of the first region with photoresist; removing the second mandrel of the second region not covered by the photoresist to completely expose the first mask stack of the second region; and sequentially etching the first mask lamination and the metal layer of the first area along the second mandrel, and simultaneously etching and removing the first mask lamination and the metal layer of the second area, so that bit line structures arranged at intervals are formed only in the first area.

Further, the first mask lamination layer sequentially comprises an oxide layer, a first carbon layer and a first protective layer from bottom to top, and the first protective layer is a silicon-rich silicon oxynitride layer or a silicon layer.

Further, the second mask lamination is located on the first mask lamination, the second mask lamination sequentially comprises a second carbon layer and a second protective layer from bottom to top, and the second protective layer is a silicon-rich anti-reflection layer.

Further, a dielectric layer is included between the metal layer and the first mask stack.

Further, sequentially etching the first mask stack and the metal layer in the first region along the second mandrel, and simultaneously removing the first mask stack and the metal layer in the second region by etching, the method further includes: and etching the dielectric layer of the first area along the second mandrel, and simultaneously etching and removing the dielectric layer of the second area.

Further, patterning the second mask stack to form first mandrels arranged at intervals, specifically, etching a part of the second protection layer and a part of the second carbon layer, taking the remaining second protection layer and the remaining second carbon layer as initial mandrels, and removing the second protection layer on the top of the initial mandrels to form the first mandrels arranged at intervals.

Further, when the second protective layer on the top of the initial mandrel is removed, a first over-etching depth is formed in the first protective layer.

Further, when the second mandrels are arranged at intervals, a second over-etching depth is formed on the first protective layer.

Further, the sum of the first over-etching depth and the second over-etching depth is less than one half of the thickness of the first protection layer.

Further, before etching the first mandrel and a part of the first dielectric layer, the method further includes: and etching to remove the first dielectric layer higher than the top of the first mandrel, so that the top of the first mandrel is completely exposed.

Further, the removing the second mandrel of the second region not covered by the photoresist includes: and removing the second mandrel in the second area by using dilute hydrofluoric acid to improve the etching selection ratio.

Further, the ratio of water to hydrofluoric acid in the dilute hydrofluoric acid is 200:1.

further, the first region is a central region of the active region, and the second region is an edge region of the active region.

The application also provides a manufacturing method of the data storage array, which comprises the following steps: providing a substrate comprising a first region and a second region; forming a metal layer on the substrate and a first mask lamination layer and a second mask lamination layer which are positioned on the metal layer; patterning the second mask lamination to form first mandrels arranged at intervals; depositing a first medium layer on the first mandrel in a shape following manner by adopting a self-alignment double-imaging process, etching the first mandrel and part of the first medium layer, forming second mandrels arranged at intervals on the rest first medium layer, wherein the number of the second mandrels is more than that of the first mandrels; covering the second mandrel of the first region with photoresist; removing the second mandrel of the second region not covered by the photoresist to completely expose the first mask stack of the second region; sequentially etching the first mask lamination and the metal layer of the first area along the second mandrel, simultaneously removing the first mask lamination and the metal layer of the second area by etching, and forming bit line structures arranged at intervals only in the first area; forming a data storage array on the bit line structure.

Furthermore, the second mask lamination is located on the first mask lamination, the second mask lamination sequentially comprises a second carbon layer and a second protective layer from bottom to top, and the second protective layer is a silicon-rich anti-reflection layer.

Further, the removing the second mandrel of the second region not covered by the photoresist includes: removing the second mandrel in the second region with dilute hydrofluoric acid to improve the etching selectivity

According to the technical scheme, the substrate is provided, the metal layer, the first mask lamination layer and the first mask lamination layer are formed on the substrate, the first protective layer in the first mask lamination layer is set to be the silicon-rich silicon oxynitride layer or the silicon layer, and the second protective layer in the second mask lamination layer is set to be the silicon-rich anti-reflection layer, so that the etching selection ratio is improved, and the damage to the first carbon layer is reduced. And then, removing the second mandrel of the second area which is not covered by the photoresist by using dilute hydrofluoric acid to improve the etching selection ratio so as to completely expose the first mask lamination of the second area and have no damage to the first area A1. And sequentially etching the first mask lamination, the dielectric layer and the metal layer in the first region along the second mandrel, and simultaneously etching and removing the first mask lamination, the dielectric layer and the metal layer in the second region, so that the bit line structures arranged at intervals are only formed in the first region. The technical scheme improves the bit line structure failure caused by pattern transfer in the manufacturing process of the bit line structure.

Drawings

Fig. 1 is a flow chart provided by an embodiment of the present application.

Fig. 2A is a structural diagram of a mask layer according to an embodiment of the present disclosure.

Fig. 2B is a structural diagram of a mask layer according to an embodiment of the present disclosure.

Fig. 3A is a flowchart provided by an embodiment of the present application.

Fig. 3B is a block diagram of an initial mandrel provided in an embodiment of the present application.

Fig. 3C is a block diagram of a first mandrel provided in an embodiment of the present application.

Fig. 3D is a schematic diagram of a first over-etch depth according to an embodiment of the present application.

Fig. 4A is a structural diagram of a first dielectric layer according to an embodiment of the disclosure.

Fig. 4B is a block diagram of a second mandrel provided in an embodiment of the present application.

FIG. 5 is a schematic diagram provided by an embodiment of the present application.

Fig. 6A is a schematic diagram provided by an embodiment of the present application.

Fig. 6B is a schematic diagram of a bit line structure according to an embodiment of the present application.

Fig. 7 is a flowchart provided by an embodiment of the present application.

Detailed Description

Embodiments of a method for fabricating a bit line structure and a method for fabricating a data storage array provided in the present application are described in detail below with reference to the accompanying drawings.

Fig. 1 is a flowchart provided in an embodiment of the present application. The manufacturing method of the bit line structure comprises the following steps: step S101, providing a substrate, wherein the substrate comprises a first area and a second area; step S102, forming a metal layer on the substrate, and a first mask lamination layer and a second mask lamination layer which are positioned on the metal layer; step S103, patterning the second mask lamination to form first mandrels arranged at intervals; step S104, depositing a first dielectric layer on the first mandrel in a conformal manner by adopting a self-aligned dual-imaging process, etching the first mandrel and part of the first dielectric layer, forming second mandrels arranged at intervals on the rest first dielectric layer, wherein the number of the second mandrels is more than that of the first mandrels; step S105, covering the second mandrel of the first area by photoresist; step S106, removing the second mandrel of the second area which is not covered by the photoresist so as to completely expose the first mask lamination of the second area; step S107, sequentially etching the first mask stack and the metal layer in the first region along the second mandrel, and simultaneously etching and removing the first mask stack and the metal layer in the second region, so as to form bit line structures arranged at intervals only in the first region.

Fig. 2A is a structural diagram of a mask layer according to an embodiment of the present disclosure. Referring to steps S101 and S102, a substrate (substrate not shown) including a first area A1 and a second area A2 is provided, and a metal layer 23 and a first mask stack 21 and a second mask stack 22 on the metal layer 23 are formed on the substrate. In this embodiment, the first area A1 is a central area of the active area, and the second area A2 is an edge area of the active area. The first mask lamination 21 sequentially comprises an oxide layer 211, a first carbon layer 212 and a first protection layer 213 from bottom to top, and the first protection layer 213 is a silicon-rich silicon oxynitride layer or a silicon layer. The second mask stack 22 is located on the first mask stack 21, the second mask stack 22 sequentially includes a second carbon layer 221 and a second protection layer 222 from bottom to top, and the second protection layer 222 is a silicon-rich anti-reflection layer.

Fig. 2B is a structural diagram of a mask layer according to an embodiment of the disclosure. Referring to steps S101 and S102, a substrate (substrate not shown) including a first area A1 and a second area A2 is provided, and a metal layer 23 and a first mask stack 21 and a second mask stack 22 on the metal layer are formed on the substrate. In this embodiment, the first area A1 is a central area of the active area, and the second area A2 is an edge area of the active area. First mask stromatolite 21 from the bottom up includes oxide layer 211, first carbon-layer 212 and first protection layer 213 in proper order, first protection layer 213 is rich silicon oxynitride layer or silicon layer of silicon to improve the sculpture selectivity, reduce the damage to first carbon-layer 212. The second mask stack 22 is located on the first mask stack 21, the second mask stack 22 sequentially includes a second carbon layer 221 and a second protection layer 222 from bottom to top, and the second protection layer 222 is a silicon-rich anti-reflection layer. A dielectric layer 24 is also included between the metal layer 23 and the first mask stack 21.

By providing the first passivation layer 213 and the second passivation layer 222 with high selectivity, damage to the first carbon layer 212 during etching is reduced, and bit line structure failure caused by the inclination or collapse of the mask pattern during the bit line manufacturing process is improved.

Fig. 3A is a flowchart provided by an embodiment of the present application. Referring to step S103, the second mask stack is patterned to form first mandrels arranged at intervals. The patterning the second mask stack to form the first mandrels arranged at intervals comprises: step S301, etching part of the second protective layer and part of the second carbon layer; step S302, using the remaining second protective layer and the second carbon layer as initial mandrels; step S303, removing the second protection layer on the top of the initial mandrel to form the first mandrels arranged at intervals.

Fig. 3B is a block diagram of an initial mandrel provided in an embodiment of the present application. Referring to step S301 and step S302, a portion of the second passivation layer 222 and a portion of the second carbon layer 221 are etched, and the remaining second passivation layer 222 and the second carbon layer 221 are used as an initial mandrel 25.

Fig. 3C is a block diagram of a first mandrel provided in an embodiment of the present application. Referring to step S303, the second protection layer 222 on top of the initial mandrel 25 is removed to form the first mandrels 26 arranged at intervals.

Fig. 3D is a schematic diagram of a first over-etch depth provided in an embodiment of the present application. As shown in fig. 3B-3D, a first over-etch depth 27 is formed in the first protective layer 213 when the second protective layer 222 on top of the initial mandrel 25 is removed.

Fig. 4A is a structural diagram of a first dielectric layer according to an embodiment of the present disclosure. Referring to step S104, a self-aligned dual imaging process is used to deposit a first dielectric layer 28 on the first mandrel 26, and the first dielectric layer 28 higher than the top of the first mandrel 26 is etched away to completely expose the top of the first mandrel 26, so that the first mandrel 26 and a portion of the first dielectric layer 28 are etched.

Fig. 4B is a structural diagram of a second mandrel provided in an embodiment of the present application. Referring to step S104, the remaining first dielectric layers 28 form second mandrels 29 arranged at intervals, and the number of the second mandrels 29 is greater than that of the first mandrels 26. As shown in fig. 4A-4B, when the second mandrels 29 are formed at intervals, a second over-etching depth 30 is formed in the first protective layer. The sum of the first over-etch depth 27 and the second over-etch depth 30 is less than one-half the thickness of the first protection layer 213.

FIG. 5 is a schematic diagram provided by an embodiment of the present application. Referring to step S105, the second mandrel 29 of the first region A1 is covered with photoresist 31. Referring to step S106, the second mandrel 29 of the second area A2 not covered by the photoresist 31 is removed to completely expose the first mask stack 21 of the second area A2. The second mandrel 29 of the second area A2 not covered by the photoresist is removed, and the second mandrel 29 of the second area A2 is removed by using dilute hydrofluoric acid to improve the etching selectivity, so as to avoid damage to the first protection layer 213 in the first area A1 in the etching process, so that the first protection layer 213 can protect the first carbon layer 212 from over-etching in the pattern transfer process, and the bit line structure failure caused by the inclination or collapse of the mask pattern in the bit line manufacturing process is improved. In this embodiment, the ratio of water to hydrofluoric acid in the dilute hydrofluoric acid is 200:1.

fig. 6A is a schematic diagram provided by an embodiment of the present application. After removing the photoresist 31 in the first area A1, referring to step S107, the first mask stack 21 and the metal layer 23 in the first area A1 are sequentially etched along the second mandrel 29, which in this embodiment further includes etching the dielectric layer 24. And simultaneously, etching and removing the first mask stack 21 and the metal layer 23 in the second region A2, which further includes etching a dielectric layer 24 in this embodiment. Fig. 6B is a schematic diagram of a bit line structure according to an embodiment of the present application, through the above steps, bit line structures 32 are formed only in the first region A1.

In the above technical solution, a substrate is provided, a metal layer 23, and a first mask stack 21 and a first mask stack 22 on the metal layer 23 are formed on the substrate, the first protection layer 213 in the first mask stack 21 is set as a silicon-rich silicon oxynitride layer or a silicon layer, and the second protection layer 222 in the second mask stack 22 is set as a silicon-rich anti-reflection layer, so as to improve an etching selectivity and reduce damage to the first carbon layer 212. And then, the second mandrel 29 of the second area A2 which is not covered by the photoresist 31 is removed by using dilute hydrofluoric acid to improve the etching selection ratio, so that the first mask lamination 21 of the second area A2 is completely exposed and has no damage to the first area A1. And sequentially etching the first mask stack 21, the dielectric layer 24 and the metal layer 23 in the first region A1 along the second mandrel 29, and simultaneously etching and removing the first mask stack 21, the dielectric layer 24 and the metal layer 23 in the second region A2, so as to form bit line structures 32 arranged at intervals only in the first region A1. The technical scheme improves the bit line structure failure caused by pattern transfer in the bit line manufacturing process.

In another embodiment provided in the present application, the method for manufacturing a data storage array in this embodiment includes the method for manufacturing a bit line structure in the previous embodiment.

Fig. 7 is a flow chart provided by an embodiment of the present application. The manufacturing method of the data storage array comprises the following steps: step S101, providing a substrate, wherein the substrate comprises a first area and a second area; step S102, forming a metal layer on the substrate, and a first mask lamination layer and a second mask lamination layer which are positioned on the metal layer; step S103, patterning the second mask lamination to form first mandrels arranged at intervals; step S104, depositing a first dielectric layer on the first mandrel in a conformal manner by adopting a self-aligned dual imaging process, etching the first mandrel and part of the first dielectric layer, forming second mandrels arranged at intervals on the rest first dielectric layer, wherein the number of the second mandrels is more than that of the first mandrels; step S105, covering the second mandrel in the first area by photoresist; step S106, removing the second mandrel of the second area which is not covered by the photoresist so as to completely expose the first mask lamination of the second area; step S107, sequentially etching the first mask lamination and the metal layer of the first area along the second mandrel, simultaneously removing the first mask lamination and the metal layer of the second area by etching, and forming bit line structures arranged at intervals only in the first area; in step S108, a data storage array is formed on the bit line structure.

Fig. 2A is a structural diagram of a mask layer according to an embodiment of the present disclosure. Referring to steps S101 and S102, a substrate including a first region A1 and a second region A2 is provided, and a metal layer 23 and a first mask stack 21 and a second mask stack 22 on the metal layer 23 are formed on the substrate. In this embodiment, the first area A1 is a central area of the active area, and the second area A2 is an edge area of the active area. The first mask stack 21 sequentially includes an oxide layer 211, a first carbon layer 212, and a first protection layer 213 from bottom to top, and the first protection layer 213 is a silicon-rich silicon oxynitride layer or a silicon layer. The second mask stack 22 is located on the first mask stack 21, the second mask stack 22 sequentially includes a second carbon layer 221 and a second protection layer 222 from bottom to top, and the second protection layer 222 is a silicon-rich anti-reflection layer.

Fig. 2B is a structural diagram of a mask layer according to an embodiment of the present disclosure. The substrate comprises a first area A1 and a second area A2, and a metal layer 23 and a first mask stack 21 and a second mask stack 22 on the metal layer are formed on the substrate. In this embodiment, the first area A1 is a central area of the active area, and the second area A2 is an edge area of the active area. The first mask lamination 21 sequentially comprises an oxide layer 211, a first carbon layer 212 and a first protection layer 213 from bottom to top, and the first protection layer 213 is a silicon-rich silicon oxynitride layer or a silicon layer. The second mask stack 22 is located on the first mask stack 21, the second mask stack 22 sequentially includes a second carbon layer 221 and a second protection layer 222 from bottom to top, and the second protection layer 222 is a silicon-rich anti-reflection layer. A dielectric layer 24 is also included between the metal layer 23 and the first mask stack 21.

Fig. 3A is a flow chart provided by an embodiment of the present application. Referring to step S103, the second mask stack is patterned to form first mandrels arranged at intervals. The patterning the second mask stack to form the first mandrels arranged at intervals comprises: step S301, etching part of the second protective layer and part of the second carbon layer; step S302, using the remaining second protective layer and the second carbon layer as initial mandrels; step S303, removing the second protection layer on the top of the initial mandrel to form the first mandrels arranged at intervals.

Fig. 3D is a schematic diagram of a first over-etch depth according to an embodiment of the present application. As shown in fig. 3D, when the second protection layer 222 on top of the initial mandrel 25 is removed, a first over-etching depth 27 is formed in the first protection layer 213.

Fig. 4A is a structural diagram of a first dielectric layer according to an embodiment of the disclosure. Referring to step S104, a self-aligned dual imaging process is used to deposit a first dielectric layer 28 on the first mandrel 26, and the first dielectric layer 28 higher than the top of the first mandrel 26 is etched away to completely expose the top of the first mandrel 26, so that the first mandrel 26 and a portion of the first dielectric layer 28 are etched.

Fig. 4B is a structural diagram of a second mandrel provided in an embodiment of the present application. Referring to step S104, the remaining first dielectric layers 28 form second mandrels 29 arranged at intervals, and the number of the second mandrels 29 is greater than that of the first mandrels 26.

Fig. 4A-4B are schematic views of a second over etch depth provided in an embodiment of the present application. As shown in fig. 4B, when the second mandrels 29 are formed at intervals, a second over-etching depth 30 is formed in the first protective layer. The sum of the first over-etch depth 27 and the second over-etch depth 30 is less than one-half the thickness of the first protection layer 213.

FIG. 5 is a schematic diagram provided by an embodiment of the present application. Referring to step S105, the second mandrel 29 of the first area A1 is covered with photoresist 31. Referring to step S106, the second mandrel 29 of the second area A2 not covered by the photoresist 31 is removed to completely expose the first mask stack 21 of the second area A2. The second mandrel 29 of the second area A2 not covered by the photoresist is removed, and the second mandrel 29 of the second area A2 is removed by using dilute hydrofluoric acid to improve the etching selectivity, so as to avoid damage to the first protection layer 213 in the first area A1 during the etching process, so that the first protection layer 213 can protect the first carbon layer 212 from being over-etched during the pattern transfer process, and the bit line structure failure caused by the inclination or collapse of the mask pattern during the bit line manufacturing process is improved. In this embodiment, the ratio of water to hydrofluoric acid in the diluted hydrofluoric acid is 200:1.

fig. 6A is a schematic diagram provided by an embodiment of the present application. After removing the photoresist 31 in the first area A1, referring to step S107, the first mask stack 21 and the metal layer 23 in the first area A1 are sequentially etched along the second mandrel 29, i.e. the dashed line at the edge of the second mandrel 29 in fig. 6A, which further includes etching the dielectric layer 24 in this embodiment. And simultaneously, etching and removing the first mask stack 21 and the metal layer 23 in the second region A2, which further includes etching a dielectric layer 24 in this embodiment. Fig. 6B is a schematic diagram of a bit line structure according to an embodiment of the present application, and through the above steps, bit line structures 32 are formed only in the first region A1.

Step S108, continue to form a data storage array on the bit line structure. The data storage array comprises a plurality of bit line structures, and the step of continuously forming the data storage array on the bit line structures comprises the step of forming a reading device and a programming device, wherein the reading device and the programming device comprise a plurality of transistors, and the transistors are formed through semiconductor processes such as thin film deposition, photoetching, etching, doping and the like.

In the above technical solution, a substrate is provided, a metal layer 23, and a first mask stack 21 and a first mask stack 22 on the metal layer 23 are formed on the substrate, the first protection layer 213 in the first mask stack 21 is set as a silicon-rich silicon oxynitride layer or a silicon layer, and the second protection layer 222 in the second mask stack 22 is set as a silicon-rich anti-reflection layer, so as to improve an etching selectivity and reduce damage to the first carbon layer 212. And then, the second mandrel 29 of the second area A2 which is not covered by the photoresist 31 is removed by using dilute hydrofluoric acid to improve the etching selection ratio, so that the first mask lamination 21 of the second area A2 is completely exposed and has no damage to the first area A1. The first mask stack 21, the dielectric layer 24 and the metal layer 23 in the first region A1 are sequentially etched along the second mandrel 29, and the first mask stack 21, the dielectric layer 24 and the metal layer 23 in the second region A2 are simultaneously removed by etching, so that bit line structures arranged at intervals are formed only in the first region A1. Through the technical scheme, the bit line structure failure caused by the inclination or collapse of the mask pattern in the bit line manufacturing process is improved, the manufacturing yield of the bit line structure is improved, and a reliable data storage array is formed.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, many modifications and adaptations can be made without departing from the principle of the present invention, and such modifications and adaptations should also be considered as the scope of the present invention.

Claims

1. A method for fabricating a bit line structure, comprising:

providing a substrate comprising a first region and a second region;

forming a metal layer on the substrate and a first mask lamination layer and a second mask lamination layer which are positioned on the metal layer;

patterning the second mask lamination to form first mandrels arranged at intervals;

depositing a first dielectric layer on the first mandrel in a self-aligning double-imaging process, etching the first mandrel and part of the first dielectric layer, and forming second mandrels arranged at intervals on the rest first dielectric layer, wherein the number of the second mandrels is more than that of the first mandrels;

covering the second mandrel of the first region with photoresist;

removing the second mandrel of the second region not covered by the photoresist to completely expose the first mask stack of the second region;

and sequentially etching the first mask lamination and the metal layer in the first area along the second mandrel, and simultaneously etching and removing the first mask lamination and the metal layer in the second area, so that the bit line structures arranged at intervals are only formed in the first area.

2. The method of claim 1, wherein the first mask stack comprises, in order from bottom to top, an oxide layer, a first carbon layer, and a first protective layer, and the first protective layer is a silicon-rich silicon oxynitride layer or a silicon layer.

3. The method of claim 2, wherein the second mask stack is disposed on the first mask stack, the second mask stack sequentially comprises a second carbon layer and a second passivation layer from bottom to top, and the second passivation layer is a silicon-rich anti-reflection layer.

4. The method of claim 1 further comprising a dielectric layer between the metal layer and the first mask stack.

5. The method of claim 4, wherein the etching the first mask stack layer and the metal layer of the first region sequentially along the second mandrel, and the etching the first mask stack layer and the metal layer of the second region simultaneously, further comprises: and etching the dielectric layer of the first area along the second mandrel, and simultaneously etching and removing the dielectric layer of the second area.

6. The method of claim 3, wherein patterning the second mask stack to form the first mandrels arranged at intervals comprises etching a portion of the second passivation layer and a portion of the second carbon layer, using the remaining second passivation layer and the second carbon layer as initial mandrels, and removing the second passivation layer on top of the initial mandrels to form the first mandrels arranged at intervals.

7. The method of claim 6, wherein a first over-etching depth is formed on the first passivation layer when the second passivation layer on top of the initial mandrel is removed.

8. The method of claim 7, wherein a second over-etch depth is formed on the first passivation layer when the second mandrels are formed at intervals.

9. The method of claim 8, wherein a sum of the first over-etch depth and the second over-etch depth is less than one-half of a thickness of the first protection layer.

10. The method of claim 1, further comprising, before etching the first mandrel and a portion of the first dielectric layer: and etching to remove the first dielectric layer higher than the top of the first mandrel, so that the top of the first mandrel is completely exposed.

11. The method of claim 1, wherein the removing the second mandrel in the second region not covered by the photoresist comprises: and removing the second mandrel in the second area by using dilute hydrofluoric acid to improve the etching selection ratio.

12. The method of claim 11, wherein the ratio of hydrofluoric acid to water in the dilute hydrofluoric acid is 200:1.

13. the method of claim 1, wherein the first region is a center region of the active region and the second region is an edge region of the active region.

14. A method of fabricating a data storage array, comprising:

providing a substrate comprising a first region and a second region;

covering the second mandrel of the first region with photoresist;

sequentially etching the first mask lamination and the metal layer of the first area along the second mandrel, and simultaneously etching and removing the first mask lamination and the metal layer of the second area, so that bit line structures arranged at intervals are formed only in the first area;

forming a data storage array on the bit line structure.

15. The method of claim 14, wherein the first mask stack comprises, in order from bottom to top, an oxide layer, a first carbon layer, and a first protective layer, and the first protective layer is a silicon-rich silicon oxynitride layer or a silicon layer.

16. The method of claim 15, wherein the second mask layer is disposed on the first mask layer, the second mask layer sequentially comprises a second carbon layer and a second passivation layer from bottom to top, and the second passivation layer is a silicon-rich anti-reflection layer.

17. The method of claim 16, wherein patterning the second mask stack to form the first mandrels spaced apart comprises etching a portion of the second passivation layer and a portion of the second carbon layer, using the remaining second passivation layer and second carbon layer as an initial mandrel, and removing the second passivation layer on top of the initial mandrel to form the first mandrels spaced apart.

18. The method of claim 14, further comprising, prior to etching the first mandrel and a portion of the first dielectric layer: and etching to remove the first dielectric layer higher than the top of the first mandrel, so that the top of the first mandrel is completely exposed.

19. The method of claim 14, wherein removing the second mandrel of the second region not covered by the photoresist comprises: and removing the second mandrel in the second area by using dilute hydrofluoric acid to improve the etching selection ratio.