US20020109167A1 - Memory device and method of fabrication thereof - Google Patents

Memory device and method of fabrication thereof Download PDF

Info

Publication number
US20020109167A1
US20020109167A1 US10/033,013 US3301301A US2002109167A1 US 20020109167 A1 US20020109167 A1 US 20020109167A1 US 3301301 A US3301301 A US 3301301A US 2002109167 A1 US2002109167 A1 US 2002109167A1
Authority
US
United States
Prior art keywords
oxide film
write line
seed layer
memory device
mtj cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/033,013
Other languages
English (en)
Inventor
Chang Kang
Young Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KANG, CHANG YONG, KIM, YOUNG GWAN
Publication of US20020109167A1 publication Critical patent/US20020109167A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type

Definitions

  • a magnetic random access memory (abbreviated as ‘MRAM’) is disclosed more specifically, an improved MRAM having a higher speed than an SRAM, integration density as high as a DRAM, and a property of a nonvolatile memory such as a flash memory is disclosed.
  • MRAM magnetic random access memory
  • the MRAM is a memory device for reading and writing information by forming multi-layer ferromagnetic thin films, and for sensing current variations according to a magnetization direction of the respective thin film.
  • the MRAM has a high speed, low power consumption and allows high integration density by the special properties of the magnetic thin film, and performs a nonvolatile memory operation such as a flash memory.
  • the MRAM embodies a memory device by using a giant magneto resistive (abbreviated as ‘GMR’) phenomenon or a spin-polarized magneto-transmission (SPMT) generated when the spin influences electron transmission.
  • GMR giant magneto resistive
  • SPMT spin-polarized magneto-transmission
  • the MRAM using the GMR utilizes the phenomenon that resistance is remarkably varied when spin directions are different in two magnetic layers having a non-magnetic layer disposed therebetween in a GMR magnetic memory device.
  • the MRAM using the SPMT utilizes the phenomenon that larger current transmission is generated when spin directions are identical in two magnetic layers having an insulating layer therebetween in a magnetic permeable junction memory device.
  • MRAM research is still in its early stage, and mostly concentrated on the formation of multi-layer magnetic thin films, less on the researches on a unit cell structure and a peripheral sensing circuit.
  • FIG. 1 is a cross-sectional diagram illustrating a conventional MRAM.
  • a gate electrode 33 namely a first word line is formed on a semiconductor substrate 31 .
  • Source/drain junction regions 35 a and 35 b are formed on the semiconductor substrate 31 at both sides of the first word line 33 .
  • a ground line 37 a and a first conductive layer 37 b are formed to contact the source/drain junction regions 35 a and 35 b .
  • the ground line 37 a is formed in a patterning process of the first conductive layer 37 b.
  • a first interlayer insulating film 39 is formed to planarize the whole surface of the resultant structure, and a first contact plug 41 is formed to expose the first conductive layer 37 b.
  • a second conductive layer which is a lower read layer 43 contacting the first contact plug 41 is patterned.
  • a second interlayer insulating film 45 is formed to planarize the whole surface of the resultant structure, and a second word line which is a write line 47 is formed on the second interlayer insulating film 45 .
  • a third interlayer insulating film 48 is formed to planarize the upper portion of the second word line which is the write line 47 .
  • a second contact plug 49 is formed to contact the second conductive layer 43 .
  • a seed layer 51 is formed into contact the second contact plug 49 .
  • the seed layer 51 is formed to overlap between the upper portion of the second contact plug 49 and the upper portion of the write line 47 .
  • a semi-ferromagnetic layer (not shown), a pinned ferromagnetic layer 55 , a tunnel junction layer 57 and a free ferromagnetic layer 59 are stacked on the seed layer 51 , thereby forming a magnetic tunnel junction (MTJ) cell 100 to have a pattern size as large as the write line 47 and to overlap the write line 47 .
  • MTJ magnetic tunnel junction
  • the semi-ferromagnetic layer prevents the magnetization direction of the pinned layer from being changed, and the magnetization direction of the tunnel junction layer 57 fixed to one direction.
  • the magnetization direction of the free ferromagnetic layer 59 can be changed by external magnetic field, and information of ‘0’ or ‘1’ can be stored according to the magnetization direction of the free ferromagnetic layer 59 .
  • a fourth interlayer insulating film 60 is formed over the resultant structure, and planarized to expose the free ferromagnetic layer 59 .
  • An upper read layer, namely a bit line 61 is formed to contact the free ferromagnetic layer 59 .
  • FIG. 2 is a detailed cross-sectional diagram illustrating portion of FIG. 1.
  • the second word line 47 and the seed layer 51 maintain an interval of ‘d’, and the pinned ferromagnetic layer 55 , the tunnel junction layer 57 and the free ferromagnetic layer 59 are stacked on the seed layer 51 , thereby forming the MTJ cell.
  • ‘d’ is formed in the third interlayer insulating film 48 , and has a size ranging from 1000 to 2000 ⁇ .
  • the conventional memory device and fabrication method therefor have a disadvantage in that a distance between the seed layer 51 of the lower portion of the MTJ cell 100 of the MRAM and the second word line 47 positioned therebelow is high, and thus power consumption is increased in a write operation.
  • a memory device and a fabrication method therefor which can perform a write operation with a small current by decreasing a distance between an MTJ cell and a second word line which is a write line.
  • a disclosed memory device comprises: a write line formed on a semiconductor substrate; an oxide film formed on the surface of the write line; a seed layer contacting the oxide film; and an MTJ cell contacting the upper portion of the seed layer, and being overlapped with the write line.
  • a disclosed method for fabricating a memory device comprises: forming a write line on a semiconductor substrate; forming an oxide film by oxidizing the surface of the write line; forming a seed layer to contact the oxide film on the write line; and forming an MTJ cell to contact the upper portion of the seed layer, being overlapped with the write line.
  • a write operation is performed with a small current by reducing a distance between the second word line which is a write line and the MTJ cell.
  • the oxide film is formed with a thickness ranging from about 100 to about 500 ⁇ by oxidizing the surface of the write line, or depositing an oxide film on the surface of the write line.
  • FIG. 1 is a cross-sectional view illustrating sequential steps of a conventional method for fabricating a memory device
  • FIG. 2 is a detailed view illustrating a portion of FIG. 1;
  • FIG. 3 is a cross-sectional view illustrating a method for fabricating a memory device in accordance with the disclosure.
  • FIG. 3 is a cross-sectional diagram illustrating a method for fabricating the memory device in accordance with a preferred embodiment.
  • a second word line 101 is formed on the second interlayer insulating film 45 of FIG. 1 by patterning.
  • the second word line 101 is formed by using an element selected from the group consisting of tungsten, aluminum, copper and combinations thereof for easy surface oxidation.
  • a third interlayer insulating film 102 is formed and planarized to expose the second word line 101 .
  • the third interlayer insulating film 102 is formed by using an insulating film having a low dielectric constant.
  • the third interlayer insulating film 102 is formed to cover the second word line 101 , and then evenly etched by a chemical mechanical polishing process, thereby exposing the second word line 101 .
  • the exposed surface of the second word line 101 is oxidized to form an oxide film 103 having a thickness ranging from about 100 to about 500 ⁇ .
  • the oxide film 103 is composed of an insulating film such as a nitride film or alumina.
  • the oxide film 103 has a different dielectric constant from a peripheral insulating film formed as an interlayer insulating film.
  • the alumina has a higher dielectric constant than the general interlayer insulating film.
  • a seed layer 105 is formed on the second word line 101 including the oxide film 103 , and an MTJ cell having a stacked structure of a pinned ferromagnetic layer 107 , a tunnel junction layer 109 and a free ferromagnetic layer 111 is formed thereon.
  • the oxide film 103 is thinly formed, the write operation can be performed with a small current.
  • a planarized interlayer insulating film 120 exposing the oxide film 103 is formed after the formation process of the oxide film 103 , and a seed layer 105 and an MTJ cell are formed on the resultant planarized structure.
  • the write operation can be performed with a small current by reducing the distance between the second word line and the MTJ cell, thereby improving the property of the device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)
US10/033,013 2000-12-28 2001-12-27 Memory device and method of fabrication thereof Abandoned US20020109167A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR2000-83819 2000-12-28
KR10-2000-0083819A KR100390977B1 (ko) 2000-12-28 2000-12-28 반도체소자의 제조방법

Publications (1)

Publication Number Publication Date
US20020109167A1 true US20020109167A1 (en) 2002-08-15

Family

ID=19703763

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/033,013 Abandoned US20020109167A1 (en) 2000-12-28 2001-12-27 Memory device and method of fabrication thereof
US10/026,834 Expired - Lifetime US6465262B2 (en) 2000-12-28 2001-12-27 Method for manufacturing a semiconductor device

Family Applications After (1)

Application Number Title Priority Date Filing Date
US10/026,834 Expired - Lifetime US6465262B2 (en) 2000-12-28 2001-12-27 Method for manufacturing a semiconductor device

Country Status (4)

Country Link
US (2) US20020109167A1 (ko)
JP (1) JP2002246569A (ko)
KR (1) KR100390977B1 (ko)
TW (1) TWI228797B (ko)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040100818A1 (en) * 2002-11-22 2004-05-27 Hiroaki Yoda Magnetic random access memory
US20050014297A1 (en) * 2002-01-16 2005-01-20 Hasan Nejad Methods of forming magnetoresistive memory devices and assemblies
US8570799B2 (en) 2011-08-16 2013-10-29 Intel Mobile Communications GmbH Magnetic random access memory with conversion circuitry
US20150236071A1 (en) * 2012-09-21 2015-08-20 Korea University Research And Business Foundation Magnetic memory device using in-plane current and electric field
US9997699B2 (en) 2015-09-18 2018-06-12 Samsung Electronics Co., Ltd. Semiconductor device having magnetic tunnel junction structure and method of fabricating the same
CN111816760A (zh) * 2019-04-11 2020-10-23 上海磁宇信息科技有限公司 一种磁性随机存储器磁性存储单元及其形成方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8435830B2 (en) 2009-03-18 2013-05-07 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5650958A (en) * 1996-03-18 1997-07-22 International Business Machines Corporation Magnetic tunnel junctions with controlled magnetic response
US5946228A (en) * 1998-02-10 1999-08-31 International Business Machines Corporation Limiting magnetic writing fields to a preferred portion of a changeable magnetic region in magnetic devices
US6114719A (en) * 1998-05-29 2000-09-05 International Business Machines Corporation Magnetic tunnel junction memory cell with in-stack biasing of the free ferromagnetic layer and memory array using the cell
US6183859B1 (en) * 1998-07-20 2001-02-06 Motorola, Inc Low resistance MTJ
US6034887A (en) * 1998-08-05 2000-03-07 International Business Machines Corporation Non-volatile magnetic memory cell and devices
US6219212B1 (en) * 1998-09-08 2001-04-17 International Business Machines Corporation Magnetic tunnel junction head structure with insulating antiferromagnetic layer
US6611405B1 (en) * 1999-09-16 2003-08-26 Kabushiki Kaisha Toshiba Magnetoresistive element and magnetic memory device
US6473336B2 (en) * 1999-12-16 2002-10-29 Kabushiki Kaisha Toshiba Magnetic memory device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050014297A1 (en) * 2002-01-16 2005-01-20 Hasan Nejad Methods of forming magnetoresistive memory devices and assemblies
US20070020774A1 (en) * 2002-01-16 2007-01-25 Hasan Nejad Methods of utilizing magnetoresistive memory constructions
US20040100818A1 (en) * 2002-11-22 2004-05-27 Hiroaki Yoda Magnetic random access memory
US6927468B2 (en) 2002-11-22 2005-08-09 Kabushiki Kaisha Toshiba Magnetic random access memory
US8570799B2 (en) 2011-08-16 2013-10-29 Intel Mobile Communications GmbH Magnetic random access memory with conversion circuitry
US8848437B2 (en) 2011-08-16 2014-09-30 Intel Mobile Communications GmbH Magnetic random access memory
US20150236071A1 (en) * 2012-09-21 2015-08-20 Korea University Research And Business Foundation Magnetic memory device using in-plane current and electric field
US9997699B2 (en) 2015-09-18 2018-06-12 Samsung Electronics Co., Ltd. Semiconductor device having magnetic tunnel junction structure and method of fabricating the same
US10211396B2 (en) 2015-09-18 2019-02-19 Samsung Electronics Co., Ltd. Semiconductor device having magnetic tunnel junction structure and method of fabricating the same
CN111816760A (zh) * 2019-04-11 2020-10-23 上海磁宇信息科技有限公司 一种磁性随机存储器磁性存储单元及其形成方法

Also Published As

Publication number Publication date
KR20020054655A (ko) 2002-07-08
JP2002246569A (ja) 2002-08-30
KR100390977B1 (ko) 2003-07-12
US6465262B2 (en) 2002-10-15
TWI228797B (en) 2005-03-01
US20020086448A1 (en) 2002-07-04

Similar Documents

Publication Publication Date Title
US7220599B2 (en) Method for manufacturing magneto-resistive random access memory
KR100608248B1 (ko) 엠램 전극용 키퍼
US6909129B2 (en) Magnetic random access memory
US6657270B2 (en) Magnetic random access memory using bipolar junction transistor, and method for fabricating the same
US6542398B2 (en) Magnetic random access memory
US7247506B2 (en) Method for producing magnetic memory device
US6664579B2 (en) Magnetic random access memory using bipolar junction transistor
US6750540B2 (en) Magnetic random access memory using schottky diode
US20050020076A1 (en) Method for manufacturing MTJ cell of magnetic random access memory
US7095069B2 (en) Magnetoresistive random access memory, and manufacturing method thereof
KR100520175B1 (ko) 반도체소자의 제조방법
US6707085B2 (en) Magnetic random access memory
US20020109167A1 (en) Memory device and method of fabrication thereof
US6787372B1 (en) Method for manufacturing MTJ cell of magnetic random access memory
US6914003B2 (en) Method for manufacturing magnetic random access memory
JP2009224477A (ja) 半導体記憶装置及びその製造方法
KR20030078136A (ko) 마그네틱 램의 제조방법
US6849466B2 (en) Method for manufacturing MTJ cell of magnetic random access memory
KR100427716B1 (ko) 엠.아이.엘.씨.를 이용한 다이오드가 사용된 마그네틱 램및 그 형성방법
KR20040041337A (ko) 새로운 구조 및 동작 방식을 갖는 자기 메모리 및 그 제조방법
TW498326B (en) Formation method of magneto-resistance RAM with magnetic tunnel junction
US20040190189A1 (en) Method for manufacturing MTJ cell of magnetic random access memory
KR20030058626A (ko) 엠램(ｍｒａｍ) 셀의 제조 방법

Legal Events

Date Code Title Description
AS Assignment

Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KANG, CHANG YONG;KIM, YOUNG GWAN;REEL/FRAME:012819/0439

Effective date: 20020318

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION