US20020109167A1 - Memory device and method of fabrication thereof - Google Patents
Memory device and method of fabrication thereof Download PDFInfo
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- US20020109167A1 US20020109167A1 US10/033,013 US3301301A US2002109167A1 US 20020109167 A1 US20020109167 A1 US 20020109167A1 US 3301301 A US3301301 A US 3301301A US 2002109167 A1 US2002109167 A1 US 2002109167A1
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- oxide film
- write line
- seed layer
- memory device
- mtj cell
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- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 239000007888 film coating Substances 0.000 claims 1
- 238000009501 film coating Methods 0.000 claims 1
- 230000005291 magnetic effect Effects 0.000 abstract description 11
- 230000010354 integration Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 42
- 239000010408 film Substances 0.000 description 31
- 239000011229 interlayer Substances 0.000 description 13
- 230000005294 ferromagnetic effect Effects 0.000 description 11
- 230000005415 magnetization Effects 0.000 description 5
- 239000010409 thin film Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003302 ferromagnetic material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/01—Manufacture or treatment
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
Definitions
- a magnetic random access memory (abbreviated as ‘MRAM’) is disclosed more specifically, an improved MRAM having a higher speed than an SRAM, integration density as high as a DRAM, and a property of a nonvolatile memory such as a flash memory is disclosed.
- MRAM magnetic random access memory
- the MRAM is a memory device for reading and writing information by forming multi-layer ferromagnetic thin films, and for sensing current variations according to a magnetization direction of the respective thin film.
- the MRAM has a high speed, low power consumption and allows high integration density by the special properties of the magnetic thin film, and performs a nonvolatile memory operation such as a flash memory.
- the MRAM embodies a memory device by using a giant magneto resistive (abbreviated as ‘GMR’) phenomenon or a spin-polarized magneto-transmission (SPMT) generated when the spin influences electron transmission.
- GMR giant magneto resistive
- SPMT spin-polarized magneto-transmission
- the MRAM using the GMR utilizes the phenomenon that resistance is remarkably varied when spin directions are different in two magnetic layers having a non-magnetic layer disposed therebetween in a GMR magnetic memory device.
- the MRAM using the SPMT utilizes the phenomenon that larger current transmission is generated when spin directions are identical in two magnetic layers having an insulating layer therebetween in a magnetic permeable junction memory device.
- MRAM research is still in its early stage, and mostly concentrated on the formation of multi-layer magnetic thin films, less on the researches on a unit cell structure and a peripheral sensing circuit.
- FIG. 1 is a cross-sectional diagram illustrating a conventional MRAM.
- a gate electrode 33 namely a first word line is formed on a semiconductor substrate 31 .
- Source/drain junction regions 35 a and 35 b are formed on the semiconductor substrate 31 at both sides of the first word line 33 .
- a ground line 37 a and a first conductive layer 37 b are formed to contact the source/drain junction regions 35 a and 35 b .
- the ground line 37 a is formed in a patterning process of the first conductive layer 37 b.
- a first interlayer insulating film 39 is formed to planarize the whole surface of the resultant structure, and a first contact plug 41 is formed to expose the first conductive layer 37 b.
- a second conductive layer which is a lower read layer 43 contacting the first contact plug 41 is patterned.
- a second interlayer insulating film 45 is formed to planarize the whole surface of the resultant structure, and a second word line which is a write line 47 is formed on the second interlayer insulating film 45 .
- a third interlayer insulating film 48 is formed to planarize the upper portion of the second word line which is the write line 47 .
- a second contact plug 49 is formed to contact the second conductive layer 43 .
- a seed layer 51 is formed into contact the second contact plug 49 .
- the seed layer 51 is formed to overlap between the upper portion of the second contact plug 49 and the upper portion of the write line 47 .
- a semi-ferromagnetic layer (not shown), a pinned ferromagnetic layer 55 , a tunnel junction layer 57 and a free ferromagnetic layer 59 are stacked on the seed layer 51 , thereby forming a magnetic tunnel junction (MTJ) cell 100 to have a pattern size as large as the write line 47 and to overlap the write line 47 .
- MTJ magnetic tunnel junction
- the semi-ferromagnetic layer prevents the magnetization direction of the pinned layer from being changed, and the magnetization direction of the tunnel junction layer 57 fixed to one direction.
- the magnetization direction of the free ferromagnetic layer 59 can be changed by external magnetic field, and information of ‘0’ or ‘1’ can be stored according to the magnetization direction of the free ferromagnetic layer 59 .
- a fourth interlayer insulating film 60 is formed over the resultant structure, and planarized to expose the free ferromagnetic layer 59 .
- An upper read layer, namely a bit line 61 is formed to contact the free ferromagnetic layer 59 .
- FIG. 2 is a detailed cross-sectional diagram illustrating portion of FIG. 1.
- the second word line 47 and the seed layer 51 maintain an interval of ‘d’, and the pinned ferromagnetic layer 55 , the tunnel junction layer 57 and the free ferromagnetic layer 59 are stacked on the seed layer 51 , thereby forming the MTJ cell.
- ‘d’ is formed in the third interlayer insulating film 48 , and has a size ranging from 1000 to 2000 ⁇ .
- the conventional memory device and fabrication method therefor have a disadvantage in that a distance between the seed layer 51 of the lower portion of the MTJ cell 100 of the MRAM and the second word line 47 positioned therebelow is high, and thus power consumption is increased in a write operation.
- a memory device and a fabrication method therefor which can perform a write operation with a small current by decreasing a distance between an MTJ cell and a second word line which is a write line.
- a disclosed memory device comprises: a write line formed on a semiconductor substrate; an oxide film formed on the surface of the write line; a seed layer contacting the oxide film; and an MTJ cell contacting the upper portion of the seed layer, and being overlapped with the write line.
- a disclosed method for fabricating a memory device comprises: forming a write line on a semiconductor substrate; forming an oxide film by oxidizing the surface of the write line; forming a seed layer to contact the oxide film on the write line; and forming an MTJ cell to contact the upper portion of the seed layer, being overlapped with the write line.
- a write operation is performed with a small current by reducing a distance between the second word line which is a write line and the MTJ cell.
- the oxide film is formed with a thickness ranging from about 100 to about 500 ⁇ by oxidizing the surface of the write line, or depositing an oxide film on the surface of the write line.
- FIG. 1 is a cross-sectional view illustrating sequential steps of a conventional method for fabricating a memory device
- FIG. 2 is a detailed view illustrating a portion of FIG. 1;
- FIG. 3 is a cross-sectional view illustrating a method for fabricating a memory device in accordance with the disclosure.
- FIG. 3 is a cross-sectional diagram illustrating a method for fabricating the memory device in accordance with a preferred embodiment.
- a second word line 101 is formed on the second interlayer insulating film 45 of FIG. 1 by patterning.
- the second word line 101 is formed by using an element selected from the group consisting of tungsten, aluminum, copper and combinations thereof for easy surface oxidation.
- a third interlayer insulating film 102 is formed and planarized to expose the second word line 101 .
- the third interlayer insulating film 102 is formed by using an insulating film having a low dielectric constant.
- the third interlayer insulating film 102 is formed to cover the second word line 101 , and then evenly etched by a chemical mechanical polishing process, thereby exposing the second word line 101 .
- the exposed surface of the second word line 101 is oxidized to form an oxide film 103 having a thickness ranging from about 100 to about 500 ⁇ .
- the oxide film 103 is composed of an insulating film such as a nitride film or alumina.
- the oxide film 103 has a different dielectric constant from a peripheral insulating film formed as an interlayer insulating film.
- the alumina has a higher dielectric constant than the general interlayer insulating film.
- a seed layer 105 is formed on the second word line 101 including the oxide film 103 , and an MTJ cell having a stacked structure of a pinned ferromagnetic layer 107 , a tunnel junction layer 109 and a free ferromagnetic layer 111 is formed thereon.
- the oxide film 103 is thinly formed, the write operation can be performed with a small current.
- a planarized interlayer insulating film 120 exposing the oxide film 103 is formed after the formation process of the oxide film 103 , and a seed layer 105 and an MTJ cell are formed on the resultant planarized structure.
- the write operation can be performed with a small current by reducing the distance between the second word line and the MTJ cell, thereby improving the property of the device.
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Hall/Mr Elements (AREA)
- Mram Or Spin Memory Techniques (AREA)
Abstract
A memory device and a fabrication method therefor. In order to improve an operation property of a magnetic RAM (abbreviated as ‘MRAM’) having a higher speed than an SRAM, integration as high as a DRAM, and a property of a nonvolatile memory such as a flash memory, an oxide film is thinly formed on a second word line which is a write line, and an MTJ cell is formed according to a succeeding process. The MRAM is formed by reducing a distance between the write line and the MTJ cell. It is thus possible to perform a write operation with a small current.
Description
- A magnetic random access memory (abbreviated as ‘MRAM’) is disclosed more specifically, an improved MRAM having a higher speed than an SRAM, integration density as high as a DRAM, and a property of a nonvolatile memory such as a flash memory is disclosed.
- Most of the semiconductor memory manufacturing companies have developed the MRAM using a ferromagnetic material as one of the next generation memory devices.
- The MRAM is a memory device for reading and writing information by forming multi-layer ferromagnetic thin films, and for sensing current variations according to a magnetization direction of the respective thin film. The MRAM has a high speed, low power consumption and allows high integration density by the special properties of the magnetic thin film, and performs a nonvolatile memory operation such as a flash memory.
- The MRAM embodies a memory device by using a giant magneto resistive (abbreviated as ‘GMR’) phenomenon or a spin-polarized magneto-transmission (SPMT) generated when the spin influences electron transmission.
- The MRAM using the GMR utilizes the phenomenon that resistance is remarkably varied when spin directions are different in two magnetic layers having a non-magnetic layer disposed therebetween in a GMR magnetic memory device.
- The MRAM using the SPMT utilizes the phenomenon that larger current transmission is generated when spin directions are identical in two magnetic layers having an insulating layer therebetween in a magnetic permeable junction memory device.
- However, MRAM research is still in its early stage, and mostly concentrated on the formation of multi-layer magnetic thin films, less on the researches on a unit cell structure and a peripheral sensing circuit.
- FIG. 1 is a cross-sectional diagram illustrating a conventional MRAM. A
gate electrode 33, namely a first word line is formed on asemiconductor substrate 31. - Source/
drain junction regions semiconductor substrate 31 at both sides of thefirst word line 33. Aground line 37 a and a firstconductive layer 37 b are formed to contact the source/drain junction regions ground line 37 a is formed in a patterning process of the firstconductive layer 37 b. - Thereafter, a first interlayer
insulating film 39 is formed to planarize the whole surface of the resultant structure, and afirst contact plug 41 is formed to expose the firstconductive layer 37 b. - A second conductive layer which is a
lower read layer 43 contacting thefirst contact plug 41 is patterned. - A second interlayer
insulating film 45 is formed to planarize the whole surface of the resultant structure, and a second word line which is awrite line 47 is formed on the second interlayerinsulating film 45. - A third interlayer
insulating film 48 is formed to planarize the upper portion of the second word line which is thewrite line 47. Asecond contact plug 49 is formed to contact the secondconductive layer 43. - A
seed layer 51 is formed into contact thesecond contact plug 49. Here, theseed layer 51 is formed to overlap between the upper portion of thesecond contact plug 49 and the upper portion of thewrite line 47. - Thereafter, a semi-ferromagnetic layer (not shown), a pinned
ferromagnetic layer 55, atunnel junction layer 57 and a freeferromagnetic layer 59 are stacked on theseed layer 51, thereby forming a magnetic tunnel junction (MTJ) cell 100 to have a pattern size as large as thewrite line 47 and to overlap thewrite line 47. - At this time, the semi-ferromagnetic layer prevents the magnetization direction of the pinned layer from being changed, and the magnetization direction of the
tunnel junction layer 57 fixed to one direction. The magnetization direction of the freeferromagnetic layer 59 can be changed by external magnetic field, and information of ‘0’ or ‘1’ can be stored according to the magnetization direction of the freeferromagnetic layer 59. - A fourth
interlayer insulating film 60 is formed over the resultant structure, and planarized to expose the freeferromagnetic layer 59. An upper read layer, namely abit line 61 is formed to contact the freeferromagnetic layer 59. - FIG. 2 is a detailed cross-sectional diagram illustrating portion of FIG. 1.
- Referring to FIG. 2, the
second word line 47 and theseed layer 51 maintain an interval of ‘d’, and the pinnedferromagnetic layer 55, thetunnel junction layer 57 and the freeferromagnetic layer 59 are stacked on theseed layer 51, thereby forming the MTJ cell. - Here, ‘d’ is formed in the third
interlayer insulating film 48, and has a size ranging from 1000 to 2000 Å. - As described above, the conventional memory device and fabrication method therefor have a disadvantage in that a distance between the
seed layer 51 of the lower portion of the MTJ cell 100 of the MRAM and thesecond word line 47 positioned therebelow is high, and thus power consumption is increased in a write operation. - Accordingly, a memory device and a fabrication method therefor are disclosed which can perform a write operation with a small current by decreasing a distance between an MTJ cell and a second word line which is a write line.
- A disclosed memory device comprises: a write line formed on a semiconductor substrate; an oxide film formed on the surface of the write line; a seed layer contacting the oxide film; and an MTJ cell contacting the upper portion of the seed layer, and being overlapped with the write line.
- A disclosed method for fabricating a memory device comprises: forming a write line on a semiconductor substrate; forming an oxide film by oxidizing the surface of the write line; forming a seed layer to contact the oxide film on the write line; and forming an MTJ cell to contact the upper portion of the seed layer, being overlapped with the write line.
- In a refinement, a write operation is performed with a small current by reducing a distance between the second word line which is a write line and the MTJ cell. The oxide film is formed with a thickness ranging from about 100 to about 500 Å by oxidizing the surface of the write line, or depositing an oxide film on the surface of the write line.
- The disclosed devices and methods will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the disclosure, wherein:
- FIG. 1 is a cross-sectional view illustrating sequential steps of a conventional method for fabricating a memory device;
- FIG. 2 is a detailed view illustrating a portion of FIG. 1; and
- FIG. 3 is a cross-sectional view illustrating a method for fabricating a memory device in accordance with the disclosure.
- A memory device and a fabrication method therefor in accordance with a preferred embodiment will now be described in detail with reference to the accompanying drawings.
- FIG. 3 is a cross-sectional diagram illustrating a method for fabricating the memory device in accordance with a preferred embodiment.
- Referring to FIG. 3, a
second word line 101 is formed on the secondinterlayer insulating film 45 of FIG. 1 by patterning. Here, thesecond word line 101 is formed by using an element selected from the group consisting of tungsten, aluminum, copper and combinations thereof for easy surface oxidation. - Thereafter, a third interlayer
insulating film 102 is formed and planarized to expose thesecond word line 101. Here, the thirdinterlayer insulating film 102 is formed by using an insulating film having a low dielectric constant. The third interlayerinsulating film 102 is formed to cover thesecond word line 101, and then evenly etched by a chemical mechanical polishing process, thereby exposing thesecond word line 101. - The exposed surface of the
second word line 101 is oxidized to form anoxide film 103 having a thickness ranging from about 100 to about 500 Å. Here, theoxide film 103 is composed of an insulating film such as a nitride film or alumina. When thesecond word line 101 is formed with copper, the surface is hardly oxidized due to strong oxidation resistance of copper, and thus a CVD oxide film is preferable. Theoxide film 103 has a different dielectric constant from a peripheral insulating film formed as an interlayer insulating film. The alumina has a higher dielectric constant than the general interlayer insulating film. - A seed layer105 is formed on the
second word line 101 including theoxide film 103, and an MTJ cell having a stacked structure of a pinnedferromagnetic layer 107, atunnel junction layer 109 and a free ferromagnetic layer 111 is formed thereon. - Since the
oxide film 103 is thinly formed, the write operation can be performed with a small current. - In another preferred embodiment, a planarized
interlayer insulating film 120 exposing theoxide film 103 is formed after the formation process of theoxide film 103, and a seed layer 105 and an MTJ cell are formed on the resultant planarized structure. - As discussed earlier, the write operation can be performed with a small current by reducing the distance between the second word line and the MTJ cell, thereby improving the property of the device.
- As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiment is not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the metes and bounds of the claims, or equivalences of such metes and bounds are therefore intended to be embraced by the appended claims.
Claims (10)
1. A memory device comprising:
a write line formed on a semiconductor substrate;
an oxide film formed on a surface of the write line;
a seed layer contacting the oxide film; and
an MTJ cell contacting the seed layer, the seed layer being sandwiched between the oxide film and MTJ cell.
2. The device according to claim 1 , wherein the oxide film is selected from the group consisting of alumina, nitride film, CVD oxide film, and combinations thereof.
3. The device according to claim 1 , wherein the oxide film has a thickness ranging from about 100 to about 500 Å.
4. A method for fabricating a memory device, comprising the steps of:
forming a write line on a semiconductor substrate;
forming an oxide film by oxidizing a surface of the write line;
forming a seed layer in contact with the oxide film; and
forming an MTJ cell in contact with the seed layer.
5. The method according to claim 4 , wherein the write line is selected from the group consisting of tungsten, aluminum, copper, and combinations thereof.
6. The method according to claim 4 , wherein the oxide film has a thickness ranging from about 100 to about 500 Å.
7. The method according to claim 4 , wherein the oxide film is selected from the group consisting of alumina, nitride film, CVD oxide film, and combinations thereof.
8. A memory device comprising:
a semiconductor substrate;
a write line disposed on the semiconductor substrate:
an oxide film coating on top of the write line;
a seed layer stacked on top of the oxide film; and
a MTJ cell stacked on top of the seed layer.
9. The device according to claim 8 , wherein the oxide film is selected from the group consisting of alumina, nitride film, CVD oxide film, and combinations thereof.
10. The device according to claim 8 , wherein the oxide film has a thickness ranging from about 100 to about 500 Å.
Applications Claiming Priority (2)
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KR10-2000-0083819A KR100390977B1 (en) | 2000-12-28 | 2000-12-28 | A method for forming a semiconductor device |
KR2000-83819 | 2000-12-28 |
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US20020109167A1 true US20020109167A1 (en) | 2002-08-15 |
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US10/026,834 Expired - Lifetime US6465262B2 (en) | 2000-12-28 | 2001-12-27 | Method for manufacturing a semiconductor device |
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US (2) | US20020109167A1 (en) |
JP (1) | JP2002246569A (en) |
KR (1) | KR100390977B1 (en) |
TW (1) | TWI228797B (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040100818A1 (en) * | 2002-11-22 | 2004-05-27 | Hiroaki Yoda | Magnetic random access memory |
US20050014297A1 (en) * | 2002-01-16 | 2005-01-20 | Hasan Nejad | Methods of forming magnetoresistive memory devices and assemblies |
US8570799B2 (en) | 2011-08-16 | 2013-10-29 | Intel Mobile Communications GmbH | Magnetic random access memory with conversion circuitry |
US20150236071A1 (en) * | 2012-09-21 | 2015-08-20 | Korea University Research And Business Foundation | Magnetic memory device using in-plane current and electric field |
US9997699B2 (en) | 2015-09-18 | 2018-06-12 | Samsung Electronics Co., Ltd. | Semiconductor device having magnetic tunnel junction structure and method of fabricating the same |
CN111816760A (en) * | 2019-04-11 | 2020-10-23 | 上海磁宇信息科技有限公司 | Magnetic random access memory magnetic storage unit and forming method thereof |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8435830B2 (en) | 2009-03-18 | 2013-05-07 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor devices |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5650958A (en) * | 1996-03-18 | 1997-07-22 | International Business Machines Corporation | Magnetic tunnel junctions with controlled magnetic response |
US5946228A (en) * | 1998-02-10 | 1999-08-31 | International Business Machines Corporation | Limiting magnetic writing fields to a preferred portion of a changeable magnetic region in magnetic devices |
US6114719A (en) * | 1998-05-29 | 2000-09-05 | International Business Machines Corporation | Magnetic tunnel junction memory cell with in-stack biasing of the free ferromagnetic layer and memory array using the cell |
US6183859B1 (en) * | 1998-07-20 | 2001-02-06 | Motorola, Inc | Low resistance MTJ |
US6034887A (en) * | 1998-08-05 | 2000-03-07 | International Business Machines Corporation | Non-volatile magnetic memory cell and devices |
US6219212B1 (en) * | 1998-09-08 | 2001-04-17 | International Business Machines Corporation | Magnetic tunnel junction head structure with insulating antiferromagnetic layer |
US6611405B1 (en) * | 1999-09-16 | 2003-08-26 | Kabushiki Kaisha Toshiba | Magnetoresistive element and magnetic memory device |
US6473336B2 (en) * | 1999-12-16 | 2002-10-29 | Kabushiki Kaisha Toshiba | Magnetic memory device |
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2000
- 2000-12-28 KR KR10-2000-0083819A patent/KR100390977B1/en not_active IP Right Cessation
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2001
- 2001-12-21 TW TW090131829A patent/TWI228797B/en not_active IP Right Cessation
- 2001-12-27 US US10/033,013 patent/US20020109167A1/en not_active Abandoned
- 2001-12-27 JP JP2001397230A patent/JP2002246569A/en active Pending
- 2001-12-27 US US10/026,834 patent/US6465262B2/en not_active Expired - Lifetime
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050014297A1 (en) * | 2002-01-16 | 2005-01-20 | Hasan Nejad | Methods of forming magnetoresistive memory devices and assemblies |
US20070020774A1 (en) * | 2002-01-16 | 2007-01-25 | Hasan Nejad | Methods of utilizing magnetoresistive memory constructions |
US20040100818A1 (en) * | 2002-11-22 | 2004-05-27 | Hiroaki Yoda | Magnetic random access memory |
US6927468B2 (en) | 2002-11-22 | 2005-08-09 | Kabushiki Kaisha Toshiba | Magnetic random access memory |
US8570799B2 (en) | 2011-08-16 | 2013-10-29 | Intel Mobile Communications GmbH | Magnetic random access memory with conversion circuitry |
US8848437B2 (en) | 2011-08-16 | 2014-09-30 | Intel Mobile Communications GmbH | Magnetic random access memory |
US20150236071A1 (en) * | 2012-09-21 | 2015-08-20 | Korea University Research And Business Foundation | Magnetic memory device using in-plane current and electric field |
US9997699B2 (en) | 2015-09-18 | 2018-06-12 | Samsung Electronics Co., Ltd. | Semiconductor device having magnetic tunnel junction structure and method of fabricating the same |
US10211396B2 (en) | 2015-09-18 | 2019-02-19 | Samsung Electronics Co., Ltd. | Semiconductor device having magnetic tunnel junction structure and method of fabricating the same |
CN111816760A (en) * | 2019-04-11 | 2020-10-23 | 上海磁宇信息科技有限公司 | Magnetic random access memory magnetic storage unit and forming method thereof |
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US6465262B2 (en) | 2002-10-15 |
US20020086448A1 (en) | 2002-07-04 |
KR100390977B1 (en) | 2003-07-12 |
JP2002246569A (en) | 2002-08-30 |
KR20020054655A (en) | 2002-07-08 |
TWI228797B (en) | 2005-03-01 |
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