KR20040041337A - Magnetic memory having novel structure and operation method, and method of fabricating the same - Google Patents

Abstract

PURPOSE: A magnetic memory having a new structure and operation method is provided, which is proper to large integration and reduces process steps. CONSTITUTION: A plurality of magnetic tunneling junctions(MTJ)(150) are arranged on a semiconductor substrate(100). A gate insulator pattern and a gate electrode are stacked on the magnetic tunneling junctions and the semiconductor substrate in sequence. And word lines are arranged on the magnetic tunneling junctions, and connect the magnetic tunneling junctions along one direction. The magnetic tunneling junction is formed with a pinning layer(142), a fixed layer(144), an insulator(146) and a free layer(148).

Description

Magnetic memory having novel structure and operation method and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a magnetic memory using a magnetic tunnel junction (MTJ) and a method for manufacturing the same.

BACKGROUND With the development of the electronics industry such as mobile communication and computers, there is an increasing demand for semiconductor devices having various functions and excellent performances. However, currently used memory devices such as static random access memory (SRAM), DRAM (dynamic RAM), flash memory (FLASH memory) and ferroelectric memory (FeRAM, ferroelectric RAM), and the like are the various functions and It does not meet excellent performance at the same time. That is, since the memory devices have the advantages and disadvantages as shown in Table 1 below, they do not meet all the characteristics required in the electronic device.

SRAM DRAM FLASH FeRAM MRAM READ high speed Medium speed high speed Medium speed Medium to high speed WRITE high speed Medium speed sleaze Medium speed Medium to high speed Non-volatility none none has exist middle has exist Refresh Unnecessary need Unnecessary Unnecessary Unnecessary Size of Unit Cell versus small small medium small Low Voltage for Operation possible There is a limit impossible There is a limit possible

FIG. 1A is a circuit diagram illustrating a unit cell of a full CMOS type SRAM using a p-channel MOSFET as a pull-up device. The SRAM has advantages of very fast read and write speeds or low power consumption. However, the SRAM, as shown in the figure, is difficult to be highly integrated since a unit cell is composed of six transistors.

1B is a circuit diagram illustrating a cell array of a conventional DRAM. As shown, since the unit cell of the DRAM is composed of one transistor and one capacitor, the area is approximately 10F ² (F represents a minimum feature size) which is much smaller than the SRAM. Therefore, the DRAM is more easily integrated than the SRAM. However, the DRAM requires a refresh operation every few milliseconds to prevent loss of information due to leakage of charge.

On the other hand, as the demand for portable electronic devices increases, non-volatility, which maintains stored information regardless of power supply, is another characteristic required in memory devices. However, the SRAM and DRAM are non-volatile. Accordingly, in the field of portable electronic devices, interest in flash memories and ferroelectric memories having non-volatility is increasing.

1C is a circuit diagram illustrating a cell array of a typical NAND flash memory. Since the NAND-type flash memory has no cell capacitor and no contact for each unit cell, the unit cell area is 4 to 8F ² smaller than the unit cell area of the DRAM. Accordingly, the NAND type flash memory is understood to be the most easily integrated memory device. However, as is known, the flash memory has a disadvantage in that an operating voltage of 5 to 12V is high in write mode, and in particular, an erase speed is slow. In addition, a pumping circuit disposed in a peripheral circuit to increase the operating voltage prevents high integration of the flash memory. In addition, the flash memory has a disadvantage in that the number of reuse is limited to approximately 10 ⁵ to 10 ⁶ times.

The cell structure of another nonvolatile memory, a ferroelectric memory, is composed of one transistor and one capacitor, similar to a DRAM unit cell. On the other hand, the ferroelectric memory has a nonvolatile property by forming the capacitor with a ferroelectric material, but a rewriting is required for each read because of the destructive nature of the read operation. In addition, the ferroelectric memory is limited in the number of reusable, has a medium operating speed. In addition, difficulties in ferroelectric materials, such as high reactivity with hydrogen, the need for high temperature annealing and the scaling of cell area / cell voltage, remain technical challenges to develop for ferroelectric memory. have.

In contrast, MRAM (magnetic RAM or magnetoresistive RAM) is non-volatile, there is no limit on the number of reuse, it is easy to high integration, and has the advantages of high speed operation and low voltage operation.

Hereinafter, the structure of the MRAM according to the prior art will be described with reference to FIGS. 2 to 4. FIG. 2 is a plan view showing a part of a cell array of an MRAM according to the prior art, and FIG. 3 shows a cross section taken along the line II ′ of FIG. 2. 4 is a perspective view illustrating a structure of an MRAM according to the prior art.

2 to 4, an isolation layer 12 is disposed in a predetermined region of the semiconductor substrate 10 to define the active regions 11. A plurality of gate electrodes 15, that is, a plurality of word lines are disposed across the active regions 11 and the device isolation layer 12. Each of the active regions 11 perpendicularly intersects the pair of gate electrodes 15. That is, when the direction of the active regions 11 is referred to as the row direction (x-axis direction), the gate electrodes 15 are disposed in the column direction (y-axis direction). The common source region 16s is disposed in the active region 11 between the gate electrodes 15, and the drain region 16d is disposed in the active regions 11 at both sides of the common source region 16s. do. Accordingly, cell transistors are formed at points where the active regions 11 and the gate electrodes 15 intersect.

The entire surface of the semiconductor substrate having the cell transistor is covered with an interlayer insulating film 20. In the interlayer insulating layer 20, a plurality of digit lines 30 parallel to the gate electrodes 15 are disposed. On the interlayer insulating layer 20 and the digit lines 30, a plurality of bit lines 50 that cross the gate electrode 15, that is, parallel to the active region 11 are disposed. Magnetic tunnel junctions (MTJs) 40 are disposed between the bit line 50 and the digit line 30. A lower electrode 35 extending above the drain region 16d is disposed between the magnetic tunnel junction 40 and the digit line 30. The magnetic tunnel junction 40 is in direct contact with the upper surface of the lower electrode 35 and the lower surface of the bit line 50. In the interlayer insulating film 20, a vertical wiring 25 electrically connecting the lower electrode 35 and the drain region 16d is disposed. The vertical wiring 25 may include a plurality of plugs sequentially stacked. The source plug 26 and the source line 28 are sequentially connected to the upper portion of the common source region 16s.

The basic structure of the magnetic tunnel junction 40 includes a pinning layer 42, a fixed layer 44, an insulating layer 46, and a free layer 48. The resistance of the magnetic tunnel junction 40 varies greatly depending on whether the magnetization direction between the free layer 48 and the pinned layer 44 is in the same or reverse direction. The resistance characteristic of the magnetic tunnel junction 40, which depends on the magnetization direction, is used as the mechanism of information storage of the MRAM. The magnetization direction of the pinned film 44 does not change during a normal read / write operation. The pinning layer 42 serves to fix the magnetization direction of the pinned layer 44 and may be formed of a plurality of layers. In contrast, the free layer 48 may change with respect to the magnetization direction of the pinned layer 44, and the allowable magnetization direction is the same as or opposite to the magnetization direction of the pinned layer 44.

The process of reading information stored in a specific cell is possible by selecting the word line 15 and the bit line 50 and then measuring the current flowing therethrough. At this time, the magnitude of the current has a large difference according to the magnetization direction between the two magnetic films 44 and 48. The difference in current magnitude represents the difference in stored information. In contrast, the process of changing the magnetization direction of the free layer 48, that is, the process of recording information, may be performed by adjusting the magnetic field formed by the current flowing through the bit line 50 and the digit line 30.

As described above, the magnetic memory according to the prior art forms the word line 15, the digit line 30, the magnetic tunnel junction 40 and the bit line 50 all in different height layers. Accordingly, the vertical height of the magnetic memory is high, and the process steps for forming it are complicated. In addition, the magnetic memory shown in FIG. 2 has a unit cell area of approximately 16F ² , which is wider than the unit cell area of the DRAM described above. In order to increase the commercial value of the magnetic memory, a magnetic memory having a structure that can be more integrated is required.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a magnetic memory having a structure and an operation method which are easy to integrate.

Another object of the present invention is to provide a method of manufacturing a magnetic memory capable of reducing process steps.

1A is a circuit diagram illustrating a unit cell of a conventional full CMOS type SRAM.

1B is a circuit diagram illustrating a cell array of a conventional DRAM.

1C is a circuit diagram illustrating a cell array of a typical NAND flash memory.

2 is a plan view showing a portion of a cell array of a magnetic memory (MRAM) according to the prior art.

3 is a process cross-sectional view showing a cell array of a magnetic memory according to the prior art.

4 is a perspective view illustrating a structure of a magnetic memory having a magnetic tunnel junction (MTJ) according to the related art.

5 through 12 are cross-sectional views illustrating a method of forming a magnetic memory according to example embodiments.

13 is a plan view illustrating a portion of a cell array of a magnetic memory according to embodiments of the present invention.

14A and 14B are circuit diagrams illustrating a cell array of a magnetic memory according to embodiments of the present invention.

15 is a perspective view showing a magnetic memory according to a preferred embodiment of the present invention.

In order to achieve the above technical problem, the present invention provides a magnetic memory in which the gate electrode, the magnetic tunnel junction and the word line in turn contact. The magnetic memory includes a plurality of magnetic tunnel junctions disposed on a semiconductor substrate, a gate insulating layer pattern and a gate electrode sequentially stacked between the magnetic tunnel junctions and the semiconductor substrate, and the magnetic tunnel junctions. Word lines connecting the tunnel junctions in one direction.

At this time, the magnetic tunnel junction is preferably composed of a pinning film, a fixed film, an insulating film and a free film stacked in sequence. In addition, the vertical lines of the magnetic tunnel junctions may further include digit lines crossing the word lines. The gate electrode extends to connect a plurality of magnetic tunnel junctions arranged in a direction perpendicular to the word line. In this case, an isolation layer defining an active region may be further disposed below the extended gate electrode.

On the other hand, the gate insulating film is preferably a thickness of 2 to 100 Å so that leakage current can occur. In addition, a source / drain region is further disposed on the semiconductor substrate next to the gate electrode. In this case, the source / drain regions form a bit line connected in one direction while crossing the word line.

The magnetic memory according to the present invention described above has a different operation scheme from that in the prior art. In particular, according to the present invention, there is provided a cell transistor formed on a semiconductor substrate having a gate electrode, a source region and a drain region, a word line connected to the gate electrode, and a magnetic tunnel junction interposed between the gate electrode and the word line. In the operating method of the magnetic memory provided, the process of reading the information recorded in the magnetic tunnel junction includes the following steps. A read voltage is applied to the word line to form a current path through the magnetic tunnel junction, the gate electrode, and the semiconductor substrate, and then the current flowing through the drain region is measured. In this case, the voltage applied to the gate electrode corresponds to the magnitude of the read voltage dropped in the magnetic tunnel junction. Accordingly, the voltage of the gate electrode for adjusting the on / off state of the cell transistor is adjusted according to the resistance of the magnetic tunnel junction.

To this end, the process of reading the information recorded in the magnetic tunnel junction applies the read voltage to the word line while forming a potential difference between the source region and the drain region.

Meanwhile, the process of writing information to the magnetic tunnel junction preferably uses a magnetic field formed by currents flowing through the word line and the digit line, respectively, and is formed by currents flowing through the word line and the gate electrode, respectively. Magnetic fields can also be used.

In order to achieve the above technical problem, a method of manufacturing a magnetic memory for connecting a gate electrode, a magnetic tunnel junction, and a word line without using a plug is provided. The method forms a gate insulating film, a gate electrode and a magnetic tunnel junction sequentially stacked on a semiconductor substrate, forms an impurity region in an active region between the gate electrodes, and then traverses the impurity region and the gate electrodes. Forming a word line connecting to top surfaces of the magnetic tunnel junctions.

The forming of the gate insulating film, the gate electrode and the magnetic tunnel junction may include forming a gate insulating film on the semiconductor substrate, forming a gate conductive film on the gate insulating film, and forming a magnetic tunnel bonding film on the gate conductive film. And patterning the magnetic tunnel junction layer to form a magnetic tunnel junction layer pattern parallel to the word line. Thereafter, the magnetic tunnel junction layer pattern, the gate conductive layer, and the gate insulating layer may be patterned in a direction perpendicular to the word line. At this time, in view of the operating method of the present invention in which the current path is formed by using the leakage current of the gate insulating film, it is preferable that the gate insulating film is formed to a thickness of 2 to 100 mA.

Meanwhile, the magnetic tunnel junction is formed of at least three material films selected from ferromagnetic materials, antiferromagnetic materials, insulating films containing metal oxides of silicon, and platinum group metal materials.

Before forming the word line, it is preferable to form a lower interlayer insulating film covering the entire surface of the semiconductor substrate including the impurity region, and then etch the lower interlayer insulating film to expose the upper surface of the magnetic tunnel junction. On the other hand, after the word line is formed, an upper interlayer insulating film is formed to cover the entire surface of the semiconductor substrate including the word line, and the vertical interlayer of the magnetic tunnel junction is formed on the upper interlayer insulating film while crossing the word line. Forming digit lines to be disposed may further be performed. In addition, before forming the gate insulating layer, an isolation layer may be further formed on the semiconductor substrate between the word lines to define an active region.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the invention will be fully conveyed to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. If it is also mentioned that the layer is on another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween.

11 is a plan view illustrating a portion of a cell array of a magnetic memory according to embodiments of the present invention. 5, 6A, and 6A are cross-sectional views illustrating a cross section taken along line II ′ of FIG. 11 to explain a method of forming a magnetic memory according to a first embodiment of the present invention.

11 and 5, a gate insulating film, a gate conductive film, and a magnetic tunnel junction film are sequentially formed on the semiconductor substrate 100, and then patterned sequentially to form a plurality of parallel gate patterns. The gate patterns each include a gate insulating layer 125, a gate electrode 135, and a magnetic tunnel junction layer 140 that are sequentially stacked. The magnetic tunnel junction layer 140 may be formed of a pinning layer 142, a pinning layer 144, an insulating layer 146, and a free layer 148 that are sequentially stacked.

The pinning layer 142 may be formed of anti-ferromagnetic layers such as IrMn, PtMn, MnO, MnS, MnTe, MnF ₂ , FeF ₂ , FeCl ₂ , FeO, CoCl ₂ , CoO, NiCl ₂ , NiO, Cr, and the like. It is preferable to form at least one selected from). The pinned layer 144 and the free layer 148 are Fe, Co, Ni, Gd, Dy, MnAs, MnBi, MnSb, CrO ₂ , MnOFe ₂ O ₃ , FeOFe ₂ O ₃ , NiOFe ₂ O ₃ , CuOFe ₂ It is preferable to form at least one selected from ferromagnetic layers such as O ₃ , MgOFe ₂ O ₃ , EuO, and Y ₃ Fe ₅ O ₁₂ . In particular, the pinned layer 144 may have a three-layer structure in which a platinum group metal film such as ruthenium (Ru) is further interposed between the above-described ferromagnetic materials. The insulating layer 146 may be formed of one material selected from metal oxide films including an aluminum oxide film.

It is preferable to form the gate spacer 160 on the side surface of the gate pattern. After forming the gate spacer 160, an ion implantation process is performed to form impurity regions 170 in the semiconductor substrate 100 between the gate patterns. The impurity region 170 is used as a source / drain region of a cell transistor. In addition, according to the present invention, the impurity region 170 is used as a bit line for selecting a specific cell. However, in this step, the impurity regions 170 are formed in parallel between the gate patterns. Accordingly, even if one of the impurity regions 170 and the gate electrodes 135 is selected, as in a conventional cell selection method, a specific cell transistor cannot be selected. For this selection operation, a word line crossing the impurity regions 170 must be formed.

Referring to FIG. 6A, a lower interlayer insulating layer 180 is formed on an entire surface of the semiconductor substrate on which the impurity region 170 is formed. Thereafter, the lower interlayer insulating layer 180 is planarized and etched until the upper surface of the magnetic tunnel junction layer 140 is exposed. The planarization etching of the lower interlayer insulating layer 180 may be performed using chemical mechanical polishing (CMP) technology. In this case, in order to prevent the etching damage from the magnetic tunnel junction layer 140, another buffer layer may be further formed on the magnetic tunnel junction layer 140.

A first conductive film is formed on the entire surface of the semiconductor substrate including the magnetic tunnel junction film 140. Subsequently, the first conductive layer is patterned to form a plurality of word lines 190 that cross the gate patterns. The word line 190 is formed to directly contact the upper surface of the exposed magnetic tunnel junction layer 140. As described above, the word line 190 is used in a process of selecting a specific cell transistor.

The patterning process for forming the word line 190 may be performed by using an etching recipe having an etching selectivity with respect to the lower interlayer insulating layer 180. In addition, the etching recipe may have an etching selectivity with respect to the insulating layer 146, but may not have an etching selectivity with respect to the free layer 148. Accordingly, while the word line 190 is formed, the free layer 146 exposed between the word lines 190 is etched. As a result, the free layer 146 is two-dimensionally arranged in regions where the word line 190 and the gate pattern cross each other. The two-dimensionally arranged free layer 148 ′ is disconnected between adjacent cells, so that the magnetic tunnel junction layer 140 forms a magnetic tunnel junction 150 that is used as a storage location of the magnetic memory. In this case, the pinned layer 144 and the pinning layer 142 are connected between adjacent cells.

Referring to FIG. 7A, an upper interlayer insulating layer 200 having a planarized upper surface is formed on an entire surface of a semiconductor substrate including the word lines 190. To this end, the forming of the upper interlayer insulating film 200 preferably includes depositing the upper interlayer insulating film 200 and planarizing the deposited upper interlayer insulating film 200. The upper interlayer insulating layer 200 is preferably thicker than the word line 190, and the difference in height at this time has an important effect on the characteristics of the magnetic memory. Therefore, it is desirable to strictly control the difference in height.

Digit lines 210 may be formed on the upper interlayer insulating layer 200 while crossing the word lines 190 and disposed vertically above the magnetic tunnel junction 140. The digital lines 210 form a current path through which a predetermined current flows in recording information. Meanwhile, an embodiment in which the digit line is not formed may be possible depending on a method of operating a magnetic memory. This will be described in detail later with reference to FIGS. 12 to 13 in association with a new operation method of the magnetic memory.

The magnetic memory thus formed is subjected to three photographic processes in the step of forming the gate pattern, the word line and the digit line. This can simplify the manufacturing process compared to the prior art, which requires the formation of vertical wires such as plugs to connect the lines. In particular, with the fact that the number of expensive photo processes can be minimized, and that the embodiments without forming the digit lines can be made possible, the manufacturing cost of the magnetic memory can be drastically reduced in accordance with the present invention.

6B and 7B are cross-sectional views illustrating a method of forming a magnetic memory according to a second exemplary embodiment of the present invention, and are cross-sectional views illustrating a cross section taken along the line II ′ of FIG. 11. Since this embodiment is similar to the first embodiment described above, a description will be given of a patterning process of the word line 190, which is different in the forming method.

6B, 7B, and 11, the etching recipe used in the patterning process for forming the word line 190 has an etching selectivity with respect to the lower interlayer insulating layer 180, and the magnetic tunnel junction layer 140. ) And the gate electrode 135 preferably have no etching selectivity. Accordingly, the magnetic tunnel junction layer 140 and the gate electrode 135 between the word lines 190 are etched while the word line 190 is formed. As a result, the magnetic tunnel junction 150 and the gate electrode 135 exposing the gate insulating layer 125 are two-dimensionally arranged in regions where the word line 190 and the gate pattern cross each other. In this case, as illustrated, the gate insulating layer 125 may be etched to a thin thickness to expose the semiconductor substrate.

8 to 10 are process cross-sectional views illustrating a method of forming a magnetic memory according to a third exemplary embodiment of the present invention, and are process cross-sectional views illustrating a cross section taken along the line II ′ of FIG. 11.

8 to 10, in the first embodiment described above, the device isolation film 105 is formed on the semiconductor substrate under the gate electrode 135 and at the same time between the word lines 190. It is characterized in that it further comprises the step of forming. As a result, the location where the device isolation layer 105 is formed is a region where the free layer 148 is etched during the patterning process for forming the word line 190 in the first embodiment. The device isolation layer 105 serves to define an active region, and is preferably formed using conventional trench device isolation techniques.

Process steps except this are according to the first embodiment. The method of forming the device isolation film 105 is also applicable to the second embodiment in which gate electrodes are formed two-dimensionally by being disconnected from adjacent cells. Such modified embodiments will be apparent to those skilled in the art to a degree that can be easily implemented, and thus detailed descriptions thereof will be omitted.

12A and 12B are circuit diagrams illustrating a cell array of a magnetic memory according to embodiments of the present invention. 13 is a perspective view showing a magnetic memory according to a preferred embodiment of the present invention.

12A, 12B, and 13, a plurality of magnetic tunnel junctions 150 arranged in two dimensions are disposed on the semiconductor substrate 100. The magnetic tunnel junction 150 includes a pinning layer 142, a fixed layer 144, an insulating layer 146, and a free layer 148 that are sequentially stacked. The pinning layer 142 may be formed of anti-ferromagnetic layers such as IrMn, PtMn, MnO, MnS, MnTe, MnF ₂ , FeF ₂ , FeCl ₂ , FeO, CoCl ₂ , CoO, NiCl ₂ , NiO, Cr, and the like. It is preferred that at least one selected from The pinned layer 144 and the free layer 148 are Fe, Co, Ni, Gd, Dy, MnAs, MnBi, MnSb, CrO ₂ , MnOFe ₂ O ₃ , FeOFe ₂ O ₃ , NiOFe ₂ O ₃ , CuOFe ₂ It is preferably made of at least one selected from ferromagnetic layers such as O ₃ , MgOFe ₂ O ₃ , EuO and Y ₃ Fe ₅ O ₁₂ . In particular, the pinned layer 144 may have a three-layer structure in which a ruthenium layer Ru is further interposed between the above-described ferromagnetic materials. The insulating film 146 is preferably an aluminum oxide film.

A gate insulating layer 125 and a gate electrode 135, which are sequentially stacked, are interposed between the semiconductor substrate 100 and the magnetic tunnel junction 150. The gate insulating layer 125 may have a thickness of about 5 to about 100 kW so that current may flow to the semiconductor substrate 100 at a typical read voltage applied through the gate electrode 135. In addition, the gate insulating layer 125 may be formed of one selected from high dielectric films including a silicon oxide film, a silicon oxynitride film, and an oxide of a metal.

The gate electrode 135 may connect the magnetic tunnel junctions 150 arranged in two directions in one direction. An isolation layer defining an active region may be disposed in the semiconductor substrate 100 between the magnetic tunnel junctions 150 connected by the gate electrode 135. A method of forming a magnetic memory having the device isolation film has been described with reference to FIGS. 8 to 11. Meanwhile, the gate electrode 135 may be arranged two-dimensionally, similarly to the magnetic tunnel junctions 150 (see FIG. 7B). In this case, the gate electrode 135 may be disposed under the magnetic tunnel junction 150 while having an island shape.

Impurity regions 170 used as source / drain regions are disposed in one direction between the gate electrodes 135. The impurity region 170 is parallel to the gate electrode 135 connecting the magnetic tunnel junctions 150. The gate electrodes 135 and the impurity regions 170 constitute cell transistors of a magnetic memory according to the present invention. In this case, the impurity region 170 may be used as a bit line for selecting the cell transistor. However, since the gate electrode 135 is disposed in a direction parallel to the impurity region 170 or disconnected from each other, the gate electrode 135 may not be used as a word line unlike in a conventional semiconductor device.

A lower interlayer insulating layer exposing the top surface of the magnetic tunnel junction 150 is disposed on the semiconductor substrate including the impurity regions 170. On the lower interlayer insulating layer, a plurality of word lines 190 is formed to contact the exposed upper surfaces of the magnetic tunnel junctions 150. The word lines 190 are disposed in a direction crossing the impurity regions 170. An upper interlayer insulating layer is disposed on the semiconductor substrate including the word lines 190. A plurality of digit lines 210 disposed in a direction crossing the word lines 190 may be disposed on the upper interlayer insulating layer. The digit lines 210 may be disposed to pass vertically above the magnetic tunnel junction 150. According to the present invention, an embodiment without the digit line is also possible.

The above-described process of writing information by the magnetic memory includes flowing a predetermined amount of current through each of the word lines 190 and WL and the digit lines 210 and DL. The sum of the magnetic fields formed by the current flowing through the word line 190 and the digit line 210 changes the magnetization direction of the free layer 148 of the magnetic tunnel junction 150. The resistance of the magnetic tunnel junction 150 changes depending on whether the magnetization direction of the free layer 158 thus changed is parallel or opposite to the magnetization direction of the pinned layer 156. This magnetic memory differs from the conventional writing method in that the word line 190 is used for writing information. Meanwhile, the word line 190 and the gate electrode 135 may be used for the above-described writing process. Such an embodiment is possible when the gate electrode 135 is configured to connect the plurality of magnetic tunnel junctions 150.

The reading of the stored information includes applying a read voltage V _WL to the word line WL 190. As described above, the gate insulating film 125 according to the present invention is an insulating film thin enough to allow current to flow to the semiconductor substrate 100 by the voltage applied to the word line 190. In this case, the current is connected to the word line 190, WL, the magnetic tunnel junction 150, MTJ, the gate electrode 135, GATE, the gate insulating layer 125, Gox, and the semiconductor substrate 100. Flow path. As shown in FIG. 12B, when such a current path is formed, the magnetic tunnel junction 150 and the gate insulating layer 125 serve as variable resistors and fixed resistors, respectively. Accordingly, the voltage Vg applied to the gate electrode 135 through the current path is about the magnitude of the read voltage V _WL dropping by the resistance of the magnetic tunnel junction 150 (MTJ).

Meanwhile, when a potential difference is formed between the impurity regions 170 on both sides of the gate electrode 135, the magnitude of the current flowing through the channel between the impurity regions is determined by the voltage Vg of the gate electrode 135. do. The potential difference is formed by applying a voltage having a predetermined magnitude to another impurity region 170 used as a drain region (that is, the bit line BL) while grounding the impurity region 170 used as a source region. can do. At this time, by comparing the magnitude of the current flowing through the channel with the reference current amount, the information stored in the magnetic tunnel junction 150 can be read. In conclusion, according to the method of the present invention for reading stored information, after forming a current path as described above, measuring the current flowing through the cell transistor. In this case, the magnitude of the current flowing through the cell transistor is determined by the voltage applied to the gate electrode 135, and the voltage applied to the gate electrode is dependent on the resistance of the magnetic tunnel junction 150, which is a place for storing information. Is determined.

According to the present invention, there is provided a magnetic memory in which a magnetic tunnel junction is interposed between the gate electrode and the word line so that the voltage applied to the gate electrode of the MOS cell transistor can be adjusted by the information stored in the magnetic tunnel junction. Accordingly, the vertical height of the magnetic memory is reduced. In particular, by directly contacting the gate electrode, the magnetic tunnel junction, and the word line in turn, patterning processes for plug formation can be avoided. The above-described plug may unnecessarily occupy a cell area, and a patterning process or the like for forming the same includes an expensive photolithography step. As a result, the magnetic memory according to the present invention has a cell structure that is easy to be highly integrated, and can reduce manufacturing costs by reducing process steps in the manufacturing process.

Claims (19)

A plurality of magnetic tunnel junctions disposed on the semiconductor substrate; A gate insulating layer pattern and a gate electrode sequentially stacked between the magnetic tunnel junctions and the semiconductor substrate; And And word lines disposed on the magnetic tunnel junctions and connecting the magnetic tunnel junctions in one direction. The method of claim 1, The magnetic tunnel junction is composed of a pinning film, a pinned film, an insulating film, and a free film that are sequentially stacked. The method of claim 1, And digit lines disposed vertically above said magnetic tunnel junctions and crossing over said word lines. The method of claim 1, And the gate electrode extends to connect a plurality of magnetic tunnel junctions arranged in a direction perpendicular to the word line. The method of claim 4, wherein And a device isolation film further defining an active region under the extended gate electrode. The method of claim 1, And the gate insulating film has a thickness of 2 to 100 microseconds. The method of claim 1, And a source / drain region is further disposed on the semiconductor substrate next to the gate electrode. The method of claim 7, wherein And the source / drain regions form a bit line connected in one direction while crossing the word line. A cell transistor formed on a semiconductor substrate, the cell transistor having a gate electrode, a source region and a drain region, a word line connected to the gate electrode, and a magnetic tunnel junction interposed between the gate electrode and the word line. To The process of reading the information recorded in the magnetic tunnel junction Applying a read voltage to the word line to form a current path through the magnetic tunnel junction, the gate electrode and the semiconductor substrate; And Measuring a current flowing through the drain region; The read voltage drops in a current path passing through the magnetic tunnel junction and is applied to the gate electrode, and the voltage applied to the gate electrode adjusts an on / off state of the cell transistor according to the resistance of the magnetic tunnel junction. Operating method of the magnetic memory, characterized in that. The method of claim 9, The process of writing information in the magnetic tunnel junction uses a magnetic field formed by currents flowing through the word line and the digit line, respectively. The method of claim 9, The process of writing information to the magnetic tunnel junction uses a magnetic field formed by currents flowing through the word line and the gate electrode, respectively. The method of claim 9, And reading out the information recorded in the magnetic tunnel junction applies the read voltage to the word line while forming a potential difference between the source region and the drain region. Forming a gate insulating film, a gate electrode and a magnetic tunnel junction sequentially stacked on the semiconductor substrate; Forming an impurity region in an active region between the gate electrodes; And Forming a word line across the impurity region and the gate electrodes to connect to top surfaces of the magnetic tunnel junctions. The method of claim 13, Forming the gate insulating film, the gate electrode and the magnetic tunnel junction Forming a gate insulating film on the semiconductor substrate; Forming a gate conductive film on the gate insulating film; Forming a magnetic tunnel junction layer on the gate conductive layer; Patterning the magnetic tunnel junction layer to form a magnetic tunnel junction layer pattern parallel to the word line; And patterning the magnetic tunnel junction layer pattern, the gate conductive layer, and the gate insulating layer in a direction perpendicular to the word line. The method of claim 13, The gate insulating film is a method of manufacturing a magnetic memory, characterized in that formed to a thickness of 2 to 100Å. The method of claim 13, The magnetic tunnel junction is formed of at least three material films selected from a ferromagnetic material, an antiferromagnetic material, an insulating film containing silicon oxide of a metal, and a platinum group metal material. The method of claim 13, Before forming the word line, Forming a lower interlayer insulating film covering an entire surface of the semiconductor substrate including the impurity region; Etching the lower interlayer insulating film to expose an upper surface of the magnetic tunnel junction. The method of claim 13, After forming the word line, Forming an upper interlayer insulating film covering an entire surface of the semiconductor substrate including the word line; And And forming digit lines on the upper interlayer insulating layer, the digit lines disposed vertically on the magnetic tunnel junction while crossing the word lines. The method of claim 13, Before forming the gate insulating film, forming a device isolation film defining an active region on the semiconductor substrate between the word lines.