KR100399439B1 - Magnetic RAM cell and method for manufacturing the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic RAM (MRAM) cell and a method of manufacturing the same. In particular, since an MRAM cell is formed on a silicon on insulator (SOI) substrate, an MRAM cell formed on a conventional general semiconductor substrate is disclosed. Smaller junction capacities increase overall circuit speed, enable lower voltage operation, improve current drive capability, and prevent short channel effects.

Description

Magnetic RAM cell and method for manufacturing the same {Magnetic RAM cell and method for manufacturing the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic RAM (MRAM) cell and a method for manufacturing the same, and more particularly, to an MRAM cell and a method for manufacturing the same, by forming an MRAM cell on a silicon on insulator (SOI) substrate to improve device characteristics. It is about.

Most semiconductor memory manufacturers are developing MRAM using ferromagnetic materials as one of the next generation memory devices.

The MRAM is a memory device that reads and writes information by forming a ferromagnetic thin film in multiple layers to sense current change according to the magnetization direction of each thin film, and enables high speed, low power, and high integration due to the unique characteristics of the magnetic thin film. The device is capable of operating a nonvolatile memory such as a flash memory.

In the conventional MRAM cell, as shown in FIG. 1, the gate electrode, that is, the word line 33 is formed on the semiconductor substrate 31. In this case, the gate electrode is provided with a gate oxide film 32 at an interface with the semiconductor substrate 31.

The source / drain junction regions 35a and 35b are formed in both semiconductor substrates 31 of the first word line 33, and the reference voltage line 37a and the first conductive layer 37b connected thereto are formed. . In this case, the reference voltage line 37a is formed during the process of forming the first conductive layer 37b.

Next, a first interlayer insulating film 39 is formed to planarize the entire upper surface, and a first contact plug 41 is formed to expose the first conductive layer 41.

The second conductive layer, which is the lower lead layer 43 connected to the first contact plug 41, is patterned.

A second interlayer insulating film 45 is formed to planarize the entire upper surface, and a second word line 47 that is a light line is formed on the second interlayer insulating film 45.

In addition, a third interlayer insulating layer 48 is formed to planarize an upper portion of the second word line 47.

In addition, a second contact plug 49 exposing the second conductive layer 43 is formed.

In addition, a seed layer 51 connected to the second contact plug 49 is formed. In this case, the seed layer 51 is formed to overlap the second word line 47 from an upper side of the second contact plug 49.

Next, an MTJ (magnetic tunnel) is formed by stacking an antiferromagnetic layer (not shown), a fixed ferromagnetic layer 55, a tunnel barrier layer 57, and a free ferromagnetic layer 59 on the seed layer 51. junction) Cells 100 are formed, but overlap each other in the pattern size of the second word line 47.

Here, the antiferromagnetic layer serves to prevent the magnetization direction of the pinned layer from changing, and thus the pinned ferromagnetic layer 55 is fixed in one direction. The magnetization direction of the free ferromagnetic layer 59 is changed by the generated magnetic field, and information of "0" or "1" may be stored according to the magnetization direction of the free ferromagnetic layer 59.

Next, a fourth interlayer insulating film 60 is formed on the entire surface to be planarized and etched to expose the free ferromagnetic layer 59, and the upper lead layer, that is, the bit line 61, connected to the free ferromagnetic layer 59. ).

However, since the conventional MRAM cell and its manufacturing method form the MRAM cell on a general semiconductor substrate, there is a limit in the formation of the junction capacitance required for the miniaturization of the device, which reduces the overall circuit speed, makes low voltage operation difficult, and lowers the current driving capability. And short channel effects, such as deterioration of device characteristics.

The present invention has been made to solve the above problems, and since the MRAM cell is formed on the SOI substrate, the junction capacity is smaller than that of the conventional MRAM cell formed on the conventional semiconductor substrate, thereby increasing the overall circuit speed and enabling low voltage operation, and driving the current. It is an object of the present invention to provide an MRAM cell and a method of manufacturing the same, which have improved capability and prevent short channel effects.

1 is a cross-sectional view of an MRAM cell according to the prior art.

2 is a cross-sectional view showing an MRAM cell according to an embodiment of the present invention.

3A through 3D are cross-sectional views illustrating a method of manufacturing an MRAM cell according to an embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

11 silicon substrate 13 buried oxide film

15: first photosensitive film 17: silicon layer

32: gate oxide film 33: word line

35a, 35b: source / drain junction region 37a: reference voltage line

37b: first conductive layer 39: first interlayer insulating film

41: first contact plug 43: lower lead layer

45: second interlayer insulating film 47: light line

49: second contact plug 51: seed layer

55: fixed ferromagnetic layer 57: tunnel barrier layer

59: free ferromagnetic layer 60: fourth interlayer insulating film

61: bit line

The MRAM cell of the present invention comprises an SOI substrate in which a silicon substrate, a buried oxide film, and a silicon layer are stacked, and a source / drain junction region having a smaller junction capacitance than a gate electrode and a general semiconductor substrate in an MRAM cell. It is characterized by including a transistor.

In the manufacturing method of the MRAM cell of the present invention, in the method of manufacturing an MRAM cell, forming a buried oxide film on a silicon substrate, using the mask in which the buried oxide film is removed only at a portion where the source region of each cell is thermally bonded. Selectively etching, growing a silicon layer on the buried oxide layer using the silicon substrate as a seed, forming an SOI substrate from the silicon substrate, the buried oxide layer and the silicon layer, and bonding capacity to the silicon layer than the gate electrode semiconductor substrate And forming a transistor with this small source / drain junction region.

Referring to the accompanying drawings, preferred embodiments of the MRAM cell and a method of manufacturing the same according to the present invention will be described in detail as follows.

2 is a cross-sectional view illustrating an MRAM cell according to an embodiment of the present invention, and FIGS. 3A to 3D are cross-sectional views illustrating a method of manufacturing an MRAM cell according to an embodiment of the present invention.

The MRAM cell according to the embodiment of the present invention is formed on the silicon substrate 11, the SOI substrate composed of the silicon oxide layer 11, the buried oxide film 13 and the silicon layer 17, the silicon layer 17, as shown in FIG. 33) and a transistor including source / drain junction regions 35a and 35b having a smaller junction capacitance than a general semiconductor substrate.

In the method of manufacturing an MRAM cell according to an exemplary embodiment of the present invention, as shown in FIG. 3A, a buried oxide film 13 and a first photosensitive film 15 having a thickness of 1000 to 4000 kPa are sequentially formed on the silicon substrate 11.

After selectively exposing and developing the first photoresist film 15 so as to be removed only at a portion to which the source region of each cell is connected, the buried oxide film 13 using the selectively exposed and developed first photoresist film 15 as a mask. Select etching.

As shown in FIG. 3B, the first photosensitive film 15 is removed, and the silicon oxide layer 11 is seeded on the buried oxide film 13 by an epitaxial process. Silicon layer 17 is formed.

Here, the silicon substrate 11, the buried oxide film 13 and the silicon layer 17 constitutes an SOI substrate.

As shown in FIG. 3C, a gate electrode, that is, a first word line 33 is formed on the SOI substrate. In this case, the gate electrode is provided with a gate oxide film 32 at the interface with the SOI substrate.

Source / drain junction regions 35a and 35b are formed in both silicon layers 17 of the first word line 33.

As shown in FIG. 3D, a reference voltage line 37a and a first conductive layer 37b connected to the source / drain junction regions 35a and 35b are formed. In this case, the reference voltage line 37a is formed during the process of forming the first conductive layer 37b.

Next, a first interlayer insulating film 39 is formed to planarize the entire upper surface, and a first contact plug 41 is formed to expose the first conductive layer 41.

The second conductive layer, which is the lower lead layer 43 connected to the first contact plug 41, is patterned.

A second interlayer insulating film 45 is formed to planarize the entire upper surface, and a second word line 47 is formed on the second interlayer insulating film 45.

In addition, a third interlayer insulating layer 48 is formed to planarize an upper portion of the second word line 47.

In addition, a second contact plug 49 exposing the second conductive layer 43 is formed.

In addition, a seed layer 51 connected to the second contact plug 49 is formed. In this case, the seed layer 51 is formed to overlap the second word line 47 from an upper side of the second contact plug 49.

Next, an MTJ cell 100 is formed by stacking an antiferromagnetic layer (not shown), a fixed ferromagnetic layer 55, a tunnel barrier layer 57, and a free ferromagnetic layer 59 on the seed layer 51. The second word line 47 overlaps the pattern size.

Here, the anti-ferromagnetic layer serves to prevent the magnetization direction of the pinned layer from changing, and thus the pinned ferromagnetic layer 55 is fixed in one direction. In addition, the magnetization direction is changed by the generated magnetic field, and the free ferromagnetic layer 59 may store information of "0" or "1" according to the magnetization direction of the free ferromagnetic layer 59.

Next, a fourth interlayer insulating film 60 is formed over the entire surface to be planarized and etched to expose the free ferromagnetic layer 59, and the upper lead layer, that is, the bit line 61, connected to the free ferromagnetic layer 59. ).

The structure and operation of the present MRAM described above are as follows.

First, the unit cell of the MRAM has a field effect transistor including a first word line 33, which is a lead line used to read information, and an MTJ cell 100, and applies an electric current to form an external magnetic field to magnetize the MTJ cell. The second word line 47, which is a light line for determining a, and a bit line 61, which is an upper lead layer for applying a current to the MTJ cell in a vertical direction so that the magnetization direction of the free layer can be known.

Here, the operation of reading information in the MTJ cell may apply a voltage to the first word line 33, which is the lead line, to operate a field effect transistor, and sense a magnitude of a current flowing when the current is applied to the bit line 61. This is to check the magnetization direction of the free ferroelectric layer in the MTJ cell.

The operation of storing information in the MTJ cell is a magnetic field generated by applying current to the second word line 47 and the bit line 61, which are the write lines, while keeping the field effect transistor off. The magnetization direction of the free ferromagnetic layer 59 is controlled.

At this time, the reason why the current is simultaneously applied to the bit line 61 and the second word line 47 is that one cell at a point where two metal lines cross each other vertically can be selected. In addition, the operation of the MTJ cell in the MRAM will be described.

First, when a current flows in a direction perpendicular to the MTJ cell, a tunneling current flows through the insulating layer.

When the tunnel barrier layer 57 and the free ferromagnetic layer 59 have the same magnetization direction, this tunneling current becomes large.

If the magnetization directions of the tunnel barrier layer 57 and the free ferromagnetic layer 59 are reversed, the tunneling current becomes small. This is called TMR (Tunneling magneto resistance) effect.

In addition, the magnetization direction of the free ferromagnetic layer 59 may be detected by sensing the current magnitude due to the TMR effect, and thus the information stored in the cell may be known.

Since the MRAM cell of the present invention and the manufacturing method thereof form an MRAM cell on an SOI substrate, the junction capacity is smaller than that of a conventional MRAM cell formed on a conventional semiconductor substrate, thereby increasing the overall circuit speed and enabling low voltage operation, and improving current driving capability. In addition, there is an effect of improving the characteristics of the device, such as preventing the short channel effect.

Claims (3)

In an MRAM cell, An SOI substrate on which a silicon substrate, a buried oxide film, and a silicon layer are stacked; And a transistor formed in the silicon layer and having a source / drain junction region having a smaller junction capacitance than a gate electrode and a general semiconductor substrate. In the manufacturing method of the MRAM cell, Forming a buried oxide film on the silicon substrate; Selectively etching the investment oxide layer using a mask in which only a portion of the source region of each cell is removed; Growing a silicon layer on the buried oxide film using the silicon substrate as a seed, and forming an SOI substrate from the silicon substrate, the buried oxide film, and the silicon layer; Forming a transistor having a source / drain junction region having a smaller junction capacitance than the gate electrode semiconductor substrate in the silicon layer. The method of claim 2, The buried oxide film is formed to a thickness of 1000 to 4000 kPa, and the silicon layer is formed to a thickness of 500 to 1000 kPa.