TW498326B - Formation method of magneto-resistance RAM with magnetic tunnel junction - Google Patents

Formation method of magneto-resistance RAM with magnetic tunnel junction Download PDF

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TW498326B
TW498326B TW90107281A TW90107281A TW498326B TW 498326 B TW498326 B TW 498326B TW 90107281 A TW90107281 A TW 90107281A TW 90107281 A TW90107281 A TW 90107281A TW 498326 B TW498326 B TW 498326B
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layer
forming
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magnetic
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TW90107281A
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Chinese (zh)
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Jr-Jeng Liou
De-Yuan Wu
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United Microelectronics Corp
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Abstract

The present invention discloses a novel formation method of magnetic tunnel junction for magneto-resistance RAM, which comprises: first providing a substrate; depositing a pinned layer on the substrate; next, forming an insulating tunnel barrier layer on top of the pinned layer; next, depositing a free layer on the insulating tunnel barrier layer, so that a large single magnetic tunnel junction covers on the whole surface of the first insulating layer on the conductive wire layer; then, performing a etching process to etch through the free layer until reaching the surface of the insulating tunnel barrier layer, so as to transfer the large single magnetic tunnel junction pattern to a small magnetic tunnel junction.

Description

498326 五、發明說明(1) 5 - 1發明領域: 本發明係關於一種磁阻隨機存取記憶體(111381161:0-resistance memory random access mem〇ry; MRAM)的製 造方法’特別疋關於一種具有磁通道接面(m a g n e t i c tunnel junction; MTJ)之磁阻隨機存取記憶體( 的形成方法。 5-2發明背景:· 隨著半導體元件的積集度不斷地擴大,晶片(chip) 的使用面積必須維持一致,甚至縮小,以持續降低電路之 單位成本。為了符合高科技產業未來發展之趨勢,唯一的 辦法就是不斷地縮小電路設計規格(design rule)。因此 ’兀件所佔的空間面積亦隨著電路設計規格(design rule )而漸趨縮小。隨著半導體技術的發展,積體電路之元件 的尺寸已經縮減到深次微米的範圍。當半導體連續縮減到 深次微米的範圍時,產生了 一些在製程微縮上的問題。 在超大型積體電路T c Ί τ ( Very Large Scale Integrated circuits; VLSI) 的4百以丄。丄, 片 7 7員域中具有很多種的記憶體型態。近 年來,在積體電路工紫制4丄 菜製程中已經發展一種可當成非揮發 性儲存元件之磁阻隨撫卢取 > 比A / 早^ 钱存取 §己憶體(magnetoresistance498326 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for manufacturing a magnetoresistive random access memory (111381161: 0-resistance memory random access memory; MRAM). How to form a magnetoresistive random access memory (MTJ) of a magnetic tunnel junction (MTJ). 5-2 BACKGROUND OF THE INVENTION: · As the accumulation of semiconductor devices continues to expand, the area of use of chips (chips) It must be consistent or even reduced to continue to reduce the unit cost of the circuit. In order to meet the future development trend of the high-tech industry, the only way is to continuously reduce the design rule of the circuit. Therefore, the space occupied by the components With the design rule of circuit (design rule) gradually shrinks. With the development of semiconductor technology, the size of integrated circuit components has been reduced to the range of deep sub-micron. When the semiconductor is continuously reduced to the range of deep sub-micron, It has some problems in the process scaling. In the very large scale integrated circuit T c Ί τ (Very Large Scale Integrated circuits; VLSI) has more than 400 ohms. Alas, there are many types of memory in the 7-member domain. In recent years, in the process of the integrated circuit circuit purple 4 lettuce process, a kind of non-volatile storage element has been developed. The magnetoresistance is taken as soon as possible >> A / A ^ Money access §

第4頁 498326 ;MRAM)。 屬氧化半 存取記憶 久性。苴 fe體胞係 持所儲存 體胞能 某些型態 胞的陣列 記憶體。 五、發明說明(2) memory random 憶體(MRAM)係 體元件的整合基 憶體且具有不限 記憶體(DRAM) 化方向而儲存資 的時間,故其為 變靠近強磁區之 憶體胞。據此, 隨機存取記憶體 現今所提出 junction; MTJ) (MRAM)高速度 一般而言,磁通 含了一個由適當 材質能根據各層 電阻器元件之電, 絕緣通道阻障層: 性層之間的傳導’ 決定於相對應的ίP. 4 498326; MRAM). It is a semi-oxidative memory. Persistence.苴 fe somatic cell line holds the memory of some types of stored somatic energy. V. Description of the invention (2) memory random memory (MRAM) is an integrated base memory of memory elements and has unlimited memory (DRAM) direction to store data, so it is a memory that becomes close to the strong magnetic region Cell. According to this, the random access memory embodies the proposed junction; MTJ) (MRAM) high speed. Generally speaking, the magnetic flux contains a barrier material made of a suitable material according to the electrical resistance of each layer of resistor elements: Inter-conduction 'depends on the corresponding ί

在磁通道接ί ,記憶體胞的電F access memory 建立於互補式金 礎上。磁阻隨機 制讀寫次數之耐 不同的是,磁記 訊,因此能夠保 非揮發性。磁記 材質的電阻,其 一個磁化記憶體 或磁阻隨機存取 磁阻隨機存取I己 導體與磁性記憶 體為非揮發性記 與動態隨機存取 k者強磁區的磁 之負έίΐ依段很長 利用磁性狀態改 可稱之為磁阻記 常可稱之為磁化 之磁通道接面(magnet t 材料的理論給予了磁阻:n:t 、低操作電壓與高密度等、'既子取記憶體 道接面型態之磁阻隨機存:在的可能性。 的磁化材質所組成多層電=憶體元件自 的磁極化方向決定電流的产=兀件,磁处 阻。在一磁通道接面記情 以改變多層 來區隔兩強磁性層,且‘阻二二可藉由一 ®子之自旋—極化通道所產’、错由兩強培 '強磁性層間之瞬間磁性的方向通道電流 δ基底〜磁阻隨機存取記恃 …丨感應電流小。因此;體利(,)之中 了利用一種最小 498326 五、發明說明(3) 尺寸的主動元件(電晶體或二極體)當成隔離元件連結磁 通道接面旋轉開關(Μ T J s p i n v a 1 v e)元件來定義磁阻隨 機存取記憶體胞。在此結構上的記憶胞區域能藉由主動元 件或是磁通道接面記憶體胞的大小來定義。磁通道接面旋 轉開關係利用自由層的磁化方向進行資料記憶。記憶體位 元的電阻是高或是低取決於相對的磁化關係、自由層與固 定層的平行或非平行的關係。在讀取模式的期間,將磁通 道接面電阻的絕對值與一參考記憶胞做一比較時,此結構 中磁阻比例與記憶胞電阻的絕對值勢必要具有一致性。當 其與一參考記憶胞做一比較時,若是記憶體中的一組主動 元件電阻顯示了艰大的電阻變化,則會發出一錯誤訊號。 第一 A圖所示為傳統磁阻記憶體胞之磁阻隨機存取記 憶體(MR AM)的陣列,此陣列包含了 一組在水平面上當成 平行字元線1 1 0 A、1 1 Ο B、1 1 0 C之電傳導線,與另一組在另 一水平面上當成平行位元線1 2 0 A、1 2 Ο B、1 2 0 C之電傳導線 。位元線 1 1 0 A、1 1 Ο B、1 1 0 C與字元線 1 2 0 A、1 2 Ο B、1 2 0 C的 方向互相成九十度角,以致於從上往下觀察時,兩組線係 互相交錯。如第一 A圖與第一 B圖所示之一記憶體胞1 3 0, 其位於每條字元線與位元線互相交叉之垂直空間内的交點 中。記憶體胞.1 3 0為一垂直疊積結構,此垂直疊積結構包 含一磁通道接面1 4 0,如第一 B圖所示。磁通道接面1 4 0具 有一磁化方向固定不變之固定層150與一磁化方向可變動 之自由層160,在固定層與自由層之間包含有一電阻層17〇Connected to the magnetic channel, the electrical F access memory of the memory cell is based on complementary metal. The resistance to random reading and writing times of the magnetoresistance differs from that of the magnetic memory, so it can be kept non-volatile. The resistance of magnetic material, one of which is magnetized memory or magnetoresistive random access. The magnetoresistive random access I conductor and magnetic memory are non-volatile memory and dynamic random access. The magnetic field of the strong magnetic field is converted. Duan uses a magnetic state to change it to be called a magnetoresistance. It can often be called a magnetized magnetic channel junction (magnet t material theory gives magnetoresistance: n: t, low operating voltage and high density, etc. The magnetoresistance of the memory interface structure of the sub-memory is randomly stored: the possibility of being there. The multi-layer electricity composed of the magnetized material = the direction of the magnetic polarization of the memory element determines the current production = element, magnetic resistance. The magnetic channel interface remembers to change the multiple layers to separate the two strong magnetic layers, and the 'resistance of two or two can be produced by the spin-polarized channel of one electron', and the moment between the two strong magnetic layers Magnetic direction channel current δ substrate ~ Reluctance random access memory 丨 ... 丨 Induction current is small. Therefore, the use of a minimum of 498326 in the body (,) V. Description of the invention (3) size active element (transistor or Diode) as an isolation element connected to the magnetic channel interface Switch (M TJ spinva 1 ve) element to define the magnetoresistive random access memory cell. The memory cell area on this structure can be defined by the size of the active cell or the magnetic channel interface memory cell. The magnetic channel is connected The surface rotation open relationship uses the magnetization direction of the free layer for data storage. The resistance of the memory bit depends on the relative magnetization relationship and the parallel or non-parallel relationship between the free layer and the fixed layer. During the read mode When comparing the absolute value of the interface resistance of a magnetic channel with a reference memory cell, the ratio of the magnetoresistance in this structure must be consistent with the absolute value of the resistance of the memory cell. When it is compared with a reference memory cell If the resistance of a group of active components in the memory shows a difficult resistance change, an error signal will be issued. Figure A shows the MR AM of a conventional magnetoresistive memory cell (MR AM). ) Array, this array contains a group of electrical conductive lines 1 1 0 A, 1 1 0 B, 1 1 C as horizontal word lines on the horizontal plane, and another group as parallel bits on the other horizontal plane Lines 1 2 0 A, 1 2 〇 B, 1 2 0 C. Electrically conductive lines. Bit lines 1 1 0 A, 1 1 Ο B, 1 1 0 C and word lines 1 2 0 A, 1 2 Ο B The directions of 1, 2 0 C are at a 90-degree angle with each other, so that when viewed from top to bottom, the two sets of lines are staggered with each other. One of the memory cells shown in Figure A and Figure B is 1 3 0 It is located at the intersection point in the vertical space where each word line and bit line cross each other. The memory cell .130 is a vertical stacking structure, which includes a magnetic channel junction 1 4 0 As shown in the first figure B. The magnetic channel junction 1 40 has a fixed layer 150 with a fixed magnetization direction and a free layer 160 with a changeable magnetization direction. A resistance layer is included between the fixed layer and the free layer. 17〇

498326 五、發明說明(4) 在陣列操作的期間,垂直方向的電流會經過記憶體胞 1 3 0。經過記憶體胞1 3 0的垂直電流路徑僅佔據一小部分的 表面積,而且連接字元線、磁通道接面1 4 0、位元線的表 面積皆相同。然而此種傳統的結構將導致某些問題的發生 。當記憶體胞的尺寸變得更小時,記憶體胞的磁力線會更 加地複雜。此外,形成記憶體胞的製程在蝕刻三明治結構 時會產生邊端缺陷(e d g e d e f e c t),且#刻比的需求也較 高。另一方面,固定層的邊端也易於形成大的離散場( s t r a y f i e 1 d )。再者,由於傳統記憶體胞的電阻訊號微弱 ,因而難以測定傳統記憶體胞的磁場。 鑒於上述之種種原因,我們更需要一種新的磁阻隨機 存取記憶體(MRAM)之記憶體胞的形成方法,以便於提昇 後續製程的產率與良率。 5 - 3發明目的及概述: 鑒於上述.之發明背景中,傳統製造磁阻隨機存取記憶 體(MRAM)的方法,其所產生的諸多缺點,本發明提供一 方法可用以克服傳統製程上的問題。498326 V. Description of the invention (4) During the operation of the array, the vertical current will pass through the memory cell 1 3 0. The vertical current path through the memory cell 130 occupies only a small part of the surface area, and the surface area connecting the word lines, the magnetic channel junction 140, and the bit lines are all the same. However, this traditional structure will lead to some problems. As the size of the memory cell becomes smaller, the magnetic field lines of the memory cell become more complicated. In addition, during the process of forming the memory cell, edge defects (e d g e d e f e c t) are generated when the sandwich structure is etched, and the requirement of #etch ratio is also high. On the other hand, the edge of the fixed layer is also easy to form a large discrete field (s t r a y f i e 1 d). Furthermore, because the resistance signal of the traditional memory cell is weak, it is difficult to measure the magnetic field of the traditional memory cell. In view of the above reasons, we need a new method for forming memory cells of magnetoresistive random access memory (MRAM) in order to improve the yield and yield of subsequent processes. 5-3 Purpose and Summary of the Invention: In view of the above-mentioned background of the invention, the conventional method for manufacturing magnetoresistive random access memory (MRAM) has many disadvantages. The present invention provides a method that can be used to overcome the traditional process. problem.

^326 五、發明說明(5) 本發明的主要目的係在提供—種磁阻隨機 (mRAM…造方法。本發明能形成—種新的磁通道2 之結構以取代傳統的結構且可得到一較好的磁阻再 因此,本方法能夠適用於半導體元件之深次微米的技術中 方法能形成 定層的邊端 結構時避免 面積之固定 另一方面, 因此易於測 夠提供一種 以增加製程 本發明的方 本發明的另一目的係在提供一種磁阻隨機 (MRAM)之磁通道接面(MTJ)的形成方法。本 一大面積之固定層於磁通道接面中,以防止固 產生離散場(stray field)且可在蝕刻三明治 產生邊端缺陷。此外,本發明能藉由形成一大 層而得到一蝕刻終止層以降低製程的複雜度。 f於本發明之記憶體胞具有較強的電阻訊號, 呈本I明之記憶體胞的磁場。據此,本發明能 i Ϊ較佳磁阻再現性之磁阻隨機存取記憶體, ,與良率,且能因此而降低成本。所以, ’此夠符合經濟上的效益。 元件^ ^ =上所述之目的,本發明揭示了一種新的半導體 一導線;造方法。首先提供一底材。在該底材上形成一第 ,形成層’且·以一第一絕緣層覆蓋於第一導線層上。其次 後ιί由、連結元件於第一絕緣層中以連接第一導線層。然 dep〇s.磁電 I 濺鐘沉積法(magnetron sputter 111 〇n)將製造磁通道接面之連續層均勻地形成於第 498326 五、發明說明(6) 一絕緣層與連結元件的表面上。其依序為,沿著第一絕緣 層與連結元件的表面沉積一固定層(pinned layer)。接 著形成一絕緣通道阻障層(insulating tunnel barrier layer)於固定層的上端。然後沉積一自由層(free layer )於絕緣通道阻障層上。因此,一大的單一磁通道接面覆 蓋於導線層上之第一絕緣層的整個表面上。隨後,藉由一 蝕刻製程蝕刻穿過自由層直到絕緣通道阻障層的表面為止 ,以便於將此大的單一磁通道接面圖案轉移成一小的磁通 道接面。然後,覆蓋一第二絕緣層於磁通道接面上。之後 ,使用一先進的矽之超大型積體電路製程以打開一接觸洞 於小的磁通道接面上之第二絕緣層中。最後,形成一第二 導線層於上述結構上以連接小的磁通道接面中之自由層。 5 - 4發明的詳細說明: 本發明在此所探討的方向為一種半導體元件的製造方 法。為了能徹底地瞭解本發明,將在下列的描述中提出詳 盡的步驟。顯然地,本發明的施行並未限定於半導體元件 之技藝者所熟習的特殊細節。另一方面,眾所周知的製程 步驟並未描述於細節中,以避免造成本發明不必要之限制 。本發明的較佳實施例會詳細描述如下,然而除了這些詳 細描述之外,本發明還可以廣泛地施行在其他的實施例中 ,且本發明的範圍不受限定,其以之後的專利範圍為準。^ 326 V. Description of the invention (5) The main purpose of the present invention is to provide a kind of random magnetic resistance (mRAM ... manufacturing method. The present invention can form a kind of new magnetic channel 2 structure to replace the traditional structure and obtain a Better magnetic resistance. Therefore, this method can be applied to the deep sub-micron technology of semiconductor devices. The method can avoid the fixed area when forming the edge structure of a fixed layer. On the other hand, it is easy to measure and provide a method to increase the manufacturing cost. Invention of the Invention Another object of the present invention is to provide a method for forming a magnetic channel junction (MTJ) of a random-resistance random (MRAM). A large-area fixed layer is arranged in the magnetic channel junction to prevent solid dispersion. Field (stray field) and can produce edge defects in the etched sandwich. In addition, the present invention can obtain an etch stop layer by forming a large layer to reduce the complexity of the process. F The memory cell in the present invention has a strong The resistance signal represents the magnetic field of the memory cell of the present invention. According to this, the present invention can reduce the reluctance random access memory with better reluctance reproducibility, and reduce the cost. Therefore, 'This is sufficient for economic benefits. The element ^ ^ = the purpose described above, the present invention discloses a new semiconductor-conductor; manufacturing method. First, a substrate is provided. A first is formed on the substrate, The formation layer 'is covered with a first insulating layer on the first wire layer. Then, the connecting elements are connected in the first insulating layer to connect the first wire layer. Then depos. (Magnetron sputter 111 〇n) uniformly forming a continuous layer for manufacturing magnetic channel junctions on the 498326 fifth, the description of the invention (6) an insulation layer and the surface of the connecting element. It is, in order, along the first insulation layer A pinned layer is deposited on the surface of the connecting element. An insulating tunnel barrier layer is formed on the upper end of the pinned layer. A free layer is then deposited on the insulating channel barrier layer. Therefore, a large single magnetic channel junction surface covers the entire surface of the first insulating layer on the wire layer. Subsequently, the free layer is etched through an etching process to the surface of the insulating channel barrier layer. In order to transfer this large single magnetic channel junction pattern into a small magnetic channel junction. Then, a second insulating layer is covered on the magnetic channel junction. After that, an advanced silicon super large integrated circuit is used. The process is to open a contact hole in the second insulating layer of the small magnetic channel junction. Finally, a second wire layer is formed on the structure to connect the free layer in the small magnetic channel junction. 5-4 Invention Detailed description of the invention: The direction of the present invention is a method of manufacturing a semiconductor device. In order to fully understand the present invention, detailed steps will be proposed in the following description. Obviously, the implementation of the present invention is not limited to Special details familiar to the artist of semiconductor components. On the other hand, well-known process steps are not described in detail to avoid unnecessary limitations of the present invention. The preferred embodiments of the present invention will be described in detail as follows. However, in addition to these detailed descriptions, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited, which is subject to the scope of subsequent patents. .

498326 五、發明說明(?) 參考第二A圖所示,在本發明之一實施例中,首先提 供一半導體底材200。在半導體底材20 0上,形成一第一導 線層2 1 〇,例如一字元線,且以一第一絕緣層2 2 〇覆蓋之。 其-人’形成一接觸洞於第一絕緣層2 2 0中以曝露第一導線 層2 1 〇之一部分表面。之後,形成一連結元件2 3 〇,例如一 二極體,於第一絕緣層2 2 0之接觸洞中以連接第一導線層 210。然後藉由磁電管〉賤鑛沉積法(magnetr〇n SpUtter deposition)將製造磁通道接面240A之連續層均勻地形成 於第一絕緣層2 2 0與連結元件2 3 0的表面上。 參考第二B圖所示,在本實施例中,其次序為,沿著 第一絕緣層2 2 0與連結元件2 3 0的表面沉積一具有多層磁化 材質(例如N i、C 〇、F e合金)之固定層(pinned layer) 250,其中,固定層25 0的極化方向一致且固定不變。接著 形成一絕緣通道阻障層(insulating tunnel barrier 1 ay er) 2 6 0於固定層2 5 0的上端,其中,絕緣通道阻障層 2 6 0的形成方法係應用一鋁材質的沉積且進行一氧化製程 以形成一鋁氧化物層,例如A 1 2 0 3。然後沉積一具有多層 磁化材質(例如N i、C 〇、F e合金)之自由層(free layer )2 7 0於絕緣通道阻障層2 6 0上,其中,自由層2 7 0具有一可 變動的極化方向。因此,一大的單一磁通道接面2 4 0 A覆蓋 於第一導線層2 1 0上之第一絕緣層2 2 0的整個表面上。498326 V. Description of the invention (?) Referring to the second figure A, in one embodiment of the present invention, a semiconductor substrate 200 is first provided. On the semiconductor substrate 200, a first conductive layer 21 is formed, for example, a word line, and is covered with a first insulating layer 220. It-person 'forms a contact hole in the first insulating layer 220 to expose a part of the surface of the first wire layer 21. After that, a connecting element 230 is formed, such as a diode, in the contact hole of the first insulating layer 220 to connect the first wire layer 210. Then, a continuous layer for manufacturing the magnetic channel junction 240A is uniformly formed on the surfaces of the first insulating layer 2 2 0 and the connecting member 2 3 0 by a magnetron> magnetron SpUtter deposition method. Referring to FIG. 2B, in this embodiment, the sequence is to deposit a multilayer magnetized material (for example, Ni, Co, F) along the surfaces of the first insulating layer 220 and the connecting element 230. e alloy) pinned layer 250, wherein the polarization direction of the pinned layer 250 is uniform and fixed. An insulating tunnel barrier 1 ayer 2 60 is formed on the upper end of the fixed layer 2 50. The method of forming the insulating channel barrier 2 60 is to deposit and perform an aluminum material. An oxidation process is performed to form an aluminum oxide layer, such as A 1 2 0 3. Then, a free layer 2 70 having a multilayer magnetization material (such as Ni, Co, Fe alloy) is deposited on the insulating channel barrier layer 2 60, wherein the free layer 2 70 has Changing direction of polarization. Therefore, a large single magnetic channel junction surface 2 40 A covers the entire surface of the first insulating layer 2 2 0 on the first wire layer 2 10.

498326 五、發明說明(8) -- 參考弟一 c圖所示’在本實施例中,形成且定義一光 阻層2 75於自由層2 70上。然後,藉由光阻層2 75當成一蝕 刻罩幕與一 |虫刻製程#穿自由層2 7 〇直到絕緣通道阻障層 2 6 0的表面為止,以便於將此大的單一磁通道接面24〇a^ 案轉移成一小的磁通道接面2 4 0 B。隨後,覆蓋一第一 / 層28 0於磁通道接面240B上。之後,形成一接;蜀洞於一小 磁通道接面24 0B上之第二絕緣層28 0中。最後,形成一第 二導線層2 9 0,例如一位元線,於上述結構上以連接小的 磁通道接面2 4 0 B中之自由層2 6 0,如第二D圖所示。 如上所述,在本發明的實施例中,提供一種磁阻隨機 存取記憶體(MRAM)的製造方法。本發明能形成一種新的 磁通道接面之結構以取代傳統的結構且可得到一較好的磁 阻再現性。因此,本方法能夠適用於半導體元件之深次微 米的技術中。此外,本方法能形成一具有大面積之固定層 於磁通道接面中,以防止固定層的邊端產生離散場&忖2 f 1 e 1 d )且可在進行蝕刻製程時避免產生三明治結構之 缺陷,如第二E圖所示。另一方面,由於本發明之記憶體 胞具有較強的電阻訊號,因此易於測定本發明之記憶體胞 的磁場。此外,本發明能藉由形成一大面積之固定層而得 =一蝕刻終止·層以降低製程的複雜度。據此,本發明能夠 提供一種具有較佳磁阻再現性之磁阻隨機存取記憶體以擗 加製程之產率與良率,且能因此而降低成本。換言之,上 發明的方法能夠符合經濟上的效益。498326 V. Description of the invention (8)-Refer to Figure 1c. In this embodiment, a photoresist layer 2 75 is formed and defined on the free layer 2 70. Then, the photoresist layer 2 75 is used as an etch mask and a worm etch process # to pass through the free layer 2 7 0 until the surface of the insulating channel barrier layer 2 60 to facilitate the connection of this large single magnetic channel. The surface 24〇a ^ case is transferred into a small magnetic channel interface 2 4 0 B. Subsequently, a first / layer 280 is covered on the magnetic channel junction 240B. After that, a junction is formed; the Shu hole is in a second insulating layer 280 on a small magnetic channel junction 24B. Finally, a second wire layer 290, such as a one-bit wire, is formed on the above structure to connect the free layer 2 60 in the small magnetic channel junction 2 4 0 B, as shown in the second D diagram. As described above, in the embodiment of the present invention, a method for manufacturing a magnetoresistive random access memory (MRAM) is provided. The invention can form a new structure of the magnetic channel junction to replace the traditional structure and obtain a better reluctance of magnetoresistance. Therefore, this method can be applied to the technology of deep submicron semiconductor devices. In addition, the method can form a fixed layer with a large area in the interface of the magnetic channel to prevent a discrete field from being generated at the edges of the fixed layer & 忖 2 f 1 e 1 d) and to avoid sandwiches during the etching process The defects of the structure are shown in the second E diagram. On the other hand, since the memory cell of the present invention has a strong resistance signal, it is easy to measure the magnetic field of the memory cell of the present invention. In addition, the present invention can reduce the complexity of the process by forming a large-area fixed layer = an etch stop layer. According to this, the present invention can provide a magnetoresistive random access memory with better magnetoresistive reproducibility to increase the yield and yield of the manufacturing process, and can reduce the cost accordingly. In other words, the method of the invention can be economically beneficial.

第11頁 498326 五、發明說明(9) 當然,本發明可能用在形成磁通道接面之製程上,也 可能用在任何磁阻隨機存取記憶體元件之製造上。而且, 本發明藉由大的固定層以避免邊端缺陷且可得到較強的電 阻訊號之方法,迄今仍未發展用在關於磁阻隨機存取記憶 體之製程方面。對深次微米的製程而言,本方法為一較佳 可行之磁阻隨機存取記憶體的製程。 顯然地,依照上面實施例中的描述,本發明可能有許 多的修正與差異。因此需要在其附加的權利要求項之範圍 内加以理解,除了上述詳細的描述外,本發明還可以廣泛 地在其他的實施例中施行。 上述僅為本發明之較佳實施例而已,並非用以限定本 發明之申請專利範圍;凡其它未脫離本發明所揭呆之精神 下所完成的等效改變或修飾,均應包含在下述申請專利範 圍内。Page 11 498326 V. Description of the invention (9) Of course, the present invention may be used in the process of forming a magnetic channel junction, or it may be used in the manufacture of any magnetoresistive random access memory device. Moreover, the present invention has not developed a method for manufacturing a magnetoresistive random access memory by using a large pinned layer to avoid edge defects and obtain a strong resistive signal. For deep sub-micron processes, this method is a better and feasible process for magnetoresistive random access memory. Obviously, according to the description in the above embodiments, the present invention may have many modifications and differences. Therefore, it needs to be understood within the scope of the appended claims. In addition to the above detailed description, the present invention can be widely implemented in other embodiments. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit of the present invention should be included in the following applications Within the scope of the patent.

498326 圖式簡單說明 第一 A圖顯示具有傳統的磁通道接面之傳統的磁阻隨 機存取記憶體的結構剖面圖; 第一 B圖顯示傳統的磁通道接面的結構剖面圖; 第二A圖至第二D圖係為根據本發明之一較佳實施例中 ,形成具有磁通道接面之磁阻隨機存取記憶體的製程剖面 圖;與 第二E圖顯示本發明之一較佳實施例的磁通道接面之 結構剖面圖。 主要部分之代表符號: 1 1 Ο A 字元線。 1 1 Ο B 字元線。 1 1 0 C 字元線。 1 20A 位元線。 1 2 Ο B 位元線。 1 2 0 C 位元線。 130 傳統之磁阻隨機存取記憶體胞。 140 傳統之磁通道接面。 15 0 固定層。 160 通道阻障層。 17 0 自由層。498326 Brief description of the diagram. The first diagram A shows a structural sectional view of a conventional magnetoresistive random access memory with a conventional magnetic channel junction. The first diagram B shows a structural sectional view of a conventional magnetic channel junction. Figures A through D are cross-sectional views of a process for forming a magnetoresistive random access memory with magnetic channel junctions according to a preferred embodiment of the present invention; and Figure E shows a comparison with one of the present invention. Structural sectional view of the magnetic channel junction of the preferred embodiment. The main part of the symbol: 1 1 〇 A character line. 1 1 Ο B word line. 1 1 0 C character line. 1 20A bit line. 1 2 〇 B bit line. 1 2 0 C bit line. 130 Traditional magnetoresistive random access memory cells. 140 Traditional magnetic channel junction. 15 0 Fixed layer. 160-channel barrier layer. 17 0 Free layer.

第13頁 498326 圖式簡單說明 2 0 0 半導體底材。 210 第一導線層。 2 2 0 第一絕緣層。 2 3 0 連結元件。 2 4 0 A 大面積之磁通道接面。 2 4 0 B 小面積之磁通道接面 2 5 0 固定層。 2 6 0 絕緣通道阻障層。Page 13 498326 Schematic illustration of 2 0 0 semiconductor substrate. 210 First wire layer. 2 2 0 First insulation layer. 2 3 0 Link components. 2 4 0 A large-area magnetic channel junction. 2 4 0 B Small-area magnetic channel interface 2 5 0 Fixed layer. 2 6 0 Insulated channel barrier.

第14頁Page 14

Claims (1)

498326 六、申請專利範圍 1. 一種形成一磁阻隨機存取記憶體之一磁通道接面的方法 ,該方法至少包含下列步驟: 提供一底材; 形成一第一磁化層於該底材上; 形成一絕緣通道阻障層於該第一磁化層上; 形成一第二磁化層於該絕緣通道阻障層上; 形成且定義一光阻層於該第二磁化層上; 藉由該光阻層當成一蝕刻罩幕蝕刻該第二磁化層直到 該絕緣通道阻障層為止;與 移除該光阻層以形成該磁通道接面。 法 方。 成向 形方 的化 面極 接的 道定 通固 磁一 之含 述包 所少 項至 1 層 第化 圍磁 範一 利第 專之 請述 申上 如中 2其 法程 方製 .成積 形沉 的一 面含 接包 道少 通至 磁驟 之步 述成 所形 項的 τΉ 層 第化 圍磁 範 一 利第 專之 請述 申上 如中 3其 4.如申請專利範圍第1項所述之磁通道接面的形成方法, 其中上述之絕緣通道阻障層至少包含一氧化物層。 5.如申請專利範圍第4項所述之磁通道接面的形成方法’ 其中上述之氧化物層至少包含一紹氧化物層。 6.如申請專利範圍第1項所述之磁通道接面的形成方法,498326 6. Scope of patent application 1. A method of forming a magnetic channel junction of a magnetoresistive random access memory, the method includes at least the following steps: providing a substrate; forming a first magnetized layer on the substrate Forming an insulating channel barrier layer on the first magnetization layer; forming a second magnetization layer on the insulating channel barrier layer; forming and defining a photoresist layer on the second magnetization layer; by the light The resist layer acts as an etching mask to etch the second magnetization layer until the insulating channel barrier layer; and removing the photoresist layer to form the magnetic channel interface. French side. The directional square-shaped chemical planes are extremely close to each other, and the Dao Dingtong solid magnetic one contains the lesser items to the first layer of the surrounding magnetic field Fan Yilidi. The special application is applied as described above and its legal formula is. The side of the product shape contains the τΉ layer that describes the steps from the enveloping road to the magnetic step. The layer is surrounded by the magnetic field. Fanyi Lidi's special application is as described above. 3. If the scope of patent application is the first The method for forming a magnetic channel junction according to the item, wherein the above-mentioned insulating channel barrier layer includes at least an oxide layer. 5. The method for forming a magnetic channel junction according to item 4 of the scope of the patent application, wherein the above oxide layer includes at least one oxide layer. 6. The method for forming a magnetic channel junction as described in item 1 of the scope of patent application, 第15頁 498326 六、申請專利範圍 其中上述之絕緣通道阻障層的形成方法至少包含一沉積製 程。 7. 如申請專利範圍第1項所述之磁通道接面的形成方法, 其中上述之絕緣通道阻障層的形成方法至少包含一氧化製 程。 8. 如申請專利範圍第1項所述之磁通道接面的形成方法, 其中上述之第二磁化層至少包含一可變動的極化方向。Page 15 498326 6. Scope of patent application Wherein, the above-mentioned method for forming the insulating channel barrier layer includes at least a deposition process. 7. The method for forming a magnetic channel junction as described in item 1 of the scope of patent application, wherein the method for forming the above-mentioned insulating channel barrier layer includes at least an oxidation process. 8. The method for forming a magnetic channel junction according to item 1 of the scope of the patent application, wherein the second magnetized layer includes at least one variable polarization direction. 9. 如申請專利範圍第1項所述之磁通道接面的形成方法, 其中上述之第二磁化層的形成步驟至少包含一沉積製程。 1 0. —種形成一磁阻隨機存取記憶體之一磁通道接面的方 法,該方法至少包含下列步驟: 提供一底材; 形成一固定層於該底材上; 沉積且形成一鋁層於該固定層上;9. The method for forming a magnetic channel junction according to item 1 of the scope of the patent application, wherein the step of forming the second magnetized layer includes at least one deposition process. 1 0. A method for forming a magnetic channel junction of a magnetoresistive random access memory, the method includes at least the following steps: providing a substrate; forming a fixed layer on the substrate; depositing and forming an aluminum Layer on the fixed layer; 藉由一氧化製程形成一鋁氧化物層,以便於該固定層 上形成一絕緣通道阻障層; 形成一自.由層於該絕緣通道阻障層上; 形成且定義一光阻層於該自由層上; 藉由該光阻層當成一 I虫刻罩幕#刻該自由層直到該絕 緣通道阻障層為止;與An aluminum oxide layer is formed by an oxidation process, so as to form an insulating channel barrier layer on the fixed layer; forming a free layer on the insulating channel barrier layer; forming and defining a photoresist layer on the On the free layer; engraving the free layer with the photoresist layer as an insect insect mask # until the insulating channel barrier layer; and 第16頁 498326 六、申請專利範圍 移除該光阻層以形成該磁通道接面。 11.如申請專利範圍第1 〇項所述之磁通道接面的形成方法 ,其中上述之固定層至少包含一磁化材料。 1 2.如申請專利範圍第1 0項所述之磁通道接面的形成方法 ,其中上述之固定層至少包含一固定的極化方向。 1 3.如申請專利範圍第1 0項所述之磁通道接面的形成方法 ,其中上述之固定層的形成步驟至少包含一沉積製程。 1 4.如申請專利範圍第1 0項所述之磁通道接面的形成方法 ,其中上述之自由層至少包含一磁化材料。 1 5.如申請專利範圍第1 0項所述之磁通道接面的形成方法 ,其中上述之自由層至少包含一可變動的極化方向。 1 6.如申請專利範圍第1 0項所述之磁通道接面的形成方法 ,其中上述之自由層的形成步驟至少包含一沉積製程。 1 7. —種具有一磁通道接面之一磁阻隨機存取記憶體的形 成方法,該方法至少包含下列步驟: 提供一底材; 形成一第一導線層於該底材上,且以一第一絕緣層覆Page 16 498326 6. Scope of patent application Remove the photoresist layer to form the magnetic channel junction. 11. The method for forming a magnetic channel junction according to item 10 of the scope of the patent application, wherein the fixed layer includes at least one magnetized material. 1 2. The method for forming a magnetic channel junction as described in item 10 of the scope of patent application, wherein the fixed layer includes at least a fixed polarization direction. 1 3. The method for forming a magnetic channel junction as described in item 10 of the scope of the patent application, wherein the step of forming the above-mentioned fixed layer includes at least one deposition process. 14. The method for forming a magnetic channel junction as described in item 10 of the scope of the patent application, wherein the above-mentioned free layer includes at least one magnetized material. 15. The method for forming a magnetic channel junction as described in item 10 of the scope of the patent application, wherein the above-mentioned free layer includes at least one variable polarization direction. 16. The method for forming a magnetic channel junction as described in item 10 of the scope of the patent application, wherein the step of forming the free layer described above includes at least one deposition process. 1 7. A method for forming a magnetoresistive random access memory with a magnetic channel interface, the method includes at least the following steps: providing a substrate; forming a first wire layer on the substrate, and -A first insulating layer 498326 六、申請專利範圍 一線; 到 通二 第導上 直 磁第 該一件 層 該該 露 第元 化 露.接 曝 該 結;; 磁 ·,曝 連 以 接 連上上·,二 面以 以 , 連 該層層上第 接, , 中 以 與化障層該 ·,道中與中 層 中 層磁阻化刻 面通層·,洞。 緣 洞 緣一道磁蝕 接磁緣面觸體 絕 觸 絕第通二幕 道該絕表接憶 一 接 一該緣第罩 通於二分二記 第 一 第於絕該刻 磁蓋第部第取 該 第 該層該於蝕 該覆該一該存 於 該 於障於層一;成且於的於機 •,洞 ·,於 層阻層阻成止形層洞層層隨 上觸面件 化道化光當為以緣觸化線阻 層接表元 磁通磁 一層層層絕接磁導磁 線一份結 一緣二義阻障阻二二二二該 導第部連 第絕第定光阻光第第第第成 II 一一一 且該道該一一該一形 第成之成 成成成成由通除成成之成且 該形層形 形形形形藉緣移形形面形層 於線; 絕 接化 蓋導層 該 道磁 1 8.如申請專利範圍第1 7項所述之磁阻隨機存取記憶體的 形成方法,其中上述之第一磁化層至少包含一固定的極化 方向。 1 9.如申請專利範圍第1 7項所述之磁阻隨機存取記憶體的 形成方法,其中上述之第一磁化層的形成步驟至少包含一498326 VI. First line of patent application; go straight to the second guide to the first magnetic layer of the first layer of the first layer of the dew yuan. Expose the knot; magnetic ·, the exposure to connect to the upper ·, the two sides to the Connected to the first layer, the middle layer and the barrier layer, the middle layer and the middle layer of the magnetoresistance facet through layer, the hole. The edge of the hole is magnetically etched, the magnetic contact surface contact is absolutely contacted, the second act is said, the watch is connected, the edge is covered, and the cover is connected to the two points. The first part is taken at the moment. The first layer should be etched, overlaid, one should be stored in the other, and the one in the layer; one that is made in the machine, the hole, and the layer in the resistance layer to form a stop layer. Dow light is connected to the surface element magnetic flux by the edge contact line resistance layer by layer, the magnetic flux line is layered, the magnetic flux line is connected, the edge is the ambiguous resistance, the resistance is 2222. Light blocking No. 1st II II one by one and the one by one formation of the road is formed by the pass through the formation of the formation and the shape of the layer is shaped by the edge of the shape The layer is on the line; the cover is conductive; the track is magnetic 1 8. The method for forming a magnetoresistive random access memory as described in item 17 of the scope of patent application, wherein the first magnetic layer described above includes at least one fixed Direction of polarization. 19. The method for forming a magnetoresistive random access memory according to item 17 of the scope of the patent application, wherein the step of forming the first magnetization layer includes at least one 第18頁 498326 六、申請專利範圍 沉積製程。 2 0 .如申請專利範圍第1 7項所述之磁阻隨機存取記憶體的 形成方法,其中上述之絕緣通道阻障層至少包含一氧化物 層。 2 1.如申請專利範圍第2 0項所述之磁阻隨機存取記憶體的 形成方法,其中上述之氧化物層至少包含一紹氧化物層。 2 2.如申請專利範圍第1 7項所述之磁阻隨機存取記憶體的 形成方法,其中上述之絕緣通道阻障層的形成方法至少包 含一沉積製程。 2 3.如申請專利範圍第1 7項所述之磁阻隨機存取記憶體的 形成方法,其中上述之絕緣通道阻障層的形成方法至少包 含一氧化製程。 2 4.如申請專利範圍第1 7項所述之磁阻隨機存取記憶體的 形成方法,其中上述之第二磁化層至少包含一可變動的極 化方向。 2 5 .如申請專利範圍第1 7項所述之磁阻隨機存取記憶體的 形成方法,其中上述之第二磁化層的形成步驟至少包含一 沉積製程。Page 18 498326 6. Scope of patent application Deposition process. 20. The method for forming a magnetoresistive random access memory according to item 17 in the scope of the patent application, wherein the above-mentioned insulating channel barrier layer includes at least an oxide layer. 2 1. The method for forming a magnetoresistive random access memory as described in item 20 of the scope of patent application, wherein the above oxide layer includes at least one oxide layer. 2 2. The method for forming a magnetoresistive random access memory as described in item 17 of the scope of the patent application, wherein the method for forming an insulating channel barrier layer includes at least a deposition process. 2 3. The method for forming a magnetoresistive random access memory as described in item 17 of the scope of the patent application, wherein the method for forming an insulating channel barrier layer includes at least an oxidation process. 2 4. The method for forming a magnetoresistive random access memory according to item 17 of the scope of the patent application, wherein the second magnetization layer includes at least a variable polarization direction. 25. The method for forming a magnetoresistive random access memory as described in item 17 of the scope of the patent application, wherein the step of forming the second magnetization layer includes at least a deposition process. 498326 六、申請專利範圍 2 6. —種具有一磁通道接面之一磁阻隨機存取記憶體的形 成方法,該方法至少包含下列步驟: 提供一底材; 形成一字元線層於該底材上,且以一第一絕緣層覆蓋 於該字元線層上; 形成一第一接觸洞於該第一絕緣層中,以曝露該字元 線層之一部份表面; 形成一連結元件於該第一接觸洞中以連接該字元線層498326 6. Application Patent Scope 2 6. —A method for forming a magnetoresistive random access memory with one magnetic channel interface, the method includes at least the following steps: providing a substrate; forming a word line layer on the Forming a first contact hole in the first insulating layer to expose a part of the surface of the word line layer on the substrate, and covering the word line layer with a first insulating layer; forming a connection A component in the first contact hole to connect the word line layer 形成一固定層於該第一絕緣層與該連結元件上; 沉積且形成一鋁層於該固定層上; 藉由一氧化製程形成一鋁氧化物層,以便於該固定層 上形成一絕緣通道阻障層; 形成一自由層於該絕緣通道阻障層上; 形成且定義一光阻層於該自由層上; 藉由該光阻層當成一#刻罩幕#刻該自由層直到該絕 緣通道阻障層為止;Forming a fixed layer on the first insulating layer and the connecting element; depositing and forming an aluminum layer on the fixed layer; forming an aluminum oxide layer by an oxidation process so as to form an insulating channel on the fixed layer A barrier layer; forming a free layer on the insulating channel barrier layer; forming and defining a photoresist layer on the free layer; using the photoresist layer as a # 刻 幕 幕 # to etch the free layer until the insulation Up to the barrier layer; 移除該光阻層以形成該磁通道接面; 形成一第二絕緣層且覆蓋於該磁通道接面; 形成一第二接觸洞於該第二絕緣層中,以曝露該磁通 道接面之該自由層的一部分表面;與 形成一位元線層於該第二接觸洞中,以連接該自由層 且形成該磁阻隨機存取記憶體。Removing the photoresist layer to form the magnetic channel interface; forming a second insulating layer covering the magnetic channel interface; forming a second contact hole in the second insulating layer to expose the magnetic channel interface A part of the surface of the free layer; and forming a bit line layer in the second contact hole to connect the free layer and form the magnetoresistive random access memory. 第20頁 498326 六、申請專利範圍 2 7.如申請專利範圍第2 6項所述之磁通道接面的形成方 法,其中上述之固定層至少包含一磁化材料。 2 8 .如申請專利範圍第2 6項所述之磁阻隨機存取記憶體的 形成方法,其中上述之固定層至少包含一固定的極化方 向。 2 9 .如申請專利範圍第2 6項所述之磁阻隨機存取記憶體的 形成方法,其中上述之固定層的形成步驟至少包含一沉積 製程。 3 0 .如申請專利範圍第2 6項所述之磁阻隨機存取記憶體的 形成方法,其中上述之自由層至少包含一磁化材料。 3 1.如申請專利範圍第2 6項所述之磁阻隨機存取記憶體的 形成方法,其中上述之自由層至少包含一可變動的極化方 向。 3 2 .如申請專利範圍第2 6項所述之磁阻隨機存取記憶體的 形成方法,其中上述之自由層的形成步驟至少包含一沉積 製程。Page 20 498326 6. Scope of patent application 2 7. The method for forming a magnetic channel junction as described in item 26 of the scope of patent application, wherein the above-mentioned fixed layer includes at least one magnetized material. 28. The method for forming a magnetoresistive random access memory as described in item 26 of the scope of the patent application, wherein the fixed layer includes at least a fixed polarization direction. 29. The method for forming a magnetoresistive random access memory according to item 26 of the scope of the patent application, wherein the step of forming the fixed layer includes at least one deposition process. 30. The method for forming a magnetoresistive random access memory according to item 26 of the scope of the patent application, wherein the above free layer includes at least one magnetized material. 3 1. The method for forming a magnetoresistive random access memory as described in item 26 of the scope of the patent application, wherein the above free layer includes at least a variable polarization direction. 32. The method for forming a magnetoresistive random access memory according to item 26 of the scope of the patent application, wherein the step of forming the free layer described above includes at least one deposition process. 第21頁Page 21
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