US20020084191A1 - Electric copper plating liquid and process for manufacturing semiconductor integrated circuit device using same - Google Patents

Electric copper plating liquid and process for manufacturing semiconductor integrated circuit device using same Download PDF

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US20020084191A1
US20020084191A1 US09/888,642 US88864201A US2002084191A1 US 20020084191 A1 US20020084191 A1 US 20020084191A1 US 88864201 A US88864201 A US 88864201A US 2002084191 A1 US2002084191 A1 US 2002084191A1
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copper
features
electroplating bath
copper electroplating
layer
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Toshio Haba
Takeyuki Itabashi
Haruo Akahoshi
Shinichi Fukada
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Hitachi Ltd
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Hitachi Ltd
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Assigned to HITACHI, LTD. reassignment HITACHI, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUKADA, SHINICHI, AKAHOSHI, HARUO, HABA, TOSHIO, ITABASHI, TAKEYUKI
Publication of US20020084191A1 publication Critical patent/US20020084191A1/en
Priority to US10/996,382 priority Critical patent/US20050087447A1/en
Abandoned legal-status Critical Current

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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/38—Electroplating: Baths therefor from solutions of copper
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method

Definitions

  • the present invention relates to a copper plating bath, more particularly, to a copper electroplating liquid to be used for filling copper in fine openings in insulating layers by electroplating, and a process for manufacturing a semiconductor integrated device with multi-layer interconnections formed using the same.
  • a diffusion-inhibiting layer (barrier layer) and a copper seed layer are formed on the surfaces of an insulating interlayer having trenches and vias formed therein by sputtering and then copper is filled in the trenches and vias by electroplating with a seed layer being as an electron transmitting layer.
  • Materials to be used for the barrier layer include high melting point metals such as tantalum, tungsten and the like, and alloys thereof and nitrides such as titanium nitride, tantalum nitride and the like.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • plating a method for filling the features.
  • the PVD method is poor in coverage with metals on the sides of the features making their aspect ratio higher (that is, making the features thinner and deeper), which may form voids in the filled metals.
  • the CVD method is relatively good in coverage, but it suffers from high costs of source materials.
  • the plating is lower in cost as compared with other methods and excellent in filling property. Therefore, it has attracted much interest.
  • Particularly electroplating is excellent in filling property, provides a high throughput, and effective to mass production. Therefore, it is most promising as a method for filling features.
  • Japanese Patent KOKAI No. Hei 11-26394 discloses a process for filling trenches by electroplating after forming an iodine coating layer on a seed layer.
  • Japanese Patent KOKAI No. Hei 11-97391 discloses a process for producing interconnections by electroplating with pulse current in a plating bath without additives.
  • Japanese Patent KOKAI No. Hei 11-310896 discloses a process for producing interconnections in a plating bath containing little support electrolyte.
  • Japanese Patent Kokai No. 2000-248397 discloses a process for filling trenches by adding a polymeric surfactant, a sulfur-based saturated organic compound and an organic dye compound to a plating bath.
  • the organic dye compound such as Absorber Dye ADI or Cy5 is added to the plating bath so as to attain levelling function which smoothes the copper surface.
  • Absorber Dye ADI and Cy5 comprise an anionic compound having 2 or more of sulfonic groups. Such a compound is scarecely adsorbed on the surface in the plating step. Therefore, it is hard to grow plating preferentially from the bottoms, which is accomplished by a reaction of an additive described below.
  • an additive is added to a copper electroplating bath, said additive suitable to allow copper plating to proceed preferentially from the bottoms of features such as trenches and vias having a high aspect ratio which have been formed on the surfaces of a substrate.
  • the copper electroplating bath of the present invention comprises a solution containing copper ions and electrolyte(s) with an addition of, for example, cyanine dye.
  • the solution containing copper ions and electrolyte(s) contains as an additive at least one of cyanine dyes represented by, for example, the following general formula (I):
  • X 31 is an anion
  • the solution containing copper ions and electrolyte(s) is characterized by having an indolium compound added thereto.
  • the copper electroplating bath may contain at least one or more of polyethers, organic sulfur compounds and halide ions as further additives.
  • the process for producing a semiconductor integrated circuit devices comprises providing an insulating layer having openings on the top of the major surface of a semiconductor wafer which has a plurality of circuit element areas formed therein, depositing a barrier layer and a seed layer on the bottom and the side surfaces of the openings and on the top surface of the insulating layer, and filling the inside of the openings with copper without forming any voids and seams by electroplating with the copper electroplating bath as described above to from a interconnection layer.
  • the process is capable of producing a high packing density LSI having an excellent reliability with high reproducibility.
  • FIGS. 1A, 1B, 1 C, and 1 D show a cross-sectional view of a major part of an interconnect structure at each step of the process for the production thereof in an Example according to the present invention, respectively.
  • FIGS. 2A, 2B, 2 C, and 2 D show a cross-sectional view of a major part of an interconnect structure at each step of the process for the production thereof in another Example according to the present invention, respectively.
  • FIG. 3 shows a cross-sectional view of a major part of an interconnect structure showing how a copper film is allowed to grow by the plating according to the present invention.
  • FIG. 4 shows a cross-sectional view of a major part of an interconnect structure in a Comparative Example to demonstrate the effect of the present invention.
  • FIG. 5 shows a cross-sectional view of a major part of an interconnection structure showing how a copper film is allowed to grow by the plating in a Comparative Example to demonstrate the effect of the present invention.
  • each reference number designates a part as follows: 1 : Silicon substrate; 2 : Insulating layer; 3 : Via; 4 : Barrier layer; 5 : Seed layer; 6 : Copper electroplated layer; 7 : Trench; 8 : Insulating layer; 9 , 11 and 12 : Copper layer; 13 : Void.
  • metals which may be used in filling fine features with a low resistance metal by electroplating include gold, silver and copper. These metals may diffuse into adjacent insulating layers and semiconductor layers to deteriorate characteristic properties of circuit elements. Therefore, the diffusion must be prevented by providing a barrier layer under the metal layer. Electroconductive materials which can function as barrier include metal nitrides such as titanium nitride, tungsten nitride, tantalum nitride, and high melting point metals such as tantalum and tungsten and alloys thereof. These barrier layers are also disposed sequentially to the surfaces of the insulating layers having the trenches and the vias as well as the inside of thereof.
  • the barrier layer which may be made of any one of metal nitrides and high melting point metals and alloys thereof has a relatively high resistance and may produce a relatively stable oxide on the surface, so that it is difficult to electroplate directly the surface of the barrier layer. For this reason, a seed layer as an electron transmitting layer, e.g., a copper film is further formed on the barrier layer using PVD, CVD, or electroless deposition process.
  • a copper is electroplated on the seed layers present even on the inner surfaces of the feature by copper electroplating to fill the inside of the feature with copper.
  • the characteristics of the copper film are very sensitively depending upon the configuration of the seed layer and the thickness of the film.
  • the plating rate at the sites without any seed layer is very slow or produce no plating resulting in generation of voids.
  • the seed layer is not uniform in thickness or has irregularities on the surface, uniformity of the growing copper film is inhibited, that is, the thickness of copper film become not uniform during copper electroplating resulting in the formation of seams, i.e., seam like boundary in the copper film filling the inside of the feature.
  • the presence of such voids and seams may cause the confinement of plating bath components, air and moisture at the sites to reduce the reliability of the resulting semiconductor integrated circuit devices having highly packed fine interconnections. Therefore, the seed layer must be uniformly produced throughout the surfaces of the insulating layer and the inside of the feature. A non-negligible variation of the seed layer in the LSI having quite a lot of openings has an influence on the final proportion of good products, i.e., yield.
  • the present inventors have found that electroplating deposits can be grown preferentially from the bottoms of the features by using a specific additive with good reproducibility as described above.
  • the additive is a material which suppresses the electroplating reaction and is consumed as the electroplating reaction proceeds. That is, the commencement of the electroplating reaction reduces the concentration of the additive on the surfaces where the reaction is taking place. If the diffusion rate of the additive is lower than the rate of the additive reaction, the diffusion of the additive controls the electroplating reaction. Therefore, an extent of the suppression of reaction depends on the amount of the additive to be supplied to the surfaces through diffusion.
  • the additive has a very low rate of reaction, or if the rate of diffusion is very high, a sufficient amount of the additive may be supplied to the bottoms of the features. Therefore, the difference in suppression is reduced between the bottoms and the openings. If the additive has a very high rate of reaction, or if the rate of diffusion is very low, little supplement of the additive may be effected to the openings of the features. The difference in suppression is again reduced between the bottoms and the openings. Therefore, preferably the additive should be of a molecule which has a rate of diffusion and a rate of reaction in such appropriate ranges as producing a difference in concentration between the openings and the bottoms of the features. Consequently, this can be an extremely effective measure to the influence of the fluctuation of the characteristics of the aforementioned seed layer.
  • Materials useful for such an additive include 2-[(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-methyl]-1,3,3-trimethyl-3H-indolium perchlorate, 2-[3-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1-propenyl]-1,3,3-trimethyl-3H-indolium chloride, 2-[5-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1,3-pentadienyl]-1,3,3-trimethyl-3H-indolium iodide, and 2-[7-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1,3,5-heptatrienyl]-1,3,3-trimethyl-3H-indolium iodide.
  • the additive concentration outside this range may be effective as additive. If the concentration is lower than 1 mg/L, resulting effects may be insufficient, while if the concentration is higher than 15 mg/L, the concentration of impurities in the copper may possibly increased.
  • Such polyethers are preferably polyethylene glycols, polypropylene glycols, polyoxypropylene glycols having an average molecular weight of 1000 to 10,000.
  • the organic sulfur compounds are preferably 3-mercapto-1-propanesulfonic acid, 2-mercapto ethane sulfonic acid, bis(4-sulfobuthyl)disulfide, bis(3-sulfopropyl)disulfide, bis(2-sulfoethyl)disulfide, or bis(p-sulfophenyl)disulfide.
  • the copper electroplating bath according to the present invention is used in a range of 15 to 35° C. in order to avoid excessive decomposition of an additive.
  • a concentration of copper ions of 0.2 mol/L or more is preferred and usually used in a range of current density of 0.2 to 3.0 A/dm 2 (square decimeter).
  • the plating bath should be stirred with a pump or air, or the substrate should be rotated or vibrated in order to maintain the supply of the additive constant.
  • an insulating layer 2 of SiO 2 having a thickness of 1.0 ⁇ m was formed on the surface of a silicon substrate of ⁇ 200 mm, and etched by ordinary dry etching to from vias 3 having ⁇ 0.25 ⁇ m and a depth of 1 ⁇ m.
  • FIG. 1B shows a cross-sectional view of the structure after the copper seed layer was formed.
  • Sample Nos. 1 to 8 in Table 1 indicate copper electroplating baths according to the present invention, and Sample No. 9 was indicates a copper electroplating bath outside the present invention prepared for comparison.
  • A-1 2-[(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-methyl]-1,3,3-trimethyl-3H-indolium perchlorate.
  • A-2 2-[3-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1-propenyl]-1,3,3-trimethyl-3H-indolium chloride.
  • A-3 2-[5-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1,3-pentadienyl]-1,3,3-trimethyl-3H-indolium iodide.
  • A-4 2-[7-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1,3,5-heptatrienyl]-1,3,3-trimethyl-3H-indolium iodide.
  • B-1 Polyethylene glycol (an average molecular weight of 3000).
  • B-2 Polyethylene glycol (an average molecular weight of 1000).
  • B-3 Polypropylene glycol (an average molecular weight of 3000).
  • B-4 Polypropylene glycol (an average molecular weight of 1000).
  • C-1 3-mercapto-1-propanesulfonic acid.
  • C-2 2-mercapto ethane sulfonic acid.
  • C-3 bis(3-sulfopropyl)disulfide.
  • C-4 bis (2-sulfoethyl)disulfide.
  • Each electroplating was conducted at a current density as indicated in Table 1 for a period of time capable of providing a charge corresponding to the formation of a film thickness of 1.0 ⁇ m.
  • the electroplating was conducted for a period of time capable of providing a charge corresponding to the formation of a film thickness of 0.03 ⁇ m.
  • the temperature was at 24° C. and the total amount of liquid was 20 liter in a bath.
  • As anode electrode phosphorus-containing copper was used.
  • the electroplating bath was circulated through a filter at a rate of 15 liter/min with an external pump.
  • the cross-section of the plated film was observed by a scanning electron microscope (SEM) where the substrate structure after plated (FIG. 1C) was processed with FIB (Focused Ion Beam) and the cross-sections of 100 vias were observed.
  • SEM scanning electron microscope
  • FIG. 3 the thickness of plated film (A) on the surface of the substrate on the way of plating and the thickness of plated film on the bottom of vias (B) were measured and the ratio of B/A was calculated.
  • the uniformity in sheet resistance of plated copper film was evaluated based on measurements at 49 points by a four probe method of the resistivity measurement.
  • the designations of the signs in the column “Type of Cyanine Dye” in Table 2 are the same as those in Table 1. They are reused for convenience.
  • the B/A is the ratio of the film thickness on the bottoms of the features (B) to that on the surface (A).
  • Sample Nos. 3 to 8 contained a polyether, an organic sulfur compound and halide ions in addition to cyanine dye. It has been found that they achieved a good filling property as well as a good uniformity in film thickness on the plane of the substrate with good reproducibility as can be seen from the excellent uniformity in sheet resistance in a range of 3 to 5%. Moreover, the EM resistance of the interconnections was also improved. Therefore, it has been found that the semiconductor integrated circuit devices having an excellent reliability can be produced.
  • Sample Nos. 5 to 8 made it possible to further facilitate the growth of film to be preferentially plated on the bottoms (FIG. 3) by rendering the concentration of cyanine dye appropriate as can be seen from the high ratio of B/A in a range of 4.5 to 6.1.
  • FIG. 1 shows a cross-sectional view of a major part of a semiconductor integrated circuit device having a plurality of semiconductor circuit element areas formed therein (not shown) at each step of the process for the production of the device. It shows an example where the present invention is applied to fill the inside of the features for connecting a plurality of interconnection layers at different levels with copper by electroplating.
  • a substrate 1 has an interconnection layer (not shown) which is formed on an insulating layer coating the surface of a silicon wafer of ⁇ 200 mm which has a plurality of semiconductor circuit element areas (not shown) formed, said interconnection layer being connected to said plurality of semiconductor circuit element areas.
  • An insulating interlayer 2 of SiO 2 or the like having a thickness of 1 ⁇ m was deposited on the top surface of the substrate.
  • Said interlayer has the bottom surface in contact with the top surface of said interconnection layer (that is, it terminates at the contact) and it was provided with vias 3 having such a high aspect ratio as having ⁇ 0.25 ⁇ m and a depth of 1 ⁇ m for connecting between interconnection layers. At the bottoms of the vias, said interconnection layer is exposed.
  • a barrier layer 4 is deposited continuously on the top surface of the insulating layer 2 and a seed layer 5 is deposited on the barrier layer. The exposed portions of the surface of the interconnection layer at the bottoms of the holes are covered with the barrier layer 4 to be electrically connected.
  • a copper layer 6 is plated on the surface of the seed layer 5 using the copper electroplating bath according to the present invention as described above, to fill the vias 3 with the copper.
  • the substrate which was plated by the process as described above was removed from the copper electroplating bath and washed with distilled water for 3 minutes. Then it was processed with FIB and the cross-sections of 100 vias were observed by SEM. As a result, it was found that voids or seams were not observed and the vias 3 were perfectly filled with copper.
  • an insulating layer (not shown) of SiN or the like was coated to prevent the diffusion of copper, and in addition an insulating layer (not shown) of SiO 2 or the like is deposited.
  • the insulating film (SiO 2 film) and the insulating layer (SiN layer) on the aforementioned filled copper film may be selectively removed by dry etching to form an interconnection structure having a plurality of vias as shown in FIG. 1A.
  • the semiconductor integrated circuit devices produced as described above according to the present invention have neither void, nor seam in the copper film filled in the vias 3 which are the key to the construction of the multi-layer fine pattern interconnection system. Therefore, the semiconductor integrated circuit devices having a highly reliable multi-layer interconnection structure can be reproducibly produced at high yield.
  • FIG. 2 is for explaining the process for production of a semiconductor integrated circuit device having a plurality of semiconductor circuit element areas (not shown) formed therein. It shows an example where the present invention is applied to fill the inside of features for forming interlayer connections connecting a plurality of interconnection layers at different levels, or therebetween, with copper, respectively.
  • FIGS. 2A, 2B, 2 C and 2 D show a cross-sectional view of a major part of the device at each step of the process for producing the device.
  • a substrate 1 has first interconnection layer (not shown) on an insulating layer which is coated on the silicon wafer of ⁇ 200 mm which has a plurality of semiconductor circuit element areas (not shown) formed therein in the same manner as in Example 2, said first interconnection layer being connected to said plurality of semiconductor circuit element areas.
  • Insulating interlayers 8 and 2 of SiO 2 or the like, each having a thickness of 0.5 ⁇ m were deposited on the top surface of the substrate.
  • vias 3 for connecting between interconnection layers, having a stairs type cross-section through the insulating layers 8 and 2 and having a high aspect ratio which consists of a via having ⁇ 0.25 ⁇ m and a depth of 1 ⁇ m and having the bottom in contact with the top surface of said first interconnection layer to expose the top surface therein, and a trench or via having ⁇ 0.25 ⁇ m and a depth of 0.5 ⁇ m terminating at the surface of the insulating layer 8 , both vias being in conjunction with each other to form said stairs type.
  • a trench 7 for forming narrow and long interconnection extending on the surface of the insulating layer 2 , having a high aspect ratio such as width 0.25 ⁇ m and a depth of 0.5 ⁇ m and having the bottom on the insulating layer 8 .
  • the thus produced interconnect structure is provided with a barrier layer 4 and a seed layer 5 (FIG. 2B) as in Example 2, and further a copper layer 6 is plated on the seed layer 5 using the copper electroplating bath of the present invention (FIG. 2C).
  • the metal layers on the surface of the insulating layer 2 were removed by a CMP technique to produce a flat insulating surface at the same level as the surfaces of the copper layers 11 and 12 which were filled in the features 3 and 7 (FIG. 2D).
  • Example 2 the substrate after the step shown in FIG. 2C was completed was removed from the copper electroplating bath as a sample and processed with FIB.
  • the cross-sections of 100 vias 3 and 100 trenches 7 were observed by SEM. As a result, it was found that neither void, nor seam was observed and the openings were perfectly filled with copper.
  • LSIs Large scale integrated circuits
  • Such LSIs will require a multi-layer fine pattern interconnection structure which is produced with copper layers filled by plating in a plurality of features having different depths and shapes as described in the present Example 3 in relation to the process of production and the configuration of circuits.
  • Application of the present invention allows high reliability LSIs to be produced in large scale at a high yield.
  • the inside of features can be reproducibly filled with copper without apertures such as voids and seams by allowing copper plating to proceed preferentially from the bottoms of the features.
  • the possibility of forming fine vias and trenches not having any apertures such as voids and seams can improve the reliability of high density semiconductor integrated circuit devices having fine interconnections filled with copper and the yield of the production thereof.
  • a copper electroplating bath comprising a solution containing copper ions and electrolyte(s) with an addition of cyanine dye(s).
  • a copper electroplating bath comprising a solution containing copper ions and electrolyte(s) with an addition of indolium compound(s).
  • a copper electroplating bath comprising a solution containing copper ions and electrolyte(s) with an addition of at least one of the compounds represented by the following general formula (I):
  • X ⁇ is an anion
  • n is 0, 1, 2, or 3.
  • a process for producing a semiconductor integrated circuit device characterized in that said process comprising providing an insulating layer having features on the top of the major surface of a semiconductor wafer which has a plurality of circuit element areas formed, depositing a barrier metal layer and a seed metal layer on the bottoms and the side surfaces of said features and on the top surface of said insulating layer, and filling the inside of said features with copper by electroplating with the copper electroplating bath according to any one of above items (1) to (5).

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US20040211673A1 (en) * 2001-12-18 2004-10-28 Morita Chemical Industries Co., Ltd. Semiconductor integrated circuit and a method for forming the same
US20050061683A1 (en) * 2003-09-22 2005-03-24 Semitool, Inc. Thiourea-and cyanide-free bath and process for electrolytic etching of gold
US20050092616A1 (en) * 2003-11-03 2005-05-05 Semitool, Inc. Baths, methods, and tools for superconformal deposition of conductive materials other than copper
US20060163725A1 (en) * 2005-01-27 2006-07-27 Toshio Haba Wiring board and production method thereof
US20060180472A1 (en) * 2005-01-27 2006-08-17 Toshio Haba Metal structure and method of its production
US20060191784A1 (en) * 2005-02-28 2006-08-31 Hitachi Global Storage Technologies Methods and systems for electroplating wafers
US20090057156A1 (en) * 2007-08-30 2009-03-05 Hitachi Cable, Ltd. Production method for wiring and vias
US20100276292A1 (en) * 2009-04-30 2010-11-04 Moses Lake Industries Inc. High speed copper plating bath
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JP2004342750A (ja) 2003-05-14 2004-12-02 Toshiba Corp 電子デバイスの製造方法
JP4644447B2 (ja) * 2004-06-25 2011-03-02 株式会社日立製作所 プリント配線板の製造方法
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CN105244271A (zh) * 2015-10-14 2016-01-13 上海华力微电子有限公司 一种减少厚膜电镀缺陷的方法

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