US20020070912A1 - Display device - Google Patents

Display device Download PDF

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Publication number
US20020070912A1
US20020070912A1 US09/998,689 US99868901A US2002070912A1 US 20020070912 A1 US20020070912 A1 US 20020070912A1 US 99868901 A US99868901 A US 99868901A US 2002070912 A1 US2002070912 A1 US 2002070912A1
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United States
Prior art keywords
signal lines
driving circuit
display region
display device
thin film
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Abandoned
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US09/998,689
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English (en)
Inventor
Hiroaki Asuma
Atsushi Hasegawa
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Hitachi Ltd
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Individual
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Assigned to HITACHI, LTD. reassignment HITACHI, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ASUMA, HIROAKI, HASEGAWA, ATSUSHI
Publication of US20020070912A1 publication Critical patent/US20020070912A1/en
Priority to US11/396,527 priority Critical patent/US7701431B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections

Definitions

  • the present invention relates to a display device, and more particularly, to an active-matrix type liquid crystal display device which forms a liquid crystal display driving circuit on the liquid-crystal-side surface of one of substrates which are arranged to face each other with liquid crystal therebetween.
  • an active-matrix type display device defines pixel regions on a liquid-crystal-side surface of one of the transparent substrates which are arranged to face each other with liquid crystal therebetween, wherein the pixel regions are surrounded by gate signal lines which are extended in the x direction and are arranged in parallel in the y direction and drain signal lines which are extended in the y direction and are arranged in parallel in the x direction.
  • each pixel region is provided with a thin film transistor which is driven by scanning signals from a gate signal line on the one hand and a pixel electrode to which video signals are supplied from a drain signal line on the other hand through that thin film transistor.
  • These pixel electrodes generate an electric field between the pixel electrode and the counter electrode which is formed opposite it on the liquid-crystal-side surface of the other transparent substrate having intensity which corresponds to the video signal, so as to control the light transmittivity of the liquid crystal.
  • liquid crystal display device which also comprises a scanning signal driving circuit and a video signal driving circuit for respectively supplying signals to respective gate signal lines and respective drain signal lines on the other transparent substrate on the side facing the liquid crystals.
  • Each circuit is comprised of a large number of MIS (Metal-Insulator-Semiconductors) type transistors having a constitution similar to that of the thin film transistor in the pixel region. These circuits can be formed simultaneously with the formation of the pixels.
  • MIS Metal-Insulator-Semiconductors
  • polycrystalline silicon (Poly-Si) has been used as semiconductor layers of the thin film transistor and the MIS type transistor.
  • the present invention has been made in view of such circumstances and it is an object of the present invention to provide a display device which can minimize the power consumption.
  • a display device is characterized in that
  • gate signal lines which are extended in the x direction and are arranged in parallel in they direction, scanning signal driving circuits which supply scanning signals to respective gate signal lines, drain signal lines which are extended in the y direction and are arranged in parallel in the x direction, and video signal driving circuits which supply video signals to respective drain signal lines are formed on one of substrates on the surface facing the liquid-crystals which are arranged to face each other in an opposed manner with liquid crystal between them,
  • the display device includes a thin film transistor which is driven by the scanning signals from one side of the gate signal line, and a pixel electrode to which the video signals from one side of the drain signal line are supplied through the above thin film transistor in each pixel region which is surrounded by the respective signal lines,
  • a display region which is a collection of the above pixel regions is distinguished from the other display regions using imaginary lines extending along the x direction as boundaries,
  • the scanning signal driving circuit which supplies the scanning signals to respective gate signal lines in one display region and the scanning signal driving circuit which supplies the scanning signals to respective gate signal lines in the other display region are separately formed,
  • drain signal lines at one display region are separated from the drain signal lines at other display regions, and
  • the video signal driving circuit which supplies the video signals to respective drain signal lines in one display region and the video signal driving circuits which supply the video signals to respective drain signal lines in other display region are separately formed.
  • a display device is characterized in that
  • gate signal lines which are extended in the x direction and are arranged in parallel in the y direction, a scanning signal driving circuit which supplies scanning signals to respective gate signal lines, drain signal lines which are extended in the y direction and are arranged in parallel in the x direction, and a video signal driving circuit which supplies video signals to respective drain signal lines are formed on one of substrates which are arranged to face each other with liquid crystal inserted between them, on the surface of the substrate facing the liquid crystals.
  • the display device includes a thin film transistor which is driven by the scanning signals from one side of the gate signal line and a pixel electrode to which the video signals from one side of the drain signal line are supplied through that thin film transistor in each pixel region which is surrounded by the respective signal lines,
  • the video signal driving circuit includes a dynamic memory which is comprised of a plurality of other thin film transistors formed in parallel with the above-mentioned thin film transistor, and
  • At least one thin film transistor among a plurality of thin film transistors is covered with a conductive film having a potential which is fixedly secured by way of an insulation film.
  • the display device having such a constitution can increase the capacity in the thin film transistors which constitutes the dynamic memory so that the generation of a leak current can be suppressed.
  • a display device is characterized in that
  • the display device includes a liquid crystal display panel and a backlight which is arranged at the rear of the liquid crystal display panel,
  • gate signal lines which are extended in the x direction and are arranged in parallel in the y direction, a scanning signal driving circuit which supplies scanning signals to respective gate signal lines, drain signal lines which are extended in the y direction and are arranged in parallel in the x direction, and a video signal driving circuit which supplies video signals to respective drain signal lines are formed on a one of substrates which are arranged to face each other in an opposed manner with liquid crystal inserted between them, on the side facing the liquid-crystal,
  • the display device includes a thin film transistor which is driven by the scanning signals from one side of the gate signal line and a pixel electrode to which the video signals from one side of the drain signal line is supplied through the thin film transistor in each pixel region which is surrounded by the respective signal lines,
  • the video signal driving circuit includes a dynamic memory which is comprised of a plurality of other thin film transistors formed in parallel with the above-mentioned thin film transistor, and
  • a light shielding film which prevents the backlight from irradiating the dynamic memory is formed on the substrate on the side which faces the backlight.
  • the liquid crystal display device having such a constitution can shield the irradiation of an external light to the thin film transistors which constitutes the dynamic memory so that it becomes possible to operate the dynamic memory normally.
  • FIG. 1 is an overall equivalent circuit diagram showing one embodiment of a liquid crystal display device according to the present invention.
  • FIG. 2 is an equivalent circuit diagram showing one embodiment of a video signal driving circuit of the liquid crystal display device according to the present invention.
  • FIG. 3 is a plan view showing one embodiment of a pixel in the liquid crystal display device according to the present invention.
  • FIG. 4 is a cross-sectional view taken along a line IV-IV in FIG. 3.
  • FIG. 5 is a plan view showing one embodiment of a dynamic memory (1 bit) of the liquid crystal display device according to the present invention.
  • FIG. 6 is a cross-sectional view taken along a line VI-VI in FIG. 5.
  • FIG. 7 is an equivalent circuit diagram showing one embodiment of a dynamic memory of the liquid crystal display device according to the present invention.
  • FIG. 8 is an operation explanatory view of the dynamic memory of the liquid crystal display device according to the present invention.
  • FIG. 9 is a cross-sectional view showing one embodiment of the liquid crystal display panel according to the present invention.
  • FIG. 10 is an explanatory view showing one embodiment of a liquid crystal display driving method according to the present invention.
  • FIG. 1 is an scale circuit diagram showing one embodiment of a liquid crystal display device according to the present invention. Although the drawing is the circuit diagram, it is illustrated corresponding to the actual geometric arrangement.
  • a transparent substrate SUB 1 is shown.
  • the transparent substrate SUB 1 is arranged to directly face a transparent substrate SUB 2 (not shown in the drawing) with liquid crystal inserted between them.
  • the transparent substrate SUB 2 at least covers the liquid crystal display portion AR and is fixedly secured to the transparent substrate SUB 1 using a sealing agent SL which also forms the periphery of the liquid crystal display portion AR (see FIG. 9).
  • gate signal lines GL which are extended in the x direction and are arranged in parallel in the y direction and drain signal lines DL which are insulated from the gate signal lines GL, are extended in they direction and are arranged in parallel in the x direction are formed.
  • Each rectangular region which is formed by a pair of respective gate signal lines GL and a pair of drain signal lines DL constitutes a pixel region.
  • a collection of these pixel regions which are arranged in a matrix array constitutes the liquid crystal display portion AR.
  • the respective drain signal lines DL are formed such that they are divided at the center of the liquid crystal display portion AR. That is, the liquid crystal display portion AR is conceptually divided into the respective pixel regions which are formed of respective gate signal lines GL ranging from the gate line of the 1st row constituting the uppermost edge to the gate line of the ith row (referred to as “front stage display portion ARf” hereinafter) and respective gate signal lines GL ranging from the gate line of the (i ⁇ 1)th row line to the lowermost nth row line (referred to as “back stage display portion ARb” hereinafter).
  • the drain signal lines DL which are in charge of the front-stage display portion ARf and the drain signal lines DL which are in charge of the back-stage display portion ARb are arranged such that they are electrically separated.
  • the value of “i” differs depending on the use of the liquid crystal display device and the “i” may be at the upper stage side with respect to the center of the liquid crystal display portion AR (the center in the y direction in the drawing) or may be at the lower stage side with respect to the center of the liquid crystal display portion AR.
  • one side (the right side in the drawing) of the respective gate signal lines GL in the front-stage display portion ARf are connected to a pixel driving shift register if which constitutes the scanning signal driving circuit, while the pixel driving shift register 1 f is driven by a start pulse clock signal supplied from outside the liquid crystal display device.
  • one side (the right side in the drawing) of the respective gate signal lines GL in the back-stage display portion Arb are connected to a pixel driving shift register 1b which is provided separately from the above-mentioned pixel driving shift register 1 f , while this pixel driving shift register 1 b is also driven by the above-mentioned start pulse clock signal.
  • the video signal driving circuit is comprised of a D-A converting circuit 2 f , a memory 3 f , an input data take-in (output) circuit 4 f , and an H-side address decoder 5 f which are sequentially arranged in parallel in this order starting from the drain signal line DL, and a V-side address decoder 6 f and a memory driving shift register 7 f which are connected to the memory 3 f.
  • the memory driving shift register 7 f is configured to be driven by inputting the above-mentioned start pulse clock signal.
  • FIG. 2 A more detailed configuration of such a video signal driving circuit is shown in FIG. 2.
  • one side (the lower side in the drawing) of the respective gate signal lines GL in the back-stage display portion ARb are connected to a video signal driving circuit which is provided separately from the above-mentioned video signal driving circuit.
  • This video signal driving circuit is, in the same manner as the above-mentioned video signal driving circuit, comprised of a D-A converting circuit 2 b , a memory 3 b , an input data take-in (output) circuit 4 b , and an H-side address decoder 5 b which arranged in parallel in order from the drain signal line DL side, and a V-side address decoder 6 b and a memory driving shift register 7 b which are connected to the memory 3 b.
  • the memory driving shift register 7 b is configured to be driven by inputting the above-mentioned start pulse clock signal.
  • the display in the liquid crystal display portion AR, while of course the display can be performed over the whole area, the display may be performed only at the front-stage display portion ARf or the display may be performed only at the back-stage display portion ARb.
  • the liquid crystal display device of this embodiment when used as a liquid crystal display device in a portable telephone, for example, a mode in which information such as date, time, sensitivity of antenna and the like (information that can be displayed on a portion of the panel) is displayed as images at the front-stage display portion ARf and the back-stage display portion ARb is not driven can be realized.
  • the liquid crystal display device can be configured not to supply the electric power to respective gate signal lines GL of the back-stage display portion ARb so that the lowering of the power consumption can be effectively enhanced.
  • FIG. 3 is a plan view which shows one embodiment of the pixel. This drawing particularly shows the pixel at a portion where the drain signal lines DL are separated. That is, the drawing shows a portion of the upper-side pixel and a portion of the lower-side pixel with respect to the gate signal line GL which intersects the drain signal line DL.
  • FIG. 4 is a cross-sectional view taken along a line IV-IV in FIG. 3.
  • a semiconductor layer AS which is made of poly-Si is formed on an upper surface of the transparent substrate SUB 1 at a region where a thin film transistor TFT is formed.
  • a first insulation film GI which is made of SiO 2 , for examples is formed over the transparent substrate SUB 1 such that the first insulation film GI also covers the semiconductor layer AS.
  • This first insulation film GI functions as a gate insulation film in the region where the thin film transistor TFT is formed and functions as a dielectric film in a region where a capacitive element Cstg which will be explained later is formed.
  • the gate signal line GL is formed on the surface of the insulation film GI such that the gate signal line GL is extended in the x direction in the drawing.
  • This gate signal line GL is formed such that a portion thereof is extended into the pixel region and is astride the semiconductor layer AS thus forming a gate electrode GT of the thin film transistor TFT.
  • a storage line SL is formed simultaneously with the formation of the gate signal line GL.
  • the storage line SL is arranged substantially parallel to the gate signal line GL and an extension portion having a relatively large area is defined between the storage line SL and the gate signal line GL.
  • This extension portion of the storage line SL is configured to form one of electrodes of the capacitive element Cstg.
  • a second insulation film IN which is for example made of SiO 2 is formed over the surface of the transparent substrate SUB 1 such that the second insulation film IN also covers the gate signal line GL and the storage line SL.
  • This second insulation film IN functions as an interlayer insulation film of the drain signal line DL which will be explained later with respect to the gate signal line GL and also functions as a dielectric film in the region where the capacitive element Cstg is formed.
  • contact holes CH 1 , CH 2 are formed in the second insulation film IN such that these contact holes CH 1 , CH 2 penetrate and reach the first insulation film GI which constitutes the lower layer so that portions of the drain region and the source region of the thin film transistor TFT are respectively exposed.
  • the drain signal line DL which is extended in the y direction in the drawing is formed on the upper surface of the second insulation film IN and the source electrode SD 2 is formed on the upper surface of the second insulation film IN simultaneously with the drain signal line DL.
  • the drain signal line DL is formed such that the drain signal line DL runs over the contact hole CHI. Due to such a constitution, the drain signal line DL of the contact hole CH 1 portion also acts as the drain electrode SD 1 of the thin film transistor TFT.
  • the drain signal line DL is separated on the gate signal line GL, wherein a separated end portion of one side of the drain signal line DL and a separated end portion of the other side of the drain signal line DL are both superposed on the gate signal line GL.
  • Such a provision is adopted to prevent the leaking of external light (such as light from the backlight) by shielding with the gate signal line GL.
  • the light shielding of the cut portion of the drain signal line DL is performed by the gate signal line GL.
  • the source electrode SD 2 is formed such that the source electrode SD 2 covers the contact hole CH 2 .
  • the source electrode SD 2 is also provided with an extension which is superposed on a portion of the storage line SL and an extension thereof.
  • the extension of the source electrode SD 2 constitutes one electrode of the capacitive element Cstg.
  • a third insulation film PSV which is made of SiO 2 , for example, is formed over the transparent substrate SUB such that the third insulation film PSV also covers the drain signal line DL and the source electrode SD 2 .
  • This third insulation film PSV functions as a protective film which prevents liquid crystal from being brought into direct contact with the thin film transistor TFT.
  • a contact hole CH 3 which exposes a portion of the extension of the source electrode SD 2 is formed in the third insulation film PSV.
  • a pixel electrode PX which is made of ITO (indium-tin-oxide), for example, is formed on an upper surface of the third insulation film PSV such that the pixel electrode PX also covers the contact hole CH 3 .
  • FIG. 5 is a plan view showing a portion of the above-mentioned memory shown in FIG. 1 corresponding to 1 bit. Further, FIG. 6 is a cross-sectional view taken along a line VI-VI of FIG. 5.
  • the memory at this portion is a so-called dynamic memory and scale size circuit diagram thereof is shown in FIG. 7.
  • the constitution shown in FIG. 5 substantially matches the scale circuit shown in FIG. 7 with respect to the geometric arrangement.
  • the memory shown in FIG. 5 is formed along with the formation of the above-mentioned pixels.
  • a semiconductor layer AS 1 and a semiconductor layer AS 2 which are made of poly-Si are formed on a surface of a transparent substrate SUB 1 .
  • the semiconductor layer AS 1 is used as a semiconductor layer which is part of a thin film transistor TFT 1
  • the semiconductor layer AS 2 is used as a semiconductor layer which constitutes a thin film transistor TFT 2 and a thin film transistor TFT 3 .
  • These semiconductor layers AS 1 , AS 2 are simultaneously formed with the formation of the semiconductor layer AS of the thin film transistor TFT in the liquid crystal display portion AR.
  • a first insulation film GI which is made of SiO 2 is formed on an upper surface of the transparent substrate SUB such that the first insulation film GI also covers these semiconductor layers AS 1 , AS 2 .
  • This first insulation film GI functions as gate insulation films of the thin film transistors TFT 1 to TFT 3 .
  • a gate wiring layer G 1 and a refresh wiring layer Rl which are extended in the x direction in the drawing are formed on an upper surface of the first insulation film GI.
  • the gate wiring layer Gl and the refresh wiring layer Rl are simultaneously formed with the formation of the gate signal line GL in the liquid crystal display portion AR.
  • the gate wiring layer Gl is formed such that the gate wiring layer G 1 transverses a portion of the semiconductor layer AS 1 thus forming a gate electrode of the thin film transistor TFT 1
  • the refresh wiring layer Rl is formed such that the refresh wiring layer Rl transverses a portion of the semiconductor layer AS 2 thus forming a gate electrode of the thin film transistor TFT 3 .
  • a second insulation layer IN which is made of SiO 2 is formed on the upper surface of the transparent substrate SUB such that the second insulation layer IN also covers the gate wiring layer Gl and the refresh wiring layer Rl.
  • the second insulation film IN functions as an interlayer insulation film for the gate wiring layer Gl and the refresh wiring layer Rl with respect to a drain wiring layer Dl which will be explained later.
  • a drain region and a source region of the thin film transistor TFT 1 , a source region of the thin film transistor TFT 2 , and a drain region and a source region of the thin film transistor TFT 3 , a portion of the refresh wiring layer Rl, and a portion of a gate electrode GT 3 are exposed by contact holes CH 4 , CH 5 , CH 6 , CH 7 , CH 8 and CH 9 through the second insulation film IN.
  • the drain wiring layer Dl which is extended in the y direction is formed on an upper surface of the second insulation film IN and this drain wiring layer Dl is connected to the drain region of the thin film transistor TFT 1 and the drain region of the thin film transistor TFT 3 .
  • This drain wiring layer Dl is simultaneously formed with the drain signal line DL in the liquid crystal display portion AR.
  • the gate electrode GT 3 which is simultaneously formed with the gate wiring layer Gl is formed such that the gate electrode GT 3 transverses the semiconductor layer AS 2 of the thin film transistor TFT 2 .
  • the gate electrode GT 3 is connected to the source region of the thin film transistor TFT 1 .
  • a conductive layer Cl which is simultaneously formed with the drain wiring layer Dl is also formed such that the conductive layer Cl establishes the connection between the source region of the thin film transistor TFT 2 and the refresh wiring layer Rl.
  • a third insulation film PSV which is made of SiO 2 is formed on the upper surface of the transparent substrate SUB such that the third insulation film PSV also covers the drain wiring layer Dl, the gate electrode GT 3 and the conductive layer Cl.
  • the third insulation film functions as an insulation film for protecting the thin film transistors TFT1 to TFT3.
  • the conductive layer CL which is made of an ITO (Indium-Tin-Oxide) film is formed on an upper surface of the third insulation film PSV.
  • the conductive layer CL is formed simultaneously at the time of forming the pixel electrodes PX in the liquid crystal display portion AR.
  • the conductive layer CL is formed such that the conductive layer CL covers the gate region of the thin film transistor TFT 2 .
  • the conductive layer CL is not limited to such a constitution and the conductive layer CL may be formed such that the conductive layer CL covers the respective gate regions of other thin film transistor TFT 1 , TFT 3 .
  • the conductive layer CL is held at a fixed potential such as a ground potential, a power supply potential or the like.
  • the memory having such a constitution can be increased in storage capacity so that it becomes possible to obtain an advantageous effect that a margin of time beyond that necessary for holding the memory before which there is no leakage of current is generated in the respective thin film transistors TFT 1 to TFT 3 .
  • FIG. 8( a ) is a view which shows the manner of operation of the dynamic memory, wherein (1) resetting of data lines (drain wiring layers) to a ground (GND), (2) data reading operation, (3) rewriting of data and (4) writing of new data are respectively indicated by the flow of electric current.
  • FIG. 8( b ) indicates timing charts of respective signals.
  • FIG. 9 is a view which shows the relationship between a liquid crystal display panel PNL which uses a transparent substrate SUB 1 and a substrate SUB 2 which are arranged to face each other with liquid crystal LC inserted between them, the substrates acting as an envelope and a backlight BL which is arranged at the back surface of the liquid crystal display panel (with respect to an observer).
  • a polarization film POL 2 is formed on the surface of the transparent substrate SUB 1 opposite to the liquid crystal, while a polarization film POL 1 is formed on a surface of the transparent substrate SUB 2 opposite to the liquid crystal.
  • the transparent substrate SUB 2 is fixedly secured to the transparent substrate SUB 1 by a sealing agent SL which also has a function of sealing liquid crystal between the transparent substrates SUB 1 and SUB 2 .
  • a light shielding film BT is formed on a backlight (BL) side of the transparent substrate SUB 1 and this light shielding film BT prevents the light irradiated from the backlight BL from being irradiated to at least the H-side address decoder, the input data take-in (output) circuit and the memory shown in FIG. 1 respectively.
  • the light shielding film BT may be formed on the whole peripheral region of the liquid crystal display portion AR (region formed of the mass of the pixels), only opening the liquid crystal display portion AR.
  • the liquid crystal display panel PNL which has such a constitution can prevent the light from the backlight BL from being irradiated to respective thin film transistors TFT 1 to TFT 3 which constitute the dynamic memory so that it becomes possible to obtain an advantageous effect that the occurrence of erroneous operations can be avoided. That is, when the dynamic memory is used, the adverse influence derived from photons generated in the semiconductors due to the irradiation of light is extremely large. The liquid crystal display panel PNL can overcome such a problem.
  • the circuits such as the dynamic memory and the like are formed on the liquid-crystal side of the transparent substrate SUB 1 which is opposite the backlight BL.
  • these circuits may be formed on the other transparent substrate SUB 2 .
  • a black vinyl film or the like may be used as the light shielding film BT.
  • FIG. 10 shows a driving method of the liquid crystal display panel PNL, and more particularly, a driving method of pixel driving shift registers 1 f , 1 b and a method for transmitting video signals from the video signal driving circuit which becomes necessary along with the driving method of the liquid crystal display panel PNL.
  • the liquid crystal display portion AR is divided into the front-stage display portion ARf and the back-stage display portion ARb and the scanning signals are supplied to the gate signal lines GL through the separate pixel driving shift registers i f , 1 b respectively.
  • the scanning signals are supplied to respective gate signal lines GL in the directions (directions A) moving away from the gate signal line GL of the front-stage display portion ARf side and the gate signal line GL of the back-stage display portion ARb side which are present at the boundary of the front-stage display portion ARf and the back-stage display portion ARb.
  • the scanning signals are sequentially supplied to respective gate signal lines GL along directions (directions B) which approach the boundary between the front-stage display part ARf and the back-stage display part ARb. That is, the scanning signal lines are firstly supplied to the gate signal line GL of the front-stage part ARf side and the gate signal line GL of the back-stage part ARb side which are disposed remotest from the boundary and then are sequentially supplied to other gate signal lines GL of the front-stage part ARf side and other gate signal lines GL of the back-stage part ARb side along the directions B.
  • the leak current which is generated in the thin film transistors which constitute the dynamic memory in the inside of the video signal driving circuit can be suppressed.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
US09/998,689 2000-12-07 2001-12-03 Display device Abandoned US20020070912A1 (en)

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JP2000373171A JP2002175056A (ja) 2000-12-07 2000-12-07 液晶表示装置

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US20090046042A1 (en) * 2007-08-15 2009-02-19 Au Optronics Corporation Drive Method for Reducing the Power Consumption of a Flat Display
US20090096944A1 (en) * 2007-10-16 2009-04-16 Kikuo Ono Liquid Crystal Display Device
US20090127561A1 (en) * 2007-11-15 2009-05-21 Takeshi Shiomi Semiconductor device, display device and mobile device
US10229620B2 (en) 2014-06-02 2019-03-12 Samsung Display Co., Ltd. Display panel and display apparatus having the same
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TWI239424B (en) * 2003-10-15 2005-09-11 Hannstar Display Corp Liquid crystal display panel and driving method therefor
JP4942341B2 (ja) * 2004-12-24 2012-05-30 三洋電機株式会社 表示装置
JP2007128029A (ja) 2005-10-04 2007-05-24 Mitsubishi Electric Corp 表示装置
CN100559440C (zh) * 2007-11-08 2009-11-11 友达光电股份有限公司 降低平面显示器功率消耗的驱动方法
US8125472B2 (en) * 2009-06-09 2012-02-28 Global Oled Technology Llc Display device with parallel data distribution
JP6087956B2 (ja) * 2012-12-03 2017-03-01 シャープ株式会社 薄膜トランジスタアレイ基板、及び、液晶表示装置
CN104835441B (zh) * 2015-05-25 2017-10-31 京东方科技集团股份有限公司 显示控制电路及方法、显示装置
CN110619858B (zh) * 2019-10-29 2021-08-13 上海中航光电子有限公司 移位寄存器、栅极驱动电路和显示面板

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KR20050074369A (ko) 2005-07-18
US7701431B2 (en) 2010-04-20
KR20020045558A (ko) 2002-06-19
CN1238827C (zh) 2006-01-25
KR100676789B1 (ko) 2007-02-02
US20060176291A1 (en) 2006-08-10
JP2002175056A (ja) 2002-06-21
CN100399119C (zh) 2008-07-02
TW561446B (en) 2003-11-11
CN1357873A (zh) 2002-07-10
KR20040108345A (ko) 2004-12-23
KR100469600B1 (ko) 2005-02-02

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