US20010042181A1

US20010042181A1 - Bus control system

Info

Publication number: US20010042181A1
Application number: US09/197,676
Authority: US
Inventors: Hirofumi Sudo
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1997-11-28
Filing date: 1998-11-23
Publication date: 2001-11-15
Anticipated expiration: 2018-11-23
Also published as: US6442668B2; CA2254525A1; GB2332291A; CN1331064C; CN1221152A; JPH11161524A; GB9825731D0; GB2332291B; CA2254525C

Abstract

A micro processor board of the bus control system comprises an internal bus which comprise a micro processor, address lines, data lines, and control signal lines, a memory connected via the internal bus with the micro processor, registers such as a system control register, and a bus interface circuit. The access to the main memory, the register, or the bus interface which is executed by the micro processor is outputted from an external bus via the bus interface circuit. Thus, the operation status of the micro processor or the internal bus can be traced by tracing the external bus.

Description

BACKGROUND OF THE INVENYION

1. Field of the Invention

The present invention relates to a bus control system and particularly, to a bus control system applicable for bus trace for monitoring the operation status of a micro processor.

2. Description of the Prior Art

There is disclosed a multi-chip module evaluating device in, for example, Japanese Patent Laid-Open No. 5-120160 (1993), which traces the wiring signal between a floating operation unit and a data memory. The wiring signal which is closed in the module substrate of a multi-chip module is traced by connecting, via a prober, a leader pad on the module substrate with a monitor unit which comprises a memory, an address generator, and a comparator. This evaluating device can trace directly the wiring signal, without using any test element group (TEG). Therefore, this evaluating device is employed for tracing the wiring signal, because an evaluation merely by signals extracted to external pins is not sufficient, in case of mounting LSI packages on the module substrate.

In this connection, the above-mentioned conventional device has the following disadvantages:

Firstly, leader pads are necessary for tracing the wiring signal, because the wiring signal is closed in the module substrate. Accordingly, the above-mentioned evaluating device is not of any use for a multi-chip module which is small-size-oriented, because the number of pads increases with the increase in the number of wiring which completes in the module substrate, which results in the increase in pads area. Secondly, a testing device is exclusively necessary for bus trace. Specially designed probers are required for connecting themselves with the special leader pads on the module substrate. Thirdly, the reliability of bus trace is lowered. When the leader pads are inferior due to a manufacturing process, then the module substrate can not be traced completely.

SUMMARY OF THE INVENTION

Therefore, an object of the present invention is to provide a bus control system with improved reliability for tracing easily the bus of a micro processor via bus interface, when evaluating bus interface peripheral circuits and the software for a micro processor board. Another object of the present invention is to improve the reliability of the evaluation system.

According to the present invention, there is provided a bus control system, which comprises a micro processor, a main memory and a system control register each of which is accessed via an internal bus by the micro processor, and a bus interface.

The bus control system of the present invention further includes a tracing means for tracing every access, by the micro processor, to the main memory, to the system control register, and to the bus interface by using an external bus via the bus interface.

According to the present invention as explained above, the following effects are obtained:

Firstly, the leader pads become unnecessary for tracing the wiring signal which is closed in a module substrate, because every status of an internal bus can be traced via the bus interface.

Secondly, a high density mounting board such as a multi-chip module can be furthermore integrated in a higher density, keeping the compatibility of function of the internal bus tracing, because the exclusive pads becomes unnecessary and the wide mounting area is preserved.

Thirdly, bus trace becomes easy, because ordinary available instruments can be used for bus trace at the external bus connected with bus interface, or the peripheral circuit of a micro processor board.

BRIEF EXPLANATION OF THE DRAWINGS

FIG. 1 is a block diagram of a bus control system of the present invention. [0014]
FIG. 2 is a timing chart for explaining the action of the bus control system of the present invention.[0015]

PREFERRED EMBODIMENT OF THE INVENTION

A preferred embodiment of the present invention is explained. The micro processor board of the bus control system of the present invention comprises an internal bus which comprise a micro processor, address lines, data lines, and control signal lines, a memory connected via the internal bus with the micro processor, registers such as a system control register, and a bus interface circuit. Every access to the main memory, the register, and the bus interface by the micro processor is outputted from an external bus via the bus interface circuit. Accordingly, the operation status of the micro processor or the internal bus can be traced by tracing the external bus. [0016]
Concretely, the micro processor indicates a write timing and read timing by using bus interface signals, when write data and read data of the micro processor are outputted from the bus interface circuit to the external bus. Thus, the data flow is traced by the external bus. [0017]
Referring to the accompanying drawings, a working example of the present invention is explained to clarify the embodiment of the present invention. [0018]
As shown in FIG. 1, micro processor board [0019] 1 comprises nicro processor 2 connected with internal bus 3, main memory 4, system control register 5,and bus interface 6. Further, micro processor board 1 is connected with external bus 7 via bus interface 6.
Next, referring to FIG. 1, the action of micro processor board [0020] 1 of the working example is explained.
[0021] Micro processor 2 accesses to main memory 4 and system control register 5 via internal bus 3. Therefore, every access in micro processor board 1 can be traced by monitoring internal bus 3.
[0022] Bus interface 6 outputs addresses, data, and control signals in internal bus 3 toward external bus 7, when micro processor 2 executes a write access to main memory 4, or system control register 5.
Also, [0023] bus interface 6 outputs addresses, data, and control signals in internal bus 3 toward external bus 7, when micro processor 2 executes a read access to main memory 4, or system control register 5.
Thus, internal bus [0024] 3 can be traced by tracing external bus 7. In other words, the execution process of a program of micro processor 2 mounted on micro processor board 1 can be traced by tracing external bus 7.
Referring to FIG. 2, the action of [0025] bus interface 6 between internal bus 3 and external bus 7 of the working example is explained.
The action of two word write into main memory by [0026] micro processor 2 as shown in FIG. 1 is shown concretely in FIG. 2.
Internal bus [0027] 3 executes a write access to main memory 4, carrying internal bus address 10 and internal bus write data 11 in micro processor 2.
[0028] Main memory 4 accepts internal bus address 10 and internal bus write data 11 and writes them by using row address strobe (RAS) control signal 12 and column address strobe (CAS) control signal 13, while bus interface 6 outputs the same address as internal bus address toward external bus address 14. At the same time bus interface 6 outputs external bus strobe 15 -to validate the external bus address.
[0029] Bus interface 6 outputs external bus data 16 which are the same as internal bus data 11. At the same time bus interface 6 outputs external bus data ready 17 synchronized with CAS control signal 13.
Thus, an effective timing of a write address and write data are confirmed by external bus [0030] 7, when micro processor 2 executes a write access to main memory 3.
Similarly, an effective timing of a read address and read data are confirmed by external bus [0031] 7, when micro processor 2 executes a read access to main memory 3. The accesses to system control register 5 are confirmed similarly. Thus, internal bus 3 can be traced by external bus 7.

Claims

What is claimed is:

1. A bus control system which comprises a micro processor, an internal bus, a main memory, a system control register, a bus interface, an external bus, and a tracing means for tracing operation states of said micro processor, wherein:

said main memory and said system control register are accessed via said internal bus by said micro processor; and

said tracing means traces, by using said external bus, via said bus interface, access which is executed by said micro processor.

2. The bus control system according to

claim 1

, wherein addresses, write data, and read data are outputted from said interface bus, and write timings and read timings are outputted using prescribed signals which run in said interface bus.

3. The bus control system to

claim 1

, wherein addresses and data in said internal bus are fed into said external bus.

4. The bus control system according to

claim 1

, wherein:

said micro processor and said bus interface are active circuits;

circuits except said micro processor and said bus interface are passive circuits; and

addresses and data of said active circuits are traced from said external bus via said bus interface by said tracing means.

5. The bus control system according to

claim 1

, which further comprises an auxiliary memory and an auxiliary register, wherein:

said internal bus includes address lines, data lines, and control signal lines; and

said auxiliary memory and said auxiliary register are connected via said internal bus with said micro processor;

6. The bus control system according to

claim 5

, wherein said bus interface activates a strobe signal for indicating that an address is outputted toward said external bus, and activates a ready signal for indicating that data are fixed.

7. The bus control system according to

claim 1

, wherein said micro processor, said internal bus, said main memory, said system control register, and said bus interface are mounted on a substrate.