CN100353350C - Assess controlling system for bus of internal integrated circuit - Google Patents
Assess controlling system for bus of internal integrated circuit Download PDFInfo
- Publication number
- CN100353350C CN100353350C CNB031473180A CN03147318A CN100353350C CN 100353350 C CN100353350 C CN 100353350C CN B031473180 A CNB031473180 A CN B031473180A CN 03147318 A CN03147318 A CN 03147318A CN 100353350 C CN100353350 C CN 100353350C
- Authority
- CN
- China
- Prior art keywords
- cpu
- equipment
- data signal
- signal line
- integrate circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Small-Scale Networks (AREA)
Abstract
The present invention relates to an assess controlling system for buses of internal integrated circuits, wherein a CPU and devices are communicated via interior integrated circuit (I<2>C) buses. The devices with the same I<2>C bus address are firstly divided into different groups, the same group devices are connected by the same data signal wire (SDA), and the different devices in each group are respectively and correspondingly connected to the same clock signal wires (SCL). The CPU sets a register, so a three-state driver in a logic device controls the switching of the devices SCL, a simulation switch controls the switching of the devices SDA, and the CPU can access the devices when the SCL and the SDA of the devices are simultaneously switched on. The present invention provides an assess controlling system for the buses of I<2>C, which is simple and reliable and has low cost, and the present invention realizes the unique hit access of the same device with the same I<2>C bus address on a single board.
Description
Technical field
The present invention relates to electric numerical data and handle, relate in particular to a kind of CPU by internal integrated circuit (I
2C) bus control system that equipment is conducted interviews.
Background technology
Flourish along with broadband networks such as Metropolitan Area Network (MAN) and enterprise network, the Ethernet switch market demand of Duo Guangkou, full light mouth increases gradually, in order to satisfy the actual demand of market networking, solve inflexible problem of light mouth configuration (multimode, single mode, middle distance, long distance) of current Duo Guangkou, full light mouth Ethernet switch, Duo Guangkou, full light mouth Ethernet switch optical interface type will be from MTRJ, small-sized SFF (Small Form Factor) but are moved towards the form of small-sized plug SFP (SmallForm-factor Pluggable).Because SFP for can plug form, is a kind of optical interface module of standard agreement, thereby helps parts selection, reduce device cost, also help light mouth flexible configuration, make the utilization of resources abundant, the situation that 40 kilometers light mouth is used in 10 kilometers use occasion can not occur.
Though the SFP flexible configuration, the management more complicated, the SFP optical module has internal integrated circuit (I
2C) bus, in order effectively to discern and manage each port device, switch software and network management system must be passed through this I
2C Serial Control bus is controlled each port.When on same veneer, using a plurality of identical ID numbers SFP optical module at present, owing to do not have the external address pin to distinguish, thereby can't realize I
2The control of the equipment that the C bus address is identical.But along with the development of SFP light jaws equipment, have a lot of identical ID number SFP optical modules on the veneer, therefore original relatively MTRJ and the Duo Guangkou of SFF, full light jaws equipment must a kind of new I of design
2The total line traffic control access mode of C comes a plurality of SFP optical modules with identical ID number are carried out unique hit access.
Summary of the invention
Technical matters to be solved by this invention is: overcome prior art and can't visit I
2The deficiency of the equipment that the C bus address is identical provides a kind of internal integrated circuit (I simple and reliable and with low cost
2C) bus access control system realizes I on the veneer
2Unique hit access of the equipment that the C bus address is identical.
The present invention solves the problems of the technologies described above the technical scheme that is adopted to be:
A kind of internal integrate circuit bus access control system, comprise CPU, internal integrate circuit bus and a plurality of equipment, wherein, described internal integrate circuit bus comprises clock cable and data signal line, described CPU and described a plurality of equipment carry out communication by described internal integrate circuit bus, also comprise logical device and switch, the identical equipment in inner Integration Bus address is connected by described logical device with clock cable between the CPU, and the break-make by described logical device control clock signal line; The identical equipment in described inner Integration Bus address is connected by described switch with data signal line between the CPU, and the break-make by described switch control data signal wire, CPU can conduct interviews to this equipment when the clock cable of described equipment and data signal line are opened simultaneously.
Described internal integrate circuit bus access control system, the identical equipment in wherein said inner Integration Bus address is connected by the three-state driver in the described logical device with clock cable between the CPU, and passes through the break-make of three-state driver control clock signal line.
Described internal integrate circuit bus access control system, wherein said switch is an analog switch, the identical equipment in described inner Integration Bus address is connected by described analog switch with data signal line between the CPU, and controls the break-make of each device data signal wire by analog switch.
Described internal integrate circuit bus access control system, also be provided with register in the wherein said logical device, CPU controls described three-state driver or analog switch by this register corresponding bits position is provided with, thus the clock cable between control CPU and each equipment or the break-make of data signal line.
Described internal integrate circuit bus access control system, wherein said register is provided with by local bus by CPU.
Described internal integrate circuit bus access control system, the identical equipment in wherein said inner Integration Bus address can be divided into different groups arbitrarily, and each equipment in every group adopts same data signal line to be connected with many different clock cables.
Described internal integrate circuit bus access control system, the identical equipment in wherein said inner Integration Bus address is the SFP optical module.
Described internal integrate circuit bus access control system, wherein for inner Integration Bus address equipment inequality, the different addresses that CPU can directly send by the protocol package hair conduct interviews to each equipment.
Described internal integrate circuit bus access control system, wherein said inner Integration Bus address each equipment inequality has identical clock cable and data signal line passage, this clock cable drives to form by logical device with the clock cable of CPU and forever is connected, and is connected but this data signal line forms gated nature with the data signal line of CPU by analog switch.
Described internal integrate circuit bus access control system, wherein said inner Integration Bus address equipment inequality is watch-dog, temperature sensor or real-time clock.
Beneficial effect of the present invention is: the invention provides a kind of novel I
2C bus access control system has realized I on the veneer
2Unique hit access of C bus address identical device can be carried out a large amount of I easily and effectively
2The control of C bus apparatus makes in the Ethernet switch and can carry out unique hit access to a plurality of SFP optical modules with identical ID number, and implementation method is simple and reliable, with low cost.
Description of drawings
Fig. 1 is an internal integrate circuit bus access control system principle schematic of the present invention.
Embodiment
With embodiment the present invention is described in further detail with reference to the accompanying drawings below:
On same veneer, CPU can carry out communication with real-time clock, watch-dog, temperature sensor and 12 SFP optical modules, thereby realizes the exchange of information such as fault, monitoring, and the communication of CPU and above-mentioned peripheral components can be passed through I
2The C bus is carried out.
Be illustrated in figure 1 as principle of the invention synoptic diagram, I
2The C bus is made of a clock cable SCL and a data signal line SDA, because the I of 12 SFP optical modules
2The address of C bus all is 0000000B, I
2C bus address undistinguishable, and real-time clock, watch-dog, temperature sensor are I
2The C bus address can be distinguished equipment.With whole I
2C equipment is 4 groups according to the multiplexing criteria of serial data bus SDA, and grouping 13 is the SFP optical module to grouping, 4 SFP optical modules is arranged in every group; Grouping 4 is I
2The differentiable equipment group in C address.Because CPU can be to I
2The differentiable equipment in C address conducts interviews by the different addresses that the protocol package hair send, thereby divides into groups 4 to be connected with SDA4 by same SCL5.For grouping 1-3, every group of SFP optical module adopts same SDA to be connected with different SCL, and SDA of each group is respectively SDA1, SDA2, SDA3, and the different SFP optical modules in every group correspondence respectively are connected on SCL1, SCL2, SCL3, the SCL4.
The SCL serial time clock line of each equipment hangs on the SCL clock line of CPU by the driving of CPLD (CPLD), and wherein SCL5 is that permanent gating hangs on the main equipment CPU, and other 4 road clock can be by the I in the CPLD
2The C bus control register is controlled the interior three-state driver of CPLD and the gating driving.
Because data line is two-way, the SDA data line of each equipment group hangs on the SDA of CPU through the isolation of analog switch, and 4 equipment groups can adopt four path analoging switch, and each SDA path all can be by the I in the CPLD
2The C bus control register is set separately and is opened or off-state.Isolate the bi-directional drive problem that can solve the open collector circuit well by analog switch.
I
2The C bus control register adopts 8 bit register, high-order 4 bits control analog switch, 4 bit control of low level three-state driver, CPU is provided with this control register according to the visit intention earlier by local bus (LOCAL BUS) interface, as shown in the table, can be by the following control (effective with high level here) that realization is set each equipment to register:
| ?Y[7] | ?Y[6] | ?Y[5] | ?Y[4] | ?Y[3] | ?Y[2] | ?Y[1] | ?Y[0] | Select the control result |
| ?0 | ?0 | ?0 | ?1 | ?0 | ?0 | ?0 | ?1 | SFP1 in the grouping 1 |
| ?0 | ?0 | ?0 | ?1 | ?0 | ?0 | ?1 | ?0 | SFP2 in the grouping 1 |
| ?0 | ?0 | ?0 | ?1 | ?0 | ?1 | ?0 | ?0 | SFP3 in the grouping 1 |
| ?0 | ?0 | ?0 | ?1 | ?1 | ?0 | ?0 | ?0 | SFP4 in the grouping 1 |
| ?0 | ?0 | ?1 | ?0 | ?0 | ?0 | ?0 | ?1 | SFP1 in the grouping 2 |
| ?0 | ?0 | ?1 | ?0 | ?0 | ?0 | ?1 | ?0 | SFP2 in the grouping 2 |
| ?0 | ?0 | ?1 | ?0 | ?0 | ?1 | ?0 | ?0 | SFP3 in the grouping 2 |
| ?0 | ?0 | ?1 | ?0 | ?1 | ?0 | ?0 | ?0 | SFP4 in the grouping 2 |
| ?0 | ?1 | ?0 | ?0 | ?0 | ?0 | ?0 | ?1 | SFP1 in the grouping 3 |
| ?0 | ?1 | ?0 | ?0 | ?0 | ?0 | ?1 | ?0 | SFP2 in the grouping 3 |
| ?0 | ?1 | ?0 | ?0 | ?0 | ?1 | ?0 | ?0 | SFP3 in the grouping 3 |
| ?0 | ?1 | ?0 | ?0 | ?1 | ?0 | ?0 | ?0 | SFP4 in the grouping 3 |
| ?1 | ?0 | ?0 | ?0 | ?0 | ?0 | ?0 | ?0 | Grouping 4 |
Like this, CPU passes through I in the CPLD
2The setting of C bus control register visits different grouping and different SFP modules, has realized the unique hit access to 12 optical modules.
If the selection of SDA passage is selected as row address, and the selection of SCL passage is selected as column address, the present invention adopts rank addresses decoding to choose a plurality of or a large amount of identical I that has
2The equipment of C bus address reaches the purpose of unique visit.In the present embodiment, SFP optical module quantity is 12, divides with the SDA data line and can be not limited to be divided into 3 groups, can also be divided into 2 to 6 groups of forms and come specific implementation; And this class of SFP I
2The equipment that the C bus address is all identical has 24 or other quantity on a veneer, with 24 SFP, divide with the SDA data line and can be divided into 2 to 12 groups, but here 3,4,6,8 groups be comparatively rational, at this moment corresponding clock grouping is 8,6,4,3 groups; Such equipment of other quantity also can so be analogized, certainly, and I
2The equipment that the C bus address is identical is not limited to the SFP optical module.
Those skilled in the art do not depart from the scope of the present invention and spirit, can have the various deformation scheme to realize the present invention, and appended claim comprises these distortion.
Claims (10)
1, a kind of internal integrate circuit bus access control system, comprise CPU, internal integrate circuit bus and a plurality of equipment, wherein, described internal integrate circuit bus comprises clock cable and data signal line, described CPU and described a plurality of equipment carry out communication by described internal integrate circuit bus, it is characterized in that, also comprise logical device and switch, the identical equipment in inner Integration Bus address is connected by described logical device with clock cable between the CPU, and the break-make by described logical device control clock signal line; The identical equipment in described inner Integration Bus address is connected by described switch with data signal line between the CPU, and the break-make by described switch control data signal wire, CPU can conduct interviews to this equipment when the clock cable of described equipment and data signal line are opened simultaneously.
2, internal integrate circuit bus access control system according to claim 1, it is characterized in that: the identical equipment in described inner Integration Bus address is connected by the three-state driver in the described logical device with clock cable between the CPU, and passes through the break-make of three-state driver control clock signal line.
3, internal integrate circuit bus access control system according to claim 2, it is characterized in that: described switch is an analog switch, the identical equipment in described inner Integration Bus address is connected by described analog switch with data signal line between the CPU, and controls the break-make of each device data signal wire by analog switch.
4, according to claim 2 or 3 described internal integrate circuit bus access control systems, it is characterized in that: also be provided with register in the described logical device, CPU controls described three-state driver or analog switch by this register corresponding bits position is provided with, thus the clock cable between control CPU and each equipment or the break-make of data signal line.
5, internal integrate circuit bus access control system according to claim 4, it is characterized in that: described register is provided with by local bus by CPU.
6, internal integrate circuit bus access control system according to claim 4, it is characterized in that: the identical equipment in described inner Integration Bus address can be divided into different groups arbitrarily, and each equipment in every group adopts same data signal line to be connected with many different clock cables.
7, internal integrate circuit bus access control system according to claim 6 is characterized in that: the identical equipment in described inner Integration Bus address is the SFP optical module.
8, internal integrate circuit bus access control system according to claim 1: for inner Integration Bus address equipment inequality, the different addresses that CPU can directly send by the protocol package hair conduct interviews to each equipment.
9, internal integrate circuit bus access control system according to claim 8,: described inner Integration Bus address each equipment inequality has identical clock cable and data signal line passage, this clock cable drives to form by logical device with the clock cable of CPU and forever is connected, and is connected but this data signal line forms gated nature with the data signal line of CPU by analog switch.
10, according to Claim 8 or 9 described internal integrate circuit bus access control systems, it is characterized in that: described inner Integration Bus address equipment inequality is watch-dog, temperature sensor or real-time clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031473180A CN100353350C (en) | 2003-07-06 | 2003-07-06 | Assess controlling system for bus of internal integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031473180A CN100353350C (en) | 2003-07-06 | 2003-07-06 | Assess controlling system for bus of internal integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1567278A CN1567278A (en) | 2005-01-19 |
| CN100353350C true CN100353350C (en) | 2007-12-05 |
Family
ID=34471898
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031473180A Expired - Fee Related CN100353350C (en) | 2003-07-06 | 2003-07-06 | Assess controlling system for bus of internal integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100353350C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101539900B (en) * | 2008-03-18 | 2011-08-24 | 英业达股份有限公司 | Device for solving conflict generated between two I<2>C slave devices with same addressing address |
| CN102684790A (en) * | 2012-05-30 | 2012-09-19 | 曙光信息产业(北京)有限公司 | Optical module control system utilizing FPGA (Field Programmable Gate Array) |
| CN102866967B (en) * | 2012-09-03 | 2015-08-26 | 杭州华三通信技术有限公司 | I 2c device management method and complex programmable logic device (CPLD) |
| CN103475421B (en) * | 2013-08-21 | 2016-08-10 | 成都新易盛通信技术股份有限公司 | A kind of SFF2X10 optical transceiver module |
| CN109361467B (en) * | 2018-12-04 | 2021-07-06 | 青岛海信宽带多媒体技术有限公司 | Optical module |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1221152A (en) * | 1997-11-28 | 1999-06-30 | 日本电气株式会社 | Bus control system |
| US6205504B1 (en) * | 1998-09-30 | 2001-03-20 | International Business Machines Corporation | Externally provided control of an I2C bus |
-
2003
- 2003-07-06 CN CNB031473180A patent/CN100353350C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1221152A (en) * | 1997-11-28 | 1999-06-30 | 日本电气株式会社 | Bus control system |
| US6205504B1 (en) * | 1998-09-30 | 2001-03-20 | International Business Machines Corporation | Externally provided control of an I2C bus |
Non-Patent Citations (2)
| Title |
|---|
| I2C总线数据传输系统的设计及其应用 陈秀玲，周欣，陈黎平.微型电脑应用，第19卷第5期 2003 * |
| 彩色电视接收机中的I2C总线 蔡武德，杨海，蔡加文，杨毅红.电视技术，第5期 2002 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1567278A (en) | 2005-01-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105785958B (en) | Multi-functional data collector, acquisition system and method based on wisdom factory | |
| CN100357926C (en) | A system and method for equipment management | |
| CN108228513B (en) | Intelligent serial port communication device based on FPGA framework | |
| US10996950B2 (en) | Apparatuses and methods involving selective disablement of side effects caused by accessing register sets | |
| CN106933753A (en) | The control method and device of intelligent interface card | |
| CN108255755A (en) | PCIE functional universal communication interface modules based on FPGA | |
| CN103999159A (en) | Memory apparatuses, computer systems and methods for ordering memory responses | |
| CN105243044B (en) | Management system and management method based on serial ports | |
| CN210573745U (en) | CPLD online upgrading device based on multiple same type backplates | |
| CN106959935A (en) | A kind of method that compatible I2C communications communicate with IPMB | |
| CN101149722A (en) | Method for executing CPU access to XFP optical module | |
| CN102866683A (en) | Signal conversion device and automatic testing system | |
| CN103500148A (en) | Device and method for enabling master control card to read type of service line card | |
| CN101082896A (en) | Control method and device between master-salve module | |
| CN109446145A (en) | A kind of channel server master board I2C extended chip, circuit and control method | |
| CN1811480A (en) | Method and apparatus for real-time monitoring level signal | |
| CN100353350C (en) | Assess controlling system for bus of internal integrated circuit | |
| CN1277170C (en) | Pick up device and method for data in plugable optical modular inner memory | |
| CN105373511A (en) | Device and method for simultaneous communication with multiple optical modules | |
| CN2660795Y (en) | Optical fiber Ethernet exchanger and monitor modular for same | |
| CN107239423A (en) | A kind of device based on extension IIC interfaces | |
| CN1435029A (en) | Bridge interface circuit | |
| CN105005233B (en) | Pulse power real-time control system based on Reflective memory network and dsp controller | |
| CN201698420U (en) | Small-sized pluggable optical receiving-sending module control device based on I2C bus | |
| CN213122967U (en) | RS485 signal sharing device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20071205 Termination date: 20100706 |