CN102866683A - Signal conversion device and automatic testing system - Google Patents
Signal conversion device and automatic testing system Download PDFInfo
- Publication number
- CN102866683A CN102866683A CN2012102617789A CN201210261778A CN102866683A CN 102866683 A CN102866683 A CN 102866683A CN 2012102617789 A CN2012102617789 A CN 2012102617789A CN 201210261778 A CN201210261778 A CN 201210261778A CN 102866683 A CN102866683 A CN 102866683A
- Authority
- CN
- China
- Prior art keywords
- module
- control unit
- transistor
- chromacoder
- logic level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Abstract
The invention discloses a signal conversion device, which is used for receiving system control information from an upper computer and converting the system control information into a plurality of TTL (Transistor-Transistor Logic) level signals to be output. The signal conversion device comprises a master control unit, wherein the master control unit is used for receiving the system control information from the upper computer through a USB (Universal Serial Bus) communication protocol and converting the system control information into an I2C (Inter-Integrated Circuit) communication protocol data format; the system control information is transmitted outwards and external return information is received through an I2C bus; and the master control unit is also used for outputting the TTL level signals according to the system control information. The invention also discloses an automatic testing system using the signal conversion device. In such a mode, a drive is not required to be mounted, and the required TTL level signals can be flexibly output; and the signal conversion device and the automatic testing system are suitable for controlling complex conditions.
Description
Technical field
The present invention relates to signal switch technology field, particularly relate to a kind of chromacoder and Auto-Test System.
Background technology
TTL(Transistor-Transistor Logic) circuit is a kind of logical circuit commonly used in the Digital Electronic Technique.The Transistor-Transistor Logic level signal is not high to power requirement when the device interior transmission of computing machine and control thereof, thermal losses is low, being connected with integrated circuit does not need expensive line driver and acceptor circuit, can satisfy the data high-speed transmission of computerized equipment inside, therefore is widely used.
And computing machine does not have the TTL output port, usually needs the USB(Universal Serial Bus of computer, USB (universal serial bus)) port, usb signal is converted to the Transistor-Transistor Logic level signal.
The USB-TTL conversion of prior art is exported the TTL signal by simulating a serial port, and it need to install driving, and its characteristic is identical with serial port.But the Transistor-Transistor Logic level number of signals of this conversion regime output is few, and needs driving is installed, and is difficult to be applied to control complicated situation.
Summary of the invention
The technical matters that the present invention mainly solves provides a kind of chromacoder and Auto-Test System, can export flexibly a plurality of required Transistor-Transistor Logic level signals.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is: a kind of chromacoder is provided, be used for from the control information of host computer receiving system, convert a plurality of Transistor-Transistor Logic level signal outputs to, it comprises: main control unit, main control unit by the usb communication agreement from the control information of host computer receiving system and convert I to
2C communication protocol data form, and pass through I
2The outside transmission system control information of C bus and receive outside back information.Wherein, main control unit is also exported a plurality of Transistor-Transistor Logic level signals according to system control information.
For solving the problems of the technologies described above, another technical solution used in the present invention is: a kind of Auto-Test System is provided, and it comprises: host computer, above-mentioned chromacoder and rear class application circuit.Chromacoder is connected with host computer, is used for from the control information of host computer receiving system, and converts a plurality of Transistor-Transistor Logic level signal outputs to.The rear class application circuit comprises signal processing circuit and to be measured, signal processing circuit is connected with chromacoder, exports required TTL control signal to be measured is tested automatically after chromacoder receives the Transistor-Transistor Logic level signal and carries out the signal processing.
Compared with prior art, the invention provides and a kind ofly can be effectively obtain the chromacoder of the Transistor-Transistor Logic level signal of demand by computer control, by the usb communication agreement from the control information of host computer receiving system and convert I to
2C communication protocol data form, and export a plurality of Transistor-Transistor Logic level signals according to system control information, it does not need to install driving, can directly use, also very flexible with the collocation of peripheral circuit, send out control command corresponding by host computer and can obtain the TTL signal level of any needs, thereby can be applicable to control complicated situation.And, when chromacoder of the present invention is applied to Auto-Test System, can realize robotization control, reduce cost.
Description of drawings
Fig. 1 is the structural representation of the chromacoder of first embodiment of the invention;
Fig. 2 is the structural representation of the main control unit of chromacoder shown in Figure 1;
Fig. 3 is the schematic diagram of a kind of embodiment of high speed IO PIC module of the present invention;
Fig. 4 is I among the present invention
2The schematic diagram of a kind of embodiment of C bus buffer module;
Fig. 5 is the schematic diagram of a kind of embodiment of channel switch module among the present invention;
Fig. 6 is the schematic diagram of a kind of embodiment of digital DIP module among the present invention;
Fig. 7 is the schematic diagram of a kind of embodiment of expansion output module among the present invention;
Fig. 8 is the schematic diagram of a kind of embodiment of storer among the present invention;
Fig. 9 is the structural representation from the control unit of chromacoder shown in Figure 1;
Figure 10 is the schematic flow sheet that chromacoder of the present invention is realized the signal conversion;
Figure 11 is the module diagram of the main control unit of chromacoder shown in Figure 1 when carrying out initialization;
Figure 12 is the module diagram of the main control unit of chromacoder shown in Figure 1 when setting the address;
Module diagram when Figure 13 is the main control unit output Transistor-Transistor Logic level signal of chromacoder shown in Figure 1;
Figure 14 be chromacoder shown in Figure 1 set the address from the control unit time module diagram;
Figure 15 be chromacoder shown in Figure 1 from control unit output Transistor-Transistor Logic level signal the time module diagram;
Module diagram when Figure 16 is resetting from the control unit of chromacoder shown in Figure 1;
Figure 17 is the structural representation of a kind of embodiment of Auto-Test System of the present invention;
Figure 18 is the structural representation of the another kind of embodiment of Auto-Test System of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiments.Based on the embodiment among the present invention, those of ordinary skills all belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
See also Fig. 1, Fig. 1 is the structural representation of the chromacoder of first embodiment of the invention.
I
2C(Inter-Integrated Circuit) bus is a kind of twin wire universal serial bus, be used for connecting controller and peripherals thereof, it is a kind of bus standard that extensively adopt in microelectronics Control on Communication field, it is a kind of special shape of synchronous communication, has interface line few, control is simple, the little and traffic rate advantages of higher of device package form.
In the present embodiment, chromacoder 10 comprises that also at least one is from control unit 200.Usb signal is by the I of main control unit 100
2Each chip that the C bus is controlled main control unit 100 sends the Transistor-Transistor Logic level signal that needs, and can also share to from the I of control unit 200 by main control unit 100
2The C bus allows sends the Transistor-Transistor Logic level signal from each chip of control unit 200.Pass through I from control unit 200 with main control unit 100
2The C bus is connected, and passes through I
2C communication protocol is from main control unit 100 receiving system control informations, and converts a plurality of Transistor-Transistor Logic level signals to respectively from from 200 outputs of control unit.
When the Transistor-Transistor Logic level signal of needs is less, can stop main control unit 100 with from control communicating by letter between the unit 200, only utilize a plurality of Transistor-Transistor Logic level signals of main control unit 100 outputs.When Transistor-Transistor Logic level number of signals that main control unit 100 can't be satisfied the demand, main control unit 100 can be controlled a plurality of from a plurality of Transistor-Transistor Logic level signals of control unit 200 outputs, satisfies actual demand.For example, be 7 from control unit 200, all pass through I from control unit 200 with main control unit 100
2The C bus parallel connection connects.
See also Fig. 2 to Fig. 8, Fig. 2 is the structural representation of the main control unit of chromacoder shown in Figure 1.Show for clear, also show among the figure from control unit 200.
As shown in Figure 2, main control unit 100 comprises High Speed I/O PIC module 101, I
2C bus buffer module 102, first passage switch module 103, the first digital DIP module 104, the first expansion output module 105 and the second output expansion module 106.
High Speed I/O PIC(Input/Output, input and output) (Peripheral Interface Controller, adopt single-chip data line and the order line time-sharing multiplex of CISC structure, being so-called variational OR structure) module 101 is used for receiving the usb signal of host computer transmission, and usb signal is converted to I
2The C format order, and via I
2C internal bus transmission I
2The C format order.In the present embodiment, main control unit 100 also comprises USB impact damper 107, and USB impact damper 107 is connected with host computer, is used for receiving the usb signal of host computer transmission, and usb signal is sent to High Speed I/O PIC module 101.Access USB impact damper 107 can guarantee the usb signal stable transfer.
I
2C bus buffer module 102 is via I
2The C internal bus receives I
2The C format order, and via I
2The C external bus outwards sends I
2The C format order arrives from control unit 200.I
2C bus buffer module 102 is via I
2The C external bus receives from the I of control unit 200 passbacks
2The C format information, and via I
2The C internal bus is sent back to High Speed I/O PIC module 101.I
2C bus buffer module 102 can be at I
2C external bus and I
2Play buffer action between the C internal bus, to stablize I
2The stable transfer of C format order.
First passage switch module 103 for example is the multichannel dispense switch, and it comprises input channel and a plurality of output channel, and input channel and High Speed I/O PIC module 101 are passed through I
2The C internal bus is connected, and sets I according to pattern
2The C format order is sent to respectively a plurality of output channels.
The first digital DIP(Dual In-line Package also is the dual-in-line package technology) module 104 passes through I with High Speed I/O PIC module 101
2The C internal bus is connected, be used for to set main control unit 100 or from the address of control unit 200, set resetting, enable, forbid and the duty such as write-protect of each functional module.Particularly, in the embodiment of the present invention, the first digital DIP module 104 is used for according to I
2The C format order is set first passage switch module 103, the first expansion output module 105 and the duty of the second expansion output module 106 and the address of main control unit 100.Because at I
2In the C bus rule, main control unit 100 and need to set different addresses from control unit 200 clashes preventing.So the first digital DIP module 104 needs to set separately the address of main control unit 100,, the address of main control unit 100 can be made as 0.0.0 here.
The 1st output channel CH1(channel of the first expansion output module 105 and first passage switch module 103, passage) be connected, be used for according to I
2The C format order is exported one group of multidigit Transistor-Transistor Logic level signal.In the present embodiment, one group of 16 Transistor-Transistor Logic level signal of the first expansion output module 105 outputs.
The second expansion output module 106 is connected with the 1st output channel CH1 of first passage switch module 103, is used for according to I
2The C format order is exported other one group of multidigit Transistor-Transistor Logic level signal.In the present embodiment, one group of 16 Transistor-Transistor Logic level signal of the second expansion output module 106 outputs.
By the first expansion output module 105 and the second expansion output module 106, main control unit 100 can be exported 32 Transistor-Transistor Logic level signals.
In the present embodiment, the first digital DIP module 104 also is used for setting the duty of described the 3rd expansion output module 108, storer 110 and the 4th expansion output module 111.High Speed I/O PIC module 101 also is used for transmission the first digital DIP module 104 and the write protect signal of storer 110, ready signal and the reset signal of main control unit 10.
Because all the other output channels of first passage switch module 103 are not used, also not shown among Fig. 2.
In embodiments of the present invention, the High Speed I/O PIC module 101 of the main control unit 100 of chromacoder 10 is selected from PIC18F1XK50/PIC18LF1XK50 chip as shown in Figure 3, and 18,19 pins of this chip are used for receiving usb signal.
I
2C bus buffer module 102 is selected from IES5502 chip as shown in Figure 4, and its pin 5 and pin 6 meet I
2The C internal bus, pin 2 and pin 7 meet I
2The C external bus.
First passage switch module 103 is selected from IES5507 chip as shown in Figure 5, and its pin 1, pin 2 and pin 13 are used for accepting the address setting of the first digital DIP module 104.Pin 14 and pin 15 meet I
2The C internal bus.
The first digital DIP module 104 is selected from SW00347 chip as shown in Figure 6, and its pin 1 is connected with pin and is connected I
2The C internal bus, this chip pin 9, pin 10 and pin 11 are 0.0.0 by pin 9, pin 10 and pin 11 being connect pull down resistor to the address that the mode on ground is set main control unit 100 in order to set the address of main control unit 100.
The first expansion output module 105, the second output expansion module 106, the 3rd expansion output module 108 and the 4th expansion output module 111 all are selected from MCP23017 chip as shown in Figure 7, and the pin 15 of this chip, pin 16, pin 17 are in order to set the address.In the present embodiment, pin 15, pin 16, pin 17 are set the first expansion output module 105 addresses as 1.0.0, the second output expansion module 106 addresses as 0.1.0 to connect pull-up resistor to high level or to connect pull down resistor to low level mode, and the 3rd expansion output module 108 addresses are 1.1.0.
See also Fig. 9, Fig. 9 is the structural representation from the control unit of chromacoder shown in Figure 1.Show for clear, also show main control unit 100 among the figure.
Comprise second channel switch module 201, the second digital DIP module 202, the 5th expansion output module 203 and the 6th expansion output module 204 from control unit 200.
Second channel switch module 201 comprises input channel and a plurality of output channel.The I of main control unit 100 among input channel and Fig. 2
2C bus buffer module 102 is passed through I
2The C external bus connects, and sets I according to pattern
2The C format order is sent to the 5th output channel CH5.Because 201 of second channel switch modules have used one in a plurality of output channels, therefore all the other output channels are all not shown.
The second digital DIP module 202 and I
2C bus buffer module 102 is passed through I
2The C external bus is connected, and is used for according to I
2The C format order is set the initial address of second channel switch module 201.Here, initial address can be set as 1.1.1, and initial address can be reset by main control unit 100.
The 5th expansion output module 203 is connected with the 5th output channel CH5 of second channel switch module 201, is used for according to I
2The C format order is exported one group of 16 Transistor-Transistor Logic level signal.
The 6th expansion output module 204 is connected with the 5th output channel CH5 of second channel switch module 201, is used for according to I
2The C format order is exported one group of 16 Transistor-Transistor Logic level signal.
Also comprise the 7th expansion output module 205 from control unit 200.The 7th expansion output module 205 is connected with the 5th output channel CH5 of second switch channel module 201, is used for according to I
216 Transistor-Transistor Logic level signals of C format order output.The address that 8 bit representation main control units 100 wherein, are arranged.In the present embodiment, also comprise the 2nd LED nixie display 206 and DB9 output port 207 from control unit 200.The 2nd LED nixie display 206 is connected with the 7th expansion output module 205, be used for to receive representative that the 7th expansion output module 205 exports from 8 Transistor-Transistor Logic level signals of the address of control unit 200, then corresponding LED is lit, to show from the address of control unit 200.DB9 output port 207 is connected with the 7th expansion output module 205, is used for receiving all the other 8 Transistor-Transistor Logic level signals that the 7th expansion output module 205 is exported.The 2nd LED nixie display 206 can be selected 7 segment numeral LED pipe.
Also comprise 8-1 data selector 208 and 3-8 code translator 209 from control unit 200.8-1 data selector 208 is connected with the second digital DIP module 202, is used for receiving 8 Transistor-Transistor Logic level signals that the 4th expansion output module 111 is exported, and exports selected Transistor-Transistor Logic level signal.The second digital DIP module 202 is according to selected Transistor-Transistor Logic level signal output decoded signal.3-8 code translator 209 is connected with 8-1 data selector 208 and the second digital DIP module 202, be used for receiving Transistor-Transistor Logic level signal and the decoded signal that 8-1 data selector 208 is exported, after the second digital DIP module 202 activates second channel switch module 201, to main control unit 100 passback I
2The C format information is with the state of expression from control unit 200.In the present embodiment, I
2The C format information is octonary signal.
In the present embodiment, the second digital DIP module 202 also is used for setting the duty of the 7th expansion output module 205 and the initial address of 8-1 data selector 208.
No matter the main control unit 100 that present embodiment provides is to export separately the Transistor-Transistor Logic level signal, or with exporting together more Transistor-Transistor Logic level signal from control unit 200, all do not need to install and drive, can directly use, also very flexible with the collocation of peripheral circuit, send out control command corresponding by host computer and can obtain the TTL signal level of any needs, thereby can be applicable to control complicated situation.
Concrete, second channel switch module 201 is selected from IES5507 chip as shown in Figure 5, and its pin 1, pin 2 and pin 13 are used for accepting the address setting of the second digital DIP module 202.Pin 14 and pin 15 meet I
2The C internal bus.In the present embodiment, the address of second channel switch module 201 is set to 1.1.1, and this address can be reset by main control unit 100 as required.
The second digital DIP module 202 is selected from SW00347 chip as shown in Figure 6, and its pin 1 is connected with pin and is connected I
2The C internal bus, this chip pin 9, pin 10 and pin 11 are in order to set from the address of control unit 200.Be different from the address of main control unit 100 from the address setting of control unit 200, and when being a plurality of from control unit 200, a plurality of addresses from control unit 200 are different.
The 5th expansion output module 203, the 6th expansion output module 204 and the 7th expansion output module 205 all are selected from MCP23017 chip as shown in Figure 7, and the pin 15 of this chip, pin 16, pin 17 are in order to set the address.In the present embodiment, pin 15, pin 16, pin 17 are set the first expansion output module 105 addresses as 1.0.0, the second output expansion module 106 addresses as 0.1.0 to connect pull-up resistor to high level or to connect pull down resistor to low level mode, and the 3rd expansion output module 108 addresses are 1.1.0.
8-1 data selector 208 is selected from 74151 chips, and the pin 11 of this chip, pin 12 and pin 13 are in order to accept the address setting of the second digital DIP module 202.Pin 1, pin 2, pin 3, pin 4, pin 5, pin 6, pin 7 and pin 9 receive the 4th expansion output module 111(and see also shown in Figure 2) 8 Transistor-Transistor Logic level signals exporting, 14 selected Transistor-Transistor Logic level signals of output of pin, be used for the signal activation of sending according to main control unit 100 or close from control unit 200, the second digital DIP modules 202 and open or close second channel switch module 201 according to selected Transistor-Transistor Logic level signal output decoded signal and control.In the present embodiment, this decoded signal is the triad signal.
3-8 code translator 209 is selected from 74138 chips, and the pin 6 of this chip receives 8-1 data selector 208 selected Transistor-Transistor Logic level signals, and pin 1, pin 2 and pin 3 receive the decoded signal of the second digital DIP module 202 outputs, and decoding output I
2The C format information, and to main control unit 100 passback I
2C form status information is with the state of expression from control unit 200.Concrete, 3-8 code translator 209 is at first to the second digital DIP module 202 passback I
2C form status information, the second digital DIP module 202 is passed through I again
2C bus buffer module 102 is to main control unit 100 passback I
2C form status information.In the present embodiment, I
2C form status information is eight signals.
See also Figure 10, Figure 10 is the schematic flow sheet that chromacoder of the present invention is realized the signal conversion.For example describes, its flow process that realizes that signal is changed may further comprise the steps the flow process that chromacoder is realized the signal conversion based on the chromacoder 10 of the first embodiment:
Step S101: 101 pairs of USB impact dampers of High Speed I/O PIC module 107 carry out initialization.
See also Figure 11, Figure 11 is the module diagram of the main control unit of chromacoder shown in Figure 1 when carrying out initialization.Before receiving usb signal, 101 pairs of USB impact dampers of High Speed I/O PIC module 107 carry out initialization, to remove the before this data of storage of USB impact damper 107.After initialization was complete, main control unit 100 was in standby condition.And High Speed I/O PIC module 101 can outwards be sent ready signal.Ready signal can be exported separately by High Speed I/O PIC module 101, also can pass through I
2C bus buffer module 102 is loaded into I
2The output of C bus.
Step S102: High Speed I/O PIC module 101 receives the system control information of host computer, and sends I
2The C format order, the first digital DIP module 104 is according to I
2The C format order is set the address of main control unit 100.
See also Figure 12, Figure 12 is the module diagram of the main control unit of chromacoder shown in Figure 1 when setting the address.High Speed I/O PIC module 101 is sent I
2The C format order, the first digital DIP module 104 is according to I
2The C format order is set the address of main control unit 100.Have the address setting pin on the first digital DIP module 104, this address namely represents the address of main control unit 100, for example, is set as 0.0.0.And the first digital DIP module 104 is also according to I
2The C format order is set the address of storer 110 and first passage switch module 103.I
2The C format order is also passed through I
2C bus buffer module 102 is loaded into I
2C bus output, when connecting from control unit 200 at main control unit 100, from control unit 200 according to I
2The C format order is set the address.
Step S103: the first expansion output module 105 and the second expansion output module 106 are respectively according to I
2The C format order is exported one group of 16 Transistor-Transistor Logic level signal.
See also Figure 13, the module diagram when Figure 13 is the main control unit output Transistor-Transistor Logic level signal of chromacoder shown in Figure 1.The first switch channel module 103 is with I
2The C format order is sent to respectively the first expansion output module 105 by an output channel and the second expansion output module 106, the first is expanded output modules 105 according to I
2The C format order is exported one group of 16 Transistor-Transistor Logic level signal, and the second expansion output module 106 is according to I
2The C format order is exported 16 Transistor-Transistor Logic level signals of another group.Simultaneously, the first switch channel module 103 also passes through other passages with I
2The C format order is sent to storer 110, the data that write with storage.
More when required signal, when needing utilization to export the Transistor-Transistor Logic level signal from control unit 200, the mode of main control unit 100 controls 200 realization signal conversions from the control unit is further comprising the steps of:
Step S104: during a plurality of Transistor-Transistor Logic level signal of main control unit 100 outputs, activate second channel switch module 201 and detection from the state of control unit 200.
Please consult Figure 13, the first digital DIP module 104 is also set the address of the 4th expansion output module 111 after High Speed I/O PIC module 101 is carried out initialization again.The first switch channel module 103 is with I
2The C format order sends to the 4th expansion output module 111.When the first expansion output module 105 and the second expansion output module 106 output Transistor-Transistor Logic level signal, the 4th expansion output module 111 is also exported 16 Transistor-Transistor Logic level signals, wherein 8 Transistor-Transistor Logic level signal activations are from controlling the second channel switch module 201 of unit 200, and other 8 Transistor-Transistor Logic level input are from the state of control unit 200.
Step S105: activate second channel switch module 201 and set the address of second channel switch module 201.
See also Figure 14, Figure 14 be chromacoder shown in Figure 1 set the address from the control unit time module diagram.Second channel switch module 201 is started working by 8 Transistor-Transistor Logic level signal activations of the 4th expansion output module 111 outputs.And receive 8 Transistor-Transistor Logic level signals that are used for activating second channel switch module 201 from the 8-1 data selector 208 of control unit 200, and selection output one Transistor-Transistor Logic level signal, the second digital DIP module 202 is opened second channel switch module 201, the second digital DIP modules 202 according to selected Transistor-Transistor Logic level signal controlling and is passed through I
2The C external bus receives I
2The C format order, and according to I
2The C format order is set from the address of control unit 200, second channel switch module 201,8-1 data selector 208 and 3-8 code translator 209.The address of second channel switch module 201 and 8-1 data selector 208 all is made as 1.1.1.
Step S 106: from 32 Transistor-Transistor Logic level signals of control unit 200 outputs, and to main control unit 100 passback I
2C form status information.
See also Figure 15, Figure 15 be chromacoder shown in Figure 1 from control unit output Transistor-Transistor Logic level signal the time module diagram.Second channel switch module 201 is with I
2The C format order is sent to the 5th expansion output module 203 and the 6th expansion output module 204, the five expansion output modules 203 and the 6th expansion output module 204 according to I
2The C format order is exported respectively one group of 16 Transistor-Transistor Logic level signal.And 8 Transistor-Transistor Logic level signals that 8-1 data selector 208 receives for detection of state, and selection output one Transistor-Transistor Logic level signal, the second digital DIP module 202 is according to selected Transistor-Transistor Logic level signal output decoded signal, 3-8 code translator 209 receives this decoded signal and Transistor-Transistor Logic level signal, after decoding, to main control unit 100 passback I
2C form status information, expression is from the state of control unit 200.Concrete, 3-8 code translator 209 is at first to the second digital DIP module 202 passback I
2C form status information, the second digital DIP module 202 is passed through I again
2C bus buffer module returns I to main control unit
2C form status information.In the present embodiment, decoded signal is 3 binary signals, I
2The C format information is eight signals.
Step S107: behind control unit 200 output Transistor-Transistor Logic level signals, to resetting from control unit 200.
See also Figure 16, the module diagram when Figure 16 is resetting from the control unit of chromacoder shown in Figure 1.The second digital DIP module 202 is passed through I
2The C external bus receives I
2The C format order is according to I
2The C format order resets to second channel switch module 201, the 5th expansion output module 203 and the 6th expansion output module 204, the second channel switch module 201 of namely resetting, the 5th expansion output module 203 and the 6th expansion output module 204.
Should be understood that preamble describes for example from control unit 200 to control one, when the chromacoder 10 of embodiment of the present invention comprise a plurality of parallel connections from control unit 200 time, to each from the control mode of controlling unit 200 as mentioned before, do not repeat them here.
Specifically, compared with prior art, the chromacoder of embodiment of the present invention has 32 TTL master ports from the control unit as example take 7 of parallel connections, reaches 7 groups 32 from port, can obtain by the control of computing machine the TTL signal level of any needs.
In sum, embodiment of the present invention provides a kind of device that can effectively obtain the Transistor-Transistor Logic level signal of demand by computer control, wherein, no matter main control unit 100 is to export separately the Transistor-Transistor Logic level signal, or with exporting together more Transistor-Transistor Logic level signal from control unit 200, all do not need to install and drive, can directly use, also very flexible with the collocation of peripheral circuit, send out control command corresponding by host computer and can obtain the TTL signal level of any needs, thereby can be applicable to control complicated situation.
The chromacoder of embodiment of the present invention may be used in the various Auto-Test Systems, the Transistor-Transistor Logic level signal that the chromacoder of embodiment of the present invention provides can further be controlled the action that various devices are realized robotization by drives or the amplification of back segment, to realize automatic control, reduce cost.
Brought forward is described, the present invention further provides a kind of Auto-Test System, and it comprises host computer, the chromacoder 10 of rear class application circuit and the first embodiment.In great majority were used, host computer was computing machine.Chromacoder 10 is connected with host computer, is used for from the control information of host computer receiving system, and converts a plurality of Transistor-Transistor Logic level signal outputs to.The rear class application circuit comprises signal processing circuit and to be measured, signal processing circuit is connected with chromacoder 10, exports required TTL control signal to be measured is tested automatically after chromacoder 10 receives the Transistor-Transistor Logic level signal and carries out the signal processing.
For example, see also Figure 17, Figure 17 is the structural representation of a kind of embodiment of Auto-Test System of the present invention.In the present embodiment, automatic control system is that antenna beats test macro automatically.Chromacoder 10 is connected with host computer 301.
Signal processing circuit comprises driving circuit 302, relay 303, programmable logic device (PLD) 304, solenoid valve 305 and the rotary cylinder 306 that connects successively.Driving circuit 302 is connected with chromacoder 10, receives the Transistor-Transistor Logic level signal from chromacoder 10.
In the present embodiment, to be measured is antenna 307.Host computer 301 sends system control information to chromacoder 10, the required Transistor-Transistor Logic level signal of chromacoder 10 outputs.Because the magnitude of voltage of Transistor-Transistor Logic level signal is lower, therefore driving circuit 302 arrives higher magnitude of voltage with the Transistor-Transistor Logic level signal driver, for example 24V exports required control signal.This control signal is pilot relay 303 as required, after relay 303 conductings, and the bring into operation program of inner pre-edit of programmable logic device (PLD) 304, solenoid valve 305 drives rotary cylinder 306 actions under programmed control, rotary cylinder 306 and then beat antenna 307.In the present embodiment, relay 303 is the 24V DC relay, and Programmadle logic device 304 is PLC(Programmable Logic Controller), rotary cylinder 306 is the gas rotary cylinder.
Please consult Figure 18, Figure 18 is the structural representation of the another kind of embodiment of Auto-Test System of the present invention again.In the present embodiment, automatic control system is the radio-frequency (RF) switch automatic control system.Chromacoder 10 is connected with host computer 401.
Signal processing circuit comprises driving circuit 402, radio-frequency (RF) switch 403 and tester 404.Has multiport for to be measured 305.Radio-frequency (RF) switch 403 also has multiport.Wherein, host computer 401, chromacoder 10, driving circuit 402 are connected with radio-frequency (RF) switch successively and are connected.Radio-frequency (RF) switch 403 and to be measured 405 the corresponding connection of port, and radio-frequency (RF) switch 403 is gone back connecting test instrument 404.
Computing machine sends system control information to chromacoder 10, the required Transistor-Transistor Logic level signal of chromacoder 10 outputs.The driven circuit 402 of Transistor-Transistor Logic level signal is driven into 24V direct voltage output control signal, and then control radio-frequency (RF) switch 403.Radio-frequency (RF) switch 403 is further controlled the port of tester 404 and to be measured 405 corresponding port conducting, to carry out the relevant parameter test.In this manner, a plurality of ports of to be measured 405 can require test according to different test indexs by tested instrument 404, obtain to be measured 405 multiple parameters.In the present embodiment, tester 404 is network analyzer.
By chromacoder 10 output Transistor-Transistor Logic level signals, automatically control radio-frequency (RF) switch and carry out corresponding test, can effectively reduce tester's running time, reduce cost.
By the way, the chromacoder of embodiment of the present invention by the usb communication agreement from the control information of host computer receiving system and convert I to
2C communication protocol data form, and export a plurality of Transistor-Transistor Logic level signals according to system control information, and driving need not be installed, be applicable to control complicated situation.When chromacoder of the present invention is applied to Auto-Test System, can realize robotization control, reduce cost.
The above only is embodiments of the present invention; be not so limit claim of the present invention; every equivalent structure or equivalent flow process conversion that utilizes instructions of the present invention and accompanying drawing content to do; or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present invention.
Claims (20)
1. a chromacoder is used for from the control information of host computer receiving system, converts a plurality of Transistor-Transistor Logic level signal outputs to, it is characterized in that, described chromacoder comprises:
Main control unit, described main control unit receives described system control information and converts I to from described host computer by the usb communication agreement
2C communication protocol data form, and pass through I
2The C bus is outwards transmitted described system control information and is received outside back information;
Wherein, main control unit is also exported a plurality of Transistor-Transistor Logic level signals according to described system control information.
2. chromacoder according to claim 1 is characterized in that, described chromacoder also comprise at least one from the control unit, described from the control unit pass through I
2C communication protocol receives described system control information from described main control unit, and convert to a plurality of Transistor-Transistor Logic level signals respectively from described from the control unit export.
3. chromacoder according to claim 2 is characterized in that, described main control unit comprises:
High Speed I/O PIC module is used for receiving the usb signal that described host computer transmits, and described usb signal is converted to I
2The C format order, and via I
2The C internal bus transmits described I
2The C format order;
I
2C bus buffer module, described I
2C bus buffer module is via I
2The C internal bus receives I
2The C format order, and via I
2The C external bus outwards sends I
2The C format order is to described from the control unit; Described I
2C bus buffer module is via I
2The C external bus receives described I from the passback of control unit
2The C format information, and via I
2The C internal bus is sent back to described High Speed I/O PIC module;
The first passage switch module, it comprises input channel and a plurality of output channel, described input channel and described High Speed I/O PIC module are passed through I
2The C internal bus is connected, and sets I according to pattern
2The C format order is sent to respectively a plurality of described output channels;
The first digital DIP module is passed through described I with described High Speed I/O PIC module
2The C internal bus is connected, and is used for according to described I
2The C format order is set described first passage switch module, the first expansion output module and the duty of the second expansion output module and the address of described main control unit;
The first expansion output module is connected with the 1st output channel of described first passage switch module, is used for according to described I
2The C format order is exported one group of 16 Transistor-Transistor Logic level signal;
The second expansion output module is connected with the 1st output channel of described first passage switch module, is used for according to described I
2The C format order is exported other one group of 16 Transistor-Transistor Logic level signal.
4. chromacoder according to claim 3 is characterized in that, described main control unit also comprises the 3rd expansion output module, is connected with the 1st output channel of described first passage switch module, is used for according to described I
216 Transistor-Transistor Logic level signals of C format order output.
5. chromacoder according to claim 4, it is characterized in that, described main control unit also comprises a LED nixie display, be connected with described the 3rd expansion output module, be used for receiving 8 Transistor-Transistor Logic level signals that described the 3rd expansion output module is exported, to show the address of described main control unit.
6. chromacoder according to claim 4 is characterized in that, the described first digital DIP module also is used for setting the duty of described the 3rd expansion output module.
7. chromacoder according to claim 3, it is characterized in that, described main control unit comprises storer, is connected with the 2nd output channel of described first passage switch module, and by the described first digital DIP module setting duty, described storer and described I
2The C internal bus links to each other, and is used for storing described I
2The data that the C internal bus writes.
8. chromacoder according to claim 7 is characterized in that, described main control unit also comprises the 4th expansion output module, is connected with the 3rd output channel of described first passage switch module, is used for according to described I
216 Transistor-Transistor Logic level signals of C format order output, and when communicating from the control unit, activates described from controlling the unit and detecting described from controlling the state of unit with described at described main control unit.
9. chromacoder according to claim 8 is characterized in that, the described first digital DIP module also is used for setting the duty of described storer and described the 4th expansion output module.
10. chromacoder according to claim 3, it is characterized in that, described main control unit also comprises the USB impact damper, is connected with described host computer, be used for receiving the usb signal of described host computer transmission, and described usb signal is sent to described High Speed I/O PIC module.
11. to 10 each described chromacoders, it is characterized in that according to claim 2, described from the control unit comprise:
The second channel switch module, it comprises input channel and a plurality of output channel, described input channel and described I
2C bus buffer module connects by described I2C external bus, and sets I according to pattern
2The C format order is sent to the 5th output channel;
The second digital DIP module is with described I
2C bus buffer module is by described I
2The C external bus is connected, and is used for according to described I
2The C format order is set the initial address of described second channel switch module;
The 5th expansion output module is connected with the 5th output channel of described second channel switch module, is used for according to described I
2The C format order is exported one group of 16 Transistor-Transistor Logic level signal;
The 6th expansion output module is connected with the 5th output channel of described second channel switch module, is used for according to described I
2The C format order is exported other one group of 16 Transistor-Transistor Logic level signal.
12. chromacoder according to claim 11 is characterized in that, described the 7th expansion output module that also comprises from the control unit is connected with the 5th output channel of described second channel switch module, is used for according to described I
216 Transistor-Transistor Logic level signals of C format order output.
13. chromacoder according to claim 12, it is characterized in that, described from the control unit also comprise the 2nd LED nixie display, be connected with described the 7th expansion output module, be used for receiving 8 Transistor-Transistor Logic level signals that described the 7th expansion output module is exported, to show described address from the control unit.
14. chromacoder according to claim 13, it is characterized in that, describedly also comprise the DB9 output port from the control unit, be connected with described the 7th expansion output module, be used for receiving all the other 8 Transistor-Transistor Logic level signals that described the 7th expansion output module is exported.
15. chromacoder according to claim 12 is characterized in that, the described second digital DIP module also is used for setting the duty of described the 7th expansion output module.
16. chromacoder according to claim 11 is characterized in that, described from the control unit also comprise:
The 8-1 data selector, be connected with the described second digital DIP module, be used for receiving 8 Transistor-Transistor Logic level signals that described the 4th expansion output module is exported, and it is described from control unit activating or close to control to export selected Transistor-Transistor Logic level signal, and the described second digital DIP module is according to selected Transistor-Transistor Logic level signal output decoded signal and control the unlatching of described second channel switch module or close;
The 3-8 code translator, be connected with described 8-1 data selector and the described second digital DIP module, be used for receiving Transistor-Transistor Logic level signal that described 8-1 data selector exports and the decoded signal of the described second digital DIP module output, and to described main control unit passback I
2C form status information, to represent described state from the control unit, wherein, described I
2The C format information is eight signals.
17. chromacoder according to claim 16 is characterized in that, the described second digital DIP module also is used for setting the initial address of described 8-1 data selector.
18. an Auto-Test System is characterized in that, comprising:
Host computer;
According to claim 1, to 17 each described chromacoders, described chromacoder is connected with described host computer, is used for from the control information of described host computer receiving system, and converts a plurality of Transistor-Transistor Logic level signal outputs to;
The rear class application circuit, it comprises signal processing circuit and to be measured, described signal processing circuit is connected with described chromacoder, exports required control signal so that described to be measured is tested automatically after described chromacoder receives described Transistor-Transistor Logic level signal and carries out the signal processing.
19. Auto-Test System according to claim 18, it is characterized in that, described Auto-Test System is that antenna beats test macro automatically, described signal processing circuit comprises driving circuit, relay, programmable logic device (PLD), solenoid valve and rotary cylinder, described to be measured is antenna, wherein, described host computer, described chromacoder, described driving circuit, described relay, described programmable logic device (PLD), described solenoid valve and described rotary cylinder connect successively, and described rotary cylinder is used for beaing described antenna.
20. Auto-Test System according to claim 18, it is characterized in that, described Auto-Test System is the radio-frequency (RF) switch automatic control system, described signal processing circuit comprises driving circuit, radio-frequency (RF) switch and tester, described to be measured has multiport, wherein, described host computer, described chromacoder, described driving circuit, described radio-frequency (RF) switch and described tester connect successively, described radio-frequency (RF) switch is controlled with the port of described tester and described to be measured corresponding port conducting, to carry out parameter testing by described control signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210261778.9A CN102866683B (en) | 2012-07-26 | 2012-07-26 | Signal conversion device and automatic testing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210261778.9A CN102866683B (en) | 2012-07-26 | 2012-07-26 | Signal conversion device and automatic testing system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102866683A true CN102866683A (en) | 2013-01-09 |
| CN102866683B CN102866683B (en) | 2014-12-17 |
Family
ID=47445606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210261778.9A Active CN102866683B (en) | 2012-07-26 | 2012-07-26 | Signal conversion device and automatic testing system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102866683B (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103678066A (en) * | 2013-12-18 | 2014-03-26 | 北京航天测控技术有限公司 | Method and device for testing test signal set |
| CN104460375A (en) * | 2014-11-26 | 2015-03-25 | 北京无线电测量研究所 | Multi-signal generation device and method used for combined grade product debugging |
| CN104615039A (en) * | 2014-09-22 | 2015-05-13 | 中国电子科技集团公司第四十一研究所 | USB interface control expandable multi-channel radio frequency switch device |
| CN105739435A (en) * | 2016-05-10 | 2016-07-06 | 苏州新代数控设备有限公司 | Numerical control device |
| CN108362989A (en) * | 2018-02-28 | 2018-08-03 | 环胜电子(深圳)有限公司 | Voltage-stablizer tests system |
| CN108494889A (en) * | 2018-02-07 | 2018-09-04 | 广州视源电子科技股份有限公司 | Telecommunication circuit based on I2C buses and adjustment method |
| CN109995397A (en) * | 2018-12-19 | 2019-07-09 | 安徽华东光电技术研究所有限公司 | 64 road Ka wave band array switch |
| CN114326370A (en) * | 2021-12-31 | 2022-04-12 | 上海节卡机器人科技有限公司 | Extended output circuit system and control method |
| CN114355796A (en) * | 2021-11-22 | 2022-04-15 | 杭州程天科技发展有限公司 | CAN communication interface extension method and extension circuit |
| CN114326370B (en) * | 2021-12-31 | 2024-04-30 | 节卡机器人股份有限公司 | Extended output circuit system and control method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101344874A (en) * | 2007-07-11 | 2009-01-14 | 深圳创维－Rgb电子有限公司 | Method and device for controlling I2C device |
| CN201919055U (en) * | 2010-12-28 | 2011-08-03 | 惠州Tcl移动通信有限公司 | Mobile terminal test box based on inter-integrated circuit (I2C) bus |
-
2012
- 2012-07-26 CN CN201210261778.9A patent/CN102866683B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101344874A (en) * | 2007-07-11 | 2009-01-14 | 深圳创维－Rgb电子有限公司 | Method and device for controlling I2C device |
| CN201919055U (en) * | 2010-12-28 | 2011-08-03 | 惠州Tcl移动通信有限公司 | Mobile terminal test box based on inter-integrated circuit (I2C) bus |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103678066A (en) * | 2013-12-18 | 2014-03-26 | 北京航天测控技术有限公司 | Method and device for testing test signal set |
| CN104615039A (en) * | 2014-09-22 | 2015-05-13 | 中国电子科技集团公司第四十一研究所 | USB interface control expandable multi-channel radio frequency switch device |
| CN104460375A (en) * | 2014-11-26 | 2015-03-25 | 北京无线电测量研究所 | Multi-signal generation device and method used for combined grade product debugging |
| CN104460375B (en) * | 2014-11-26 | 2017-02-22 | 北京无线电测量研究所 | Multi-signal generation device and method used for combined grade product debugging |
| CN105739435A (en) * | 2016-05-10 | 2016-07-06 | 苏州新代数控设备有限公司 | Numerical control device |
| CN105739435B (en) * | 2016-05-10 | 2018-07-20 | 苏州新代数控设备有限公司 | Numerical control device |
| CN108494889A (en) * | 2018-02-07 | 2018-09-04 | 广州视源电子科技股份有限公司 | Telecommunication circuit based on I2C buses and adjustment method |
| CN108362989A (en) * | 2018-02-28 | 2018-08-03 | 环胜电子(深圳)有限公司 | Voltage-stablizer tests system |
| CN108362989B (en) * | 2018-02-28 | 2020-11-17 | 环胜电子(深圳)有限公司 | Voltage stabilizer test system |
| CN109995397A (en) * | 2018-12-19 | 2019-07-09 | 安徽华东光电技术研究所有限公司 | 64 road Ka wave band array switch |
| CN114355796A (en) * | 2021-11-22 | 2022-04-15 | 杭州程天科技发展有限公司 | CAN communication interface extension method and extension circuit |
| CN114326370A (en) * | 2021-12-31 | 2022-04-12 | 上海节卡机器人科技有限公司 | Extended output circuit system and control method |
| CN114326370B (en) * | 2021-12-31 | 2024-04-30 | 节卡机器人股份有限公司 | Extended output circuit system and control method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102866683B (en) | 2014-12-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102866683B (en) | Signal conversion device and automatic testing system | |
| CN100568211C (en) | Realize method and the device of a plurality of I2C of visit with programming device from device | |
| CN108228513B (en) | Intelligent serial port communication device based on FPGA framework | |
| CN113608936B (en) | Multi-path interface test system and method | |
| CN105681145A (en) | FPGA-based FlexRay communication module | |
| CN103559863B (en) | LED lamp panel and LED display screen | |
| CN101097563A (en) | System and method for realizing board centralized management and controlling | |
| CN103903651B (en) | Double-line serial port build-in self-test circuit, and communication method thereof | |
| CN100530156C (en) | Control method and device between master-salve module | |
| CN110597745A (en) | Method and device for realizing multi-master multi-slave I2C communication of switch system | |
| CN102081586A (en) | Multiple I2C (Inter-IC) slot circuit system and method for transmitting I2C signal | |
| CN114564428A (en) | Airborne electronic equipment I/O port expansion system | |
| CN102609376B (en) | Serial bus memory, serial bus transmission system and method | |
| CN104332135A (en) | Parallel display circuit and display device thereof | |
| CN107015212A (en) | Universal interface board of the radar wave control based on VPX buses with monitoring platform of testing oneself | |
| CN102693196A (en) | Memory controller address and data pin multiplexing | |
| CN109407574A (en) | Output-controlling device and its method may be selected in a kind of multibus | |
| CN100395744C (en) | Method and system for realizing central control of central control unit to single board | |
| CN107239423A (en) | A kind of device based on extension IIC interfaces | |
| CN201698420U (en) | Small-sized pluggable optical receiving-sending module control device based on I2C bus | |
| CN103488601B (en) | A kind of clock delay, data access method, system and equipment | |
| CN201378316Y (en) | Universal input/output interface extension circuit and mobile terminal with same | |
| CN114660383A (en) | Universal ground detection test board card for load manager | |
| CN113626359A (en) | Signal switching device and method for flash memory chip of server | |
| CN107918593A (en) | The expansion interface circuit and communication means of the one-to-many universal serial bus of near-end |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20180731 Address after: 233400 Huaiyuan County Economic Development Zone, Bengbu, Anhui Patentee after: Anhui Dafu Electromechanical Technology Co., Ltd. Address before: 215000 33 Torch Road, hi tech Zone, Suzhou, Jiangsu Patentee before: Suzhou Tatfook Communication Technology Co., Ltd. |
|
| TR01 | Transfer of patent right |