JPH05120160A - Multi-chip module evaluating device - Google Patents

Abstract

PURPOSE:To trace the wiring signal which completes within a module substrate of a multi-chip module. CONSTITUTION:A monitor part 8 including a SUB data memory LDM 9, a comparator 10, and an address generator 11 is connected to a leader pad provided on a module substrate of a multi-chip module 1 for the wiring signal set between a floating point arithmetic unit 5 and a data memory 4 via a prober. Thus the wiring signal which completes within the module substrate can be traced. Then the wiring signal can be directly traced and the module 1 can be evaluated at a high speed and with no deterioration of the waveform.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a plurality of LSs on a substrate.
In a multi-chip module in which I is mounted into one module, each L that is a constituent element of the module
It relates to tracing SI signals.

[0002]

2. Description of the Related Art In recent years, LSIs having various functions have been developed, and various systems have been constructed using these LSIs. When considering the construction of a system using LSI,
The issues of transmission system and packaging density are very important. This 2
One of the means to solve one of the problems is a multi-chip module. However, in the multi-chip module, a plurality of LSIs having many functions are mounted on the module substrate, and therefore it is not easy to evaluate the module. Similar to the large-scaled LSI, there is no general-purpose evaluation method for a multichip module, and it often depends on the device. However, the problems of multi-chip module evaluation are almost the same.
The purpose is to trace signals that have not been extracted to the outside. In many cases, the function check of the module or the characteristics of the transmission system cannot be solved without actually seeing the signal when any problem occurs.

As a method for solving this problem, the following two methods are generally adopted. First of all, L
Similar to SI, there is a method of evaluating a module by providing a TEG. In this case, when evaluating the evaluation items from various angles in advance and designing the module,
The TEG will also be designed together. Therefore, the evaluation items that have been thoroughly examined are the most reliable evaluation methods and the most commonly used evaluation methods. However, considering the TEG is
Comparing to SI design, providing TEG itself requires a great deal of labor, overlaps not only with evaluation but also with design, and is not a simple method.

As a second method, a multi-chip module is generally drawn out as an external pin, focusing on mounting an LSI, which has already been developed and whose characteristics are well understood, on a substrate. This is a method of evaluation using only signals. According to this method, if the check pattern is devised, the evaluation of the multi-chip module can be realized with very simple hardware.
However, it is not possible to directly follow signals related to wiring completed in the module substrate.

An example of the second conventional method for evaluating a multi-chip module will be described below with reference to the drawings.

FIG. 5 shows an example of a multi-chip module. In FIG. 5, reference numeral 1 denotes a multi-chip module, which includes an instruction memory 3, a data memory 4, a floating point arithmetic unit 5, and a data transfer control unit 6.
It consists of Reference numeral 2 is an interface block unit, and 7 is a host computer. Hereinafter, 1 is MCM,
2 is called IU, 3 is called LIM, 4 is called LDM, and 5 is called EPU. As shown in FIG. 5, the MCM 1 is connected to the IU 2 in the TCU 6. Therefore, TCU
6 and EPU5, TCU6 and LDM4, EPU5 and L
The signal lines between DM4 and between EPU5 and LDM4 are signal lines whose wiring is completed in the module substrate.

The operation of the multi-chip module evaluation device configured as described above will be described below.

First, in the host computer 7, T
The operation check pattern programs of CU6, EPU5, LDM4, and LIM3 are prepared and sent to each element through IU2. In case of TCU6,
The operation pattern is directly sent to the TCU 6 through the IU 2.
On the contrary, the operation result is checked on the host computer 7 through the TCU 6 to the IU 2. If a trace function is added to the IU2, it is possible to directly trace the signal line if there is any malfunction.

In the case of LDM4, an operation check pattern is sent through IU2 and TCU6. Conversely, the operation result is T
Transfer to the host computer 7 through CU6, IU2,
Check on the host computer. At this time, if there is some malfunction, the signal line between the TCU 6 and the LDM 4 cannot be directly traced, but the signal line on the IU 2 side of the TCU is
As described above, since the cause can be investigated by tracing, it is possible to know the cause relatively easily by devising the operation check pattern.

Next, in the case of LIM3, IU2, TCU6, E
An operation check pattern is sent through PU5. On the contrary, the operation result is transferred to the host computer through EPU5, TCU6 and IU2 and checked on the host computer. Finally, in the case of EPU5, the calculated data is IU2, TCU6
Command data to IU2, T
It is stored in LIM3 through CU6 and EPU5. After that, according to the instruction data of LIM3, an operation is performed using the data of LDM4 to check the operation. The operation result is stored in LDM4 once, and then TCU6, I
Check on the host computer through U2.

As described above, conventionally, in the evaluation of the multi-chip module, when the TEG is not provided, the operation check pattern is sent to each element by using the signal in which the external pin is drawn from the interface block unit 2 side. The operation result is read out through the interface block unit 2 to check the operation.

[0012]

However, in the above configuration, when checking the LIM3, LDM4, and EPU5, it is necessary to pass the TCU6 without fail. Therefore, regarding the signal of the wiring on the module substrate. Must confirm the operation by the output signal from TCU6. In this case, if the number of wiring signals on the module board increases and the operation of the module becomes complicated, T
The operation cannot be confirmed only by tracing the signal at the output stage of the CU 6. Therefore, it becomes necessary to trace the wiring signal on the module substrate.

In view of the above-mentioned problems, the present invention provides a multi-chip module evaluation device capable of tracing a wiring signal on a module substrate without providing a TEG.

[0014]

In order to solve the above-mentioned problems, a multi-chip module evaluation device of the present invention is designed so that all control lines and all data line lead-out pads on a wiring board of a multi-chip module are provided on a module board. Provided to this pad from outside the multi-chip module via a prober, memory, address generator,
The configuration is such that a monitor unit having a comparator is connected.

[0015]

According to the present invention, the wiring signal completed in the module substrate in the multi-chip module can be directly extracted to the outside of the module from the extraction pad on the module substrate via the prober by the above-described structure. By providing a memory, an address generator, and a comparator for a signal taken out via the lead-out pad, the prober, it becomes possible to easily trace the signal in the module without providing the TEG.

[0016]

【Example】

(Embodiment 1) Hereinafter, a multi-chip module evaluation apparatus according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of wirings in a multichip module and a monitor unit for the wiring signals in the embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a multi-chip module, which includes an instruction memory (LIM) 3 and a data memory (LD
M) 4, a floating point unit (EPU) 5, and a data transfer control unit (TCU) 6. 2 is an interface block unit (I
U) and 7 are host computers, and 8 is a monitor unit between the floating point arithmetic unit 5 and the data memory (EPU-LDM).

FIG. 2 shows the configuration of the floating point arithmetic unit and the data memory monitor unit. In FIG. 2, 8
Is a monitor unit between EPU and LDM, and is composed of a sub data memory (SUB LDM) 9, a comparator 10, and an address generator 11.

The operation of the multi-chip module evaluation device configured as described above will be described below with reference to FIGS. 1 and 2.

In FIG. 2, the contents of the signal line to be traced are specified in advance on the host computer 7 and the IU
Send to 2. The address generator 11 is activated by the signal from the IU2, and the address generator 1
The address of the SUB LDM 9 is determined by 1 and the address of the signal to be traced from the LDM 4 is designated. Here, for the address of the SUB LDM 9 designated by the address generator 11, the signal of the control line or data line of the LDM 4 to be traced on the multi-chip module 1 designated by the address generator 11 is stored. By transferring the content of the signal of the LDM4 stored in the SUB LDM9 to the IU2, the EPU on the multichip module 1 in FIG.
The contents of the wiring signal between the LDM and the LDM can be traced.

Further, when the data is traced in the above manner, the data is transferred from the SUB LDM 9 to the IU 2, and the data is also transferred from the SUB LDM to the comparator 10 at the same time, so that the comparison data can be previously compared from the IU 2 side. If it is stored in 10, the operation can be confirmed on the comparator 10. In this case, since the signal transmission path is shortened as compared with checking the operation result on the host computer 7, deterioration of the signal waveform can be prevented, and thus more accurate and high-speed operation check can be performed.

As described above, according to this embodiment, the external pads of the multi-chip module 1 are connected to the lead pads of all control lines and all data lines between the EPU 5 and the LDM 4 on the multi-chip module 1 via the prober. Therefore, by connecting the monitor unit having the SUB LDM, the comparator, and the address generator, the wiring signal completed on the module substrate can be directly traced without providing the TEG on the multichip module 1. Moreover, it is possible to confirm the operation of the multi-chip module 1 faster and more accurately than the operation confirmation on the host computer 7.

(Embodiment 2) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of a multi-chip module evaluation device showing a second embodiment of the present invention. In FIG. 3, reference numeral 1 is a multi-chip module, and LIM3, L
It is composed of DM4, EPU5, and TCU6. 2 is I
U, 7 is a host computer, 8 is an EPU-LDM monitor unit,
12 is between the floating point arithmetic unit and the instruction memory (EPU
-LIM) shows a monitor unit.

FIG. 4 shows the structure of the floating point arithmetic unit and the instruction memory monitor unit. In FIG. 4, 12
Is an EPU-LIM monitor unit, which is composed of a sub-instruction memory (SUB LIM) 13, a comparator 14, and an address generator 15. As described above, the configuration in FIG. 4 is similar to that in FIG. The difference from FIG. 2 is that the SUB LIM 13 is connected to the lead-out pads for all control lines and all data lines between EPU and LIM.

Regarding the multi-chip module evaluation device configured as described above, referring to FIG. 3 and FIG.
The operation will be described below.

In FIG. 4, the contents of the signal line to be traced are designated in advance on the host computer 7 and the IU
Send to 2. The address generator 15 is activated by the signal from the IU 2 and the address generator 1
5, the address of SUBLIM 13 is determined, and the address of the signal to be traced from LIM 3 is designated. Here, with respect to the address of the SUB LIM 13 designated by the address generator 15, the signal of the control line or the data line of the LIM 4 to be traced on the multi-chip module 1, which is also designated by the address generator 15, is stored. By transferring the content of the signal of the LIM3 stored in the SUB LIM13 to the IU2, the E on the multichip module 1 in FIG.
The contents of the wiring signal between PU and LIM can be traced.

Further, when data is traced in the above manner, when data is transferred from the SUB LIM 9 to the IU 2, data is transferred from the SUB LIM to the comparator 14 at the same time. If stored in, the operation can be confirmed on the comparator 14. In this case, since the signal transmission path is shortened as compared with checking the operation result on the host computer 7, deterioration of the signal waveform can be prevented, and thus more accurate and high-speed operation check can be performed.

As described above, according to this embodiment, the external pads of the multi-chip module 1 are connected to the lead pads of all control lines and all data lines between the EPU5 and the LIM3 on the multi-chip module 1 via the prober. Therefore, by connecting the monitor unit having the SUB LIM, the comparator, and the address generator, it is possible to directly trace the wiring signal completed on the module substrate without providing the TEG on the multichip module 1. In addition, the multi-chip module 1 is faster and more accurate than the operation check on the host computer 7.
It is possible to confirm the operation of.

[0029]

INDUSTRIAL APPLICABILITY As described above, according to the present invention, in the multi-chip module, the wiring signal completed in the module board is transferred from the extraction pad provided on the module board to the memory outside the multi-chip module via the prober. By connecting to the wiring signal monitor unit having the address generator and the comparator, it is possible to directly trace the wiring signal completed in the module substrate without providing the TEG in the module.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a multi-chip module evaluation device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a monitor unit between a floating point arithmetic unit and a data memory for explaining the operation in the embodiment.

FIG. 3 is an overall configuration diagram of a multi-chip module evaluation device according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a monitor unit between a floating point arithmetic unit and an instruction memory for explaining the operation in the embodiment.

FIG. 5 is a schematic diagram of a conventional multi-chip module evaluation device.

[Explanation of symbols]

 1 multi-chip module 2 interface block unit 3 instruction memory 4 data memory 5 floating point arithmetic unit 6 data transfer control unit 7 host computer 8 monitoring unit between floating point arithmetic unit and data memory 9 sub data memory 10,14 comparator 11,15 address Generator 12 Floating point arithmetic unit, monitor section between instruction memories 13 Sub instruction memory

Claims (2)

[Claims] 1. A second processor that shares a bus with a first processor, a data memory (LDM) is connected to a shared bus between the processors, and further, to the first processor. , Equipped with instruction memory (LIM),
A first processor, a processing element (PE), which is made into one module, and which constitutes the PE;
Processor, LIM, between the first processor LDM which is the wiring completed inside the module of the multi-chip module (MCM) in which the lead-out pads for all the control lines and all the data lines of the LDM are provided on the module substrate, or
MCM via the prober for the lead-out pads for all control lines and all data lines between the second processor and LIM
A multi-chip module evaluation device comprising a monitor unit having a structure in which a memory is externally connected to the memory and an address generator and a comparator are connected to the memory. 2. The first processor according to claim 1,
A multi-chip module evaluation device in which a multi-chip module is configured by using a floating point arithmetic unit and a data transfer control unit as a second processor.