US20010038105A1 - Polysilicon evaluating method, polysilicon inspection apparatus and method for preparation of thin film transistor - Google Patents

Polysilicon evaluating method, polysilicon inspection apparatus and method for preparation of thin film transistor Download PDF

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US20010038105A1
US20010038105A1 US09/756,309 US75630901A US2001038105A1 US 20010038105 A1 US20010038105 A1 US 20010038105A1 US 75630901 A US75630901 A US 75630901A US 2001038105 A1 US2001038105 A1 US 2001038105A1
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polysilicon film
film
periodicity
linearity
polysilicon
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Hiroyuki Wada
Yoshimi Hirata
Ayumu Taguchi
Koichi Tatsuki
Nobuhiko Umezu
Shigeo Kubota
Tetsuo Abe
Akifumi Ooshima
Tadashi Hattori
Makoto Takatoku
Yukiyasu Sugano
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Sony Corp
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Priority claimed from JP2000005996A external-priority patent/JP4631116B2/ja
Priority claimed from JP2000005995A external-priority patent/JP4572436B2/ja
Priority claimed from JP2000005994A external-priority patent/JP4556266B2/ja
Application filed by Individual filed Critical Individual
Assigned to SONY CORPORATION reassignment SONY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WADA, HIROYUKI, SUGANO, YUKIYASU, TAKATOKU, MAKOTO, ABE, TETSUO, HATTORI, TADASHI, OOSHIMA, AKIFUMI, KUBOTA, SHIGEO, TAGUCHI, AYUMU, TATSUKI, KOICHI, UMEZU, NOBUHIKO, HIRATA, YOSHIMI
Publication of US20010038105A1 publication Critical patent/US20010038105A1/en
Priority to US10/394,223 priority Critical patent/US6933185B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

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  • This invention relates to a method for evaluating the state of a polysilicon film generated on annealing amorphous silicon, an inspection apparatus for inspecting a polysilicon film formed on annealing amorphous silicon, and a method for preparation of a thin-film transistor provided with a polysilicon film generated on annealing amorphous silicon.
  • This invention also relates to a method for preparation of a thin-film transistor of a bottom gate structure in which a gate electrode is formed between a substrate and a polysilicon film.
  • a thin-film transistor employing a polysilicon film as a channel layer is being put to practical use. If polysilicon is used in the channel layer, electrical field mobility of the thin-film transistor is increased significantly. Thus, if the transistor is used as a driving circuit for e.g., a liquid crystal display, it is possible to realize high definition, high speed and a small size of the display.
  • the state of crystals of the polysilicon film formed on the uppermost surface at a stage of completion of the polycrystallization process for the polysilicon film is checked by 100%-inspection or by random product sampling to check whether or not the product at this state is a reject. Also, the energy information furnished to the polysilicon film is fed back to the excimer laser annealing device to set an optimum laser power.
  • the present inventors have conducted perseverant researches, and have found that, when an amorphous silicon film is annealed to form a polysilicon film, there is presented linearity and/or periodicity in the spatial structure of the polysilicon film surface, depending on the energy applied to the amorphous silicon film during this annealing, and that evaluation of this linearity and/or periodicity in the surface spatial structure is effective in evaluating the polysilicon film.
  • the present inventors have also found that the linearity and/or periodicity presented in the spatial structure of the film surface of the polysilicon film as a result of the annealing becomes maximum when a certain pre-set energy is applied, and that adjustment or control of the energy applied to the amorphous silicon film based on the energy which maximizes the linearity and/or periodicity on the spatial structure of the surface of the polysilicon film therefore is effective to optimize the characteristics of the polysilicon film.
  • the present inventors have found that the linearity and/or periodicity presents itself in the spatial structure of a polysilicon film surface when polysilicon film as a channel of a thin-film transistor on the substrate is formed.
  • a polysilicon film is formed by forming a film of amorphous silicon and by laser annealing the resulting amorphous silicon film using excimer laser having a linear illuminating surface.
  • excimer laser having a linear illuminating surface.
  • the light beam is moved in a direction perpendicular to the longitudinal direction of the linear illuminating surface as the hest energy is applied to the entire glass substrate surface.
  • micro-irregularities are formed on the surface of the polysilicon film produced in this manner by the excimer laser annealing, and that these micro-irregularities present periodicity in a direction perpendicular to the direction of the light beam movement.
  • the present inventors have found that evaluation of this linearity and/or periodicity is effective in evaluating whether or not the polysilicon film formed is usable as a thin-film transistor.
  • the present inventors have also found that the result of evaluation of the linearity and/or periodicity can be effectively utilized in adjusting or controlling the excimer laser energy.
  • the present invention provides a method for evaluating a polysilicon film formed by annealing an amorphous silicon film, including evaluating the linearity and/or periodicity of a spatial structure of the film surface of the polysilicon film, and evaluating the state of the polysilicon film based on the result of evaluation of linearity and/or periodicity.
  • the present invention provides an apparatus for inspecting a polysilicon film formed by annealing an amorphous silicon film, which includes means for observing the spatial structure of the surface of the polysilicon film and means for evaluating the linearity and/or periodicity of the spatial structure of the film surface of the polysilicon film acquired by the observing means to inspect the state of the polysilicon film based on the result of evaluation of the linearity and/or periodicity.
  • the present invention provides a method for preparation of a thin-film transistor which includes the steps of forming an amorphous silicon film, annealing the formed amorphous silicon film to form a polysilicon film, and evaluating the linearity and/or periodicity of the spatial structure of the film surface of the polysilicon film to evaluate the state of the polysilicon film based on the result of evaluation of linearity and/or periodicity.
  • the present invention provides a method for preparation of a thin-film transistor having a step of forming a polysilicon film serving as a channel layer by laser annealing an amorphous silicon film by an excimer laser annealing device which includes the steps of forming a gate electrode on a substrate, forming an amorphous silicon film on the substrate on which the gate electrode has been formed, laser annealing the amorphous silicon films on plural substrates or plural locations of the amorphous silicon film on a sole substrate to form a polysilicon film, evaluating the linearity and/or periodicity of a spatial structure of a surface of the polysilicon film formed on the gate electrode on the substrate, evaluating the linearity and/or periodicity of the spatial structure of the surface of the polysilicon film formed on locations other than the gate electrode on the substrate, calculating the manufacturing margin of the polysilicon film in the laser annealing based on the linearity and/or periodicity of the spatial structure of the polysilicon film surface
  • the present invention provides a method for preparation of a thin-film transistor of a bottom gate structure in which a gate electrode is formed between a substrate and a polysilicon film which includes the steps of forming a gate electrode on the substrate, forming an amorphous silicon film on the substrate on which the gate electrode has been formed, laser annealing the amorphous silicon film to form a polysilicon film, and checking the acceptability of the polysilicon film based on a spatial structure of the surface of the polysilicon film.
  • the checking step includes evaluating the linearity and/or periodicity of the spatial structure of the surface of the polysilicon film formed on the gate electrode of each substrate, evaluating the linearity and/or periodicity of the spatial structure of the surface of the polysilicon film formed on a location other than the gate electrode of each substrate, and checking the acceptability of the polysilicon film based on the linearity and/or periodicity of the spatial structure of the surface of the polysilicon film formed on the gate electrode or on the linearity and/or periodicity of the spatial structure of the surface of the polysilicon film formed on a location other than the gate electrode.
  • this method for preparation of a thin-film transistor of the bottom gate structure the polysilicon film generated on laser annealing the amorphous silicon film is evaluated.
  • polysilicon evaluation or inspection can be achieved readily non-destructively, whilst the numerical computation is feasible without visual inspection, thus assuring automatic evaluation. Moreover, subjective evaluation can be achieved with high accuracy.
  • FIG. 1 illustrates a schematic cross-sectional structure of a bottom gate type TFT.
  • FIG. 2 illustrates a cross-sectional structure of a bottom gate type TFT following formation of a polysilicon film.
  • FIG. 3 illustrates the relation between the grain size of a polysilicon film and the energy furnished by excimer laser annealing.
  • FIG. 4 illustrates an image on the surface of a polysilicon film when excimer laser annealing is performed with an optimum laser power value, an image on the surface of a polysilicon film when excimer laser annealing is performed with a power smaller than the optimum laser power value and an image on the surface of a polysilicon film when excimer laser annealing is performed with a power larger than the optimum laser power value.
  • FIG. 5 is a schematic view of a polysilicon film evaluation device embodying the present invention.
  • FIG. 6 is a flowchart for illustrating an evaluation sequence of a polysilicon film.
  • FIG. 7 illustrates an autocorrelation image for high periodicity.
  • FIG. 8 illustrates an autocorrelation image for high periodicity.
  • FIG. 9 is a flowchart for illustrating an evaluation sequence of a polysilicon film.
  • FIG. 10 illustrates an autocorrelation image for high periodicity in case of evaluation by the other polysilicon film.
  • FIG. 11 illustrates an autocorrelation image for low periodicity in case of evaluation by the other polysilicon film.
  • FIG. 12 illustrates AC values as found for a specified image.
  • FIG. 13 illustrates autocorrelation values for the energy applied to a polysilicon film.
  • FIG. 14 illustrates AC values and the grain size for the energy applied to the polysilicon film.
  • FIG. 15 illustrates AC values with respect to the laser power of the excimer laser in a bottom gate type TFT.
  • FIG. 16 illustrates typical experimental data of AC values with respect to the laser power of the excimer laser in a bottom gate type TFT.
  • FIG. 17 illustrates AC values as found based on an image photographed with a microscopic device employing a UV laser (DUV) AC values as found based on an image photographed with SEM.
  • DUV UV laser
  • FIG. 18 illustrates the structure of a specified application (EQC) of a polysilicon film evaluation device to a production process of a bottom gate type TFT.
  • FIG. 19 illustrates the relation between the margin of preparation of the energy applied to the polysilicon film and variations in the excimer laser power in case the laser power is set to an optimum value.
  • FIG. 20 illustrates the relation between the margin of preparation of the energy applied to the polysilicon film and variations in the excimer laser power in case the laser power is not set to an optimum value.
  • FIG. 21 illustrates a typical relation between the margin of production of a bottom gate type TFT and the laser power and a method for finding the optimum value of the laser power from this typical relation.
  • FIG. 22 illustrates another typical relation between the margin of production of a bottom gate type TFT and the laser power and a method for finding the optimum value of the laser power from this typical relation.
  • FIG. 23 shows the structure of a specified application (IPQC) in which a polysilicon film evaluation device is applied to a production process of the bottom gate type TFT.
  • IPQC specified application
  • FIG. 24 illustrates a method for verifying, from the AC value of the bottom gate type TFT whether or not the polysilicon film is acceptable.
  • FIG. 25 illustrates typical results of the above check on plural LCDs formed on a glass substrate.
  • the polysilicon film evaluation device of the present embodiment is used for inspecting the polysilicon film formed in the production process of a thin-film transistor having bottom gate structure (bottom gate type TFT).
  • the bottom gate type TFT is a thin-film transistor in which a gate electrode, a gate insulating film and a polysilicon film (channel layer) are formed sequentially from the lower layer side on e.g., a glass substrate. That is, the bottom gate type TFT is such a TFT in which a gate electrode is formed between the polysilicon film as a channel layer and a glass substrate.
  • a bottom gate type TFT 1 is comprised of a glass substrate 2 on which are layered a gate electrode 3 , a first gate insulating film 4 , a second gate insulating film 5 , a polysilicon film 6 , a stop 7 , a first interlayer insulating film 8 , a second interlayer insulating film 9 , a wiring 10 , a planarizing film 11 and a transparent electrically conductive film 12 , as shown in FIG.1.
  • the gate electrode 3 is formed by depositing molybdenum (Mo) to a thickness of 50 to 300 nm on the glass substrate 2 and by subsequent patterning by anisotropic etching.
  • Mo molybdenum
  • the first gate insulating film 4 is a silicon nitride (SiN x ) film, e.g., 50 nm in thickness.
  • SiN x silicon nitride
  • the second gate insulating film 5 is formed e.g., of silicon dioxide (SiO 2 ), e.g., 120 nm in thickness, this silicon dioxide (SiO 2 ) being layered on the first gate insulating film 4 .
  • the polysilicon film 6 is formed e.g., of polysilicon (p-Si) 40 nm in thickness. This polysilicon film 6 is layered on the second gate insulating film 5 . This polysilicon film 6 operates as a channel layer of the bottom gate type TFT 1 .
  • This polysilicon film 6 is formed on polycrystallization by annealing amorphous silicon (a-Si) formed to a thickness of 40 nm by e.g., the LPCVD method. In the polycrystallization process for the polysilicon film 6 , laser annealing processing employing an excimer laser as a UV laser is used.
  • a pulsed light beam having a linear irradiating surface is radiated and the amorphous silicon is polycrystallized to polysilicon as the illumination area of the pulsed beam is moved.
  • the illuminating surface of the light beam has a length in the longitudinal direction of 20 cm and a length along its short side of 400 ⁇ m, with the pulse frequency being 300 Hz.
  • the scanning direction of the light beam in excimer laser annealing is perpendicular to the longitudinal direction of the illuminating surface of the linear laser, that is the short side direction.
  • the polysilicon film 6 is first polycrystallized by excimer laser annealing and subsequently doped with impurity ions to form a source/drain area. This ion doping is executed after forming a stop 7 at a position where the gate electrode 3 is formed, in order to prevent impurities from being implanted on the polysilicon film 6 overlying the gate electrode 3 .
  • This stop 7 is formed of silicon dioxide (SiO 2 ) with a film thickness of 200 nm and is formed using a mask used in forming the gate electrode 3 .
  • the first interlayer insulating film 8 is formed by silicon nitride (SiN x ) with a film thickness e.g., of 300 nm, this silicon nitride (SiN x ) being layered on the polysilicon film 6 .
  • the second interlayer insulating film 9 is formed of silicon dioxide (SiO 2 ) with a film thickness e.g., of 150 nm, this silicon dioxide (SiO 2 ) being layered on the first interlayer insulating film 8 .
  • the wiring 10 is formed by depositing aluminum (Al) and titanum (Ti), after providing a contact hole for connection to a source/drain area of the polysilicon film 6 at a location corresponding to a source/drain area of the first interlayer insulating film 8 and the second interlayer insulating film 9 , and by patterning on etching. This wiring 10 interconnects the source/drain area of each transistor formed on the polysilicon film 6 to form a pre-set circuit pattern on the substrate.
  • Al aluminum
  • Ti titanum
  • the planarizing film (HRC) 11 is a film for planarizing the surface of the bottom gate type TFT 1 and is formed to a film thickness of 2 to 3 ⁇ m after depositing the wiring 10 .
  • the transparent electrically conductive film 12 is of a transparent electrically conductive material, such as, for example, ITO, and is an electrically conductive line for interconnecting the wiring 10 to an external element or wiring present externally of the bottom gate type TFT 1 .
  • This transparent electrically conductive film 12 is formed on the planarizing film 11 after boring the contact hole in the planarizing film 11 .
  • the electrical field mobility of the channel field is increased appreciably. So, if the bottom gate type TFT 1 is used as e.g., a driving circuit for the liquid crystal display, it is possible to realize refinement, high speed and size reduction of the display. Moreover, in the above-mentioned bottom gate type TFT 1 , the so-called low-temperature polycrystallization process, in which amorphous silicon is heat-treated using excimer laser annealing to form the polysilicon film 6 . The result is that the thermal damage to the glass substrate 2 in the polycrystallization process is diminished to render possible the use of an inexpensive heat-resistant large-area glass substrate.
  • the grain size of polysilicon represents a critical factor governing the electrical field mobility of the polysilicon film 6 .
  • the grain size depends appreciably on the energy applied to the polysilicon film 6 at the time of excimer laser annealing. So, the laser power control and stabilization at the time of excimer laser annealing influence the characteristics and the yield of production of the completed bottom gate type TFT 1 significantly.
  • the grain size of the polysilicon film 6 is varied significantly. For example, if the laser power is increased excessively, silicon crystals are comminuted to cause so-called linear defects. If conversely the laser power is excessive, there result so-called writing defects such that sufficiently large grain size is not obtained.
  • the excimer laser annealing device used in the excimer laser annealing as described above undergoes larger laser power output fluctuations, so that it is difficult to control the laser power so that the grain size for the portion of the polysilicon film 6 lying on the glass substrate 2 and that for the portion of the polysilicon film 6 lying on the gate electrode 3 will be optimum.
  • the 100% inspection of the state of the crystals of the polysilicon film 6 formed on the uppermost surface of the polysilicon film 6 is performed when the polycrystallization process of the polysilicon film 6 is completed, as shown for example in FIG. 2, or inspection is performed on products sampled at random, to check whether or not the manufactured products are rejects.
  • the information on the energy applied to the polysilicon film 6 is fed back to the excimer laser annealing device to set the laser power.
  • the polysilicon film evaluation device embodying the present invention is used for evaluating the polysilicon film at a stage when the polycrystallization process for the polysilicon film 6 is completed, to check whether or not the obtained product at this stage is a reject, and for feeding back the information to the excimer laser annealing device to set the laser energy:
  • the mobility of the thin-film transistor is influenced appreciably by the polysilicon grain size, as discussed above. For realizing sufficient mobility, a larger polysilicon grain size is preferred.
  • the grain size of the polysilicon film depends appreciably on the energy applied in the excimer laser annealing. Referring to FIG. 3, the grain size of the polysilicon film increases with increasing energy applied. When reaching or exceeding a pre-set energy indicated by L in the drawing, variation in the grain size becomes smaller and stabilized. The energy L is referred to as the minimum allowed energy. If the energy is increased further, the change in the grain size is increased, with the polysilicon proving micro-sized grains with a certain threshold value indicated H in the drawing as a boundary. This energy is referred to as the maximum allowed energy H.
  • the illuminated laser power is controlled to be in a range from the minimum allowed energy L, where the grain size is becoming stabilized, up to the maximum allowed energy H directly before the grain size proves the micro-sized grains.
  • FIG. 4B shows the image on a film surface of the polysilicon film, with the laser power set to a value smaller than the optimum value
  • FIG. 4C shows the image on a film surface of the polysilicon film, with the laser power set to a value larger than the optimum value.
  • the laser scanning direction in the excimer laser annealing is the direction X in the drawing.
  • the amorphous silicon film is irradiated with a light beam having a linear irradiating surface, with the laser light scanning direction being perpendicular to the longitudinal direction of the laser beam irradiating surface.
  • the surface image of the polysilicon film with the laser power set to its optimum value exhibits linearity as compared to the surface images of the polysilicon film with the laser power not set to its optimum value (FIGS. 4A and 4C).
  • the surface image of FIG. 4B exhibits linearity with respect to the laser scanning direction, indicated by X in FIG. 4. That is, the polysilicon film surface, with the laser power set to the optimum value, has a characteristic linear shape exhibiting linearity in its spatial structure.
  • the surface image of the polysilicon film with the laser power set to its optimum value exhibits periodicity as compared to the surface images of the polysilicon film with the laser power not set to its optimum value (FIGS. 4A and 4C).
  • the surface image of FIG. 4B exhibits periodicity in the direction perpendicular to the laser scanning direction (indicated by arrow Y in FIG. 4). That is, the surface image of the polysilicon film with the laser power set to its optimum value has a characteristic linear shape exhibiting linearity in its spatial structure.
  • the polysilicon film evaluating device embodying the present invention checks the polysilicon film state by exploiting the above-described characteristics. That is, the polysilicon film evaluating device embodying the present invention performs numerical analysis of the surface image of the polysilicon film following excimer laser annealing to check whether the surface spatial structure of the polysilicon film exhibits periodicity, whether the surface spatial structure of the polysilicon film exhibits linearity or whether the surface spatial structure of the polysilicon film exhibits both linearity and periodicity, in order to inspect the state of the polysilicon film of the bottom gate type TFT.
  • the photographed image of the polysilicon film exhibiting both the linearity and periodicity is represented schematically, it may be represented as having numerous straight lines arranged parallel to and at an equal spacing to one another. If the photographed image of the polysilicon film not exhibiting linearity nor periodicity is represented schematically, it may be represented as having irregular short lines appearing irregularly.
  • a given image is translated in a direction having the assumed periodicity and in a perpendicular direction thereto and correlation of the translated image is evaluated numerically. For example, if an image exhibiting linearity and periodicity is translated, there is presented an image with a high correlation, that is with a higher rate of image superposition. If conversely an image exhibiting no linearity nor periodicity is translated, there is presented no highly correlated image, that is, there is presented no image with a high rate of image superposition, at a pre-set period.
  • this second smallest value is used to diminish the value of defocussing and may be replaced by the smallest value or the third smallest value, fourth smallest value and so on, and that the side peak value is the second locally largest value in the y-direction from the point of origin, excluding the point of origin, less the second locally smallest value in the y-direction from the point of origin.
  • the polysilicon film evaluating apparatus embodying the present invention is such a device in which a production substrate of a bottom gate type TFT, that is a substrate obtained directly after formation of the polysilicon film on excimer laser annealing an amorphous silicon film, is imaged by a microscopic device employing a UV light laser with a wavelength of 266 nm, and the state of the polysilicon film formed is evaluated from the photographing image.
  • FIG. 5 shows a configuration of a polysilicon film evaluation apparatus embodying the present invention.
  • a polysilicon film evaluation apparatus 20 shown in FIG. 5 includes a movable stage 21 , a UV solid laser light source 22 , a CCD camera 23 , an optical fiber probe 24 , a beam splitter 25 , an objective lens 26 , a control computer 27 and a picture processing computer 28 .
  • the movable stage 21 is a stage for supporting a substrate 1 on which has been formed a polysilicon film being inspected. This movable stage 21 has the functions of supporting the substrate 1 being inspected and of transporting the substrate 1 being inspected to a pre-set inspection position.
  • the movable stage 21 includes an X-stage, a Y-stage, a Z-station and a suction plate.
  • the X- and Y-stages are stages movable in the horizontal direction. By these X- and Y-stages, the substrate 1 to be inspected is moved to a pre-set inspecting position.
  • the Z-stage is a stage moved in the vertical direction for adjusting the stage height.
  • the suction plate is used for immobilizing the substrate 1 being inspected by suction.
  • the UV solid laser light source 22 is a UV light source with a wavelength of 266 nm and uses e.g., a Nd:YAG fourth harmonics full-solid laser. Meanwhile, a UV laser light source with a wavelength of the order of 166 nm, recently developed, may also be employed.
  • the CCD camera 23 which is a camera highly sensitized with respect to UV light and has a CCD image sensor as an internal imaging device, images the surface of the substrate 1 by this CCD image sensor.
  • This CCD camera 23 has its main body portion cooled to suppress the thermal noise, readout noise or the circuit noise generated in e.g., the CCD image sensor.
  • the optical fiber probe 24 is a waveguide channel for the UV laser light for guiding the UV laser light radiated from the UV solid laser light source 22 to the beam splitter 25 .
  • the beam splitter 25 reflects the UV laser light from the UV solid laser light source 22 to illuminate the reflected light through the objective lens 26 onto the substrate 1 on the movable stage 21 .
  • the beam splitter 25 transmits the reflected from the substrate 1 to illuminate the transmitted light on a high sensitivity low noise camera 3 .
  • the beam splitter 25 is a laser light separator for separating the optical path of the optical system of the light radiated from e.g., the UV solid laser light source 22 from the optical path of the optical system of the reflected light to the CCD camera 23 .
  • the objective lens 26 is an optical component for enlarging the reflected light from the substrate 1 to detect the enlarged light.
  • This objective lens 26 has the NA of 0.9 and a wavelength of 266 nm, and is corrected for aberration.
  • the objective lens 26 is arranged between the beam splitter 25 and the movable stage 21 .
  • the control computer 27 is responsible for lighting control of the laser light of the UV solid laser light source 22 , movement position control of the movable stage 21 and switching control of the objective lens 26 .
  • the picture processing computer 28 is responsible for capturing and analysis of an image of the substrate 1 photographed by the CCD image sensor provided on the CCD camera 23 and for evaluation of the polysilicon film formed on the substrate 1 .
  • the UV laser light radiated from the UV solid laser light source 22 is illuminated on the substrate 1 through the optical fiber probe 24 , beam splitter 25 and the objective lens 26 .
  • the UV laser light radiated on the substrate 1 is reflected by the surface of the substrate 1 .
  • the reflected light falls on the CCD camera 23 through the objective lens 26 and the beam splitter 25 .
  • the CCD camera 23 images the incident reflected light by the image sensor to route the surface image information of the polysilicon film, obtained on imaging, to the picture processing computer 28 .
  • the picture processing computer 28 evaluates the state of the polysilicon film, based on the information on the surface image of the captured polysilicon film, in a manner as hereinafter explained. Based on the result of evaluation, the picture processing computer 28 finds setting values of the laser power at the time of excimer laser annealing aimed at generating the polysilicon film, or checks whether or not the polysilicon film formed on the substrate 1 is acceptable.
  • a picture on the surface of the polysilicon film is captured at step S 1 .
  • the autocorrelation function then is calculated from the captured image at step S 2 .
  • a surface perpendicular to the arraying direction including the (0, 0) on the image coordinate is sliced at step S 3 .
  • the peak and side peak values of the autocorrelation function on the slicing plane were then calculated and the ratio of the peak value and the side peak values was taken to find the AC value at step S 4 . Based on this AC value, the polysilicon film was evaluated at step S 4 .
  • the autocorrelation function is a function shown by the following equation: R ⁇ ( ⁇ ) r ⁇ lim ⁇ ⁇ ⁇ 1 T ⁇ ⁇ 0 T ⁇ f ⁇ ( x ) ⁇ f ⁇ ( x + ⁇ ) ⁇ ⁇ x
  • This autocorrelation function R(ô) is a function representing the correlation when a certain function f(x) is translated by ô in the x-direction.
  • This polysilicon film evaluation apparatus 20 finds the autocorrelation of the surface picture of the polysilicon film using the following Winner-Hintin theorem.
  • the image information specifically captured is termed “iii”.
  • FIGS. 7 and 8 show an autocorrelation function for an image exhibiting high autocorrelation, that is a spatial structure of the polysilicon film surface exhibiting high periodicity and linearity.
  • FIG. 8 shows an autocorrelation function for an image exhibiting low autocorrelation, that is a surface spatial structure of the polysilicon film exhibiting poor periodicity and linearity.
  • the polysilicon film evaluation apparatus 20 slices a plane perpendicular to the arraying direction, that is the linearity exhibiting direction, and which comprehends coordinate values (0, 0) on an image surface, from the autocorrelation function calculated using this Winner-Hintin theorem, to find a function obtained on slicing.
  • the plane comprehending coordinate values (0, 0) on an image surface is sliced to standardize the value from the autocorrelation function varied with experimental parameters such as the volume of the illuminated light or CCD gain.
  • the function obtained on this slicing is the above-mentioned autocorrelation function R(ô) in a direction perpendicular to the arraying direction.
  • the autocorrelation function may be found using the Winner-Hintin theorem as follows:
  • FIGS. 10 and 11 show an autocorrelation function for an image exhibiting high autocorrelation, that is a surface spatial structure of the polysilicon film exhibiting high periodicity and linearity.
  • FIG. 11 shows an autocorrelation function for an image exhibiting low autocorrelation, that is a surface spatial structure of the polysilicon film exhibiting poor periodicity and linearity.
  • the polysilicon film evaluation apparatus 20 finds locally maximum peak and side peak values from the produced function. Then, it finds the ratio of the locally maximum value to the side peak value. The resulting ratio is an AC value.
  • the bottom gate type TFT 1 thus photographs the surface image of the polysilicon film and finds the autocorrelation function of the photographed image to achieve numerical representation of the linearity and periodicity of the polysilicon film.
  • the AC value is increased proportionally as from a time point when the energy applied to the polysilicon film by excimer laser annealing reaches a certain energy EB 1 , with the AC value becoming maximum at a certain energy ET.
  • the AC value is at a peak value for this maximum energy RT and is subsequently decreased proportionally.
  • the AC value ceases to decrease at a certain energy EB 2 , with the AC value at this time being the minimum value. That is, the AC value exhibits peak characteristics for a given energy value.
  • the maximum value in the graph representing peak characteristics of AC values, is comprised in an energy range in which the grain size of the polysilicon film is optimum.
  • the energy E B1 for which the AC value begins to be increased proportionally, is lower than the allowed minimum energy L for which the grain size accorded to the polysilicon film is optimum.
  • the energy E B2 for which the proportional decrease of the AC value ceases to reach the maximum value coincides with the allowed maximum energy which is the threshold energy value for which the crystal grains of the polysilicon film becomes micro-sized crystals.
  • the polysilicon film 6 on the gate electrode 3 is higher than the polysilicon film 6 on the glass substrate 2 (on the source/drain area) in energy diffusion characteristics in case of laser annealing. So, even if the laser power applied from the excimer laser annealing device is the same, the energy applied to the portion of the polysilicon film 6 lying on the gate electrode 3 differs from that applied to the portion of the polysilicon film 6 lying on the glass substrate 2 , that is on the source/drain area, with the result that the grain size differs in the two portions.
  • the relation between the AC value and the laser power of the excimer laser is as shown in FIG. 15, such that the peak value on the gate electrode, that is on the source/drain area, is at a different position from that on the gate electrode.
  • the AC value of the portion of the polysilicon film lying on the glass substrate, that is on the source/drain area is at a peak at a laser power lower than that for the portion of the polysilicon film 6 lying on the gate electrode.
  • FIG. 16 shows illustrative specified experimental data of the AC values with respect to the laser power of the excimer laser.
  • the AC values are of such characteristics that there are two different peak values, that is the peak value on the gate electrode and the peak value on the glass substrate. From the graph of FIG. 16, it is seen that the laser power for excimer laser annealing is optimally set to 380 mJ.
  • a microscopic device employing a UV light laser is applied as the polysilicon imaging device.
  • the device for photographing an original image usable for evaluating the linearity and/or periodicity of the polysilicon film is not limited to this microscopic device.
  • the linearity and/or periodicity of the surface spatial structure of the polysilicon film may be evaluated based on the picture as observed by SEM.
  • the output value of the actual laser power undergoes fluctuations with respect to the laser power setting value, as discussed above.
  • the output laser power shows Gaussian characteristics of distribution such that certain fluctuations are produced with respect to the pre-set power setting.
  • the manufacturing margin of the energy afforded to the polysilicon film that is an energy range outside which the product is a reject, is of a large value relative to the fluctuations.
  • the laser power of the excimer laser annealing device is set to an optimum value by exploiting peak properties of the AC value of the bottom gate type TFT as follows:
  • the laser power on the lower limit threshold of the manufacturing margin is the laser power corresponding to the minimum allowed energy (L) afforded to the polysilicon film on the gate electrode, specifically, the laser power on the left end of the AC value portion drawn with a thick line on the gate electrode indicated in FIGS. 21 and 22 (MO(L)).
  • the laser power on the upper limit threshold of the manufacturing margin is the laser power corresponding to the maximum allowed energy (H) afforded to the polysilicon film on the gate electrode, specifically, the laser power on the right end of the AC value portion drawn with a thick line on the glass substrate indicated in FIGS. 21 and 22 (G(H)).
  • a median value of the manufacturing margin, thus found, is found, and the laser power for this median value is set as an optimum value.
  • the output value of the actual laser power undergoes larger fluctuations with respect to the laser power setting, as discussed above. So, with the polysilicon film evaluation apparatus 20 , the decision as to acceptability is given on the basis of 100 % or approximately 100% inspection so as not to transfer the flaw in the excimer laser annealing process to subsequent processes.
  • the polysilicon film evaluation apparatus 20 gives the decision as to acceptability as follows:
  • acceptability may be achieved in case laser annealing is performed in a range from the allowed minimum energy L of the energy applied to the portion of the polysilicon film lying on the gate electrode to the laser power corresponding to the allowed maximum energy H applied to the portion of the polysilicon film lying on the glass substrate.
  • this range begins at the laser power at the left end of the AC value curve on the gate electrode drawn with a thick line and terminates at the laser power at the right end of the AC value curve on the glass substrate drawn with a thick line. That is, if the polysilicon film is annealed with the laser power comprised in the ranges ⁇ circle over (3) ⁇ and ⁇ circle over (4) ⁇ in FIG. 24, the polysilicon film is acceptable.
  • the polysilicon film evaluation apparatus 20 first finds the AC value on the portion of the polysilicon film lying on the gate electrode. The polysilicon film evaluation apparatus 20 then checks whether or not this AC value is larger than the threshold value AC L (MO) as found when the allowed minimum energy L is applied to the polysilicon film. If the AC value is larger than the threshold value AC L (Mo), the laser power is within the range ⁇ circle over (3) ⁇ in FIG. 24, and hence the polysilicon film is verified to be acceptable.
  • AC L threshold value
  • the threshold value AC B The autocorrelation value when the polysilicon film portion on the gate electrode is annealed with the laser power corresponding to the allowed maximum energy H afforded to the polysilicon film on the glass substrate is set as being the threshold value AC B . It is then checked whether or not the AC value of the polysilicon film portion lying on the gate electrode is within a range from threshold value AC L to threshold value AC B and also whether or not the AC value of the polysilicon film portion lying on the glass substrate is lower than the threshold value AC B . If this condition is met, the laser power is within the range ⁇ circle over (4) ⁇ in FIG. 24 and hence the polysilicon film is verified to be acceptable. If the above condition is not met, the laser power is within the ranges of ⁇ circle over (1) ⁇ , ⁇ circle over (2) ⁇ and ⁇ circle over (5) ⁇ in FIG. 24 and hence the polysilicon film is verified to be a reject.
  • the reject positions can be located by carrying out 100%-inspection on the LCDs, even on the occasion of occurrence of partial flaws, thereby relieving the load otherwise imposed on the downstream side processing.

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JP2000005994A JP4556266B2 (ja) 2000-01-07 2000-01-07 ポリシリコン評価方法、ポリシリコン検査装置、薄膜トランジスタ製造方法、及び、アニール処理装置
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JP4278940B2 (ja) 2002-09-09 2009-06-17 株式会社 液晶先端技術開発センター 結晶化装置および結晶化方法
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TWI612293B (zh) 2016-11-18 2018-01-21 財團法人工業技術研究院 Ｌｔｐｓ背板結晶品質檢測裝置及其方法

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US20220052082A1 (en) * 2020-08-14 2022-02-17 Samsung Display Co., Ltd. Display device manufacturing apparatus and method

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KR100753782B1 (ko) 2007-08-31
TW490802B (en) 2002-06-11
DE60133057T2 (de) 2009-02-26
EP1115150A2 (fr) 2001-07-11
US20030183853A1 (en) 2003-10-02
DE60133057D1 (de) 2008-04-17
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EP1115150A3 (fr) 2004-10-20
EP1115150B1 (fr) 2008-03-05

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