US20010035570A1 - Package for semiconductor devices - Google Patents

Package for semiconductor devices Download PDF

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Publication number
US20010035570A1
US20010035570A1 US09/488,087 US48808700A US2001035570A1 US 20010035570 A1 US20010035570 A1 US 20010035570A1 US 48808700 A US48808700 A US 48808700A US 2001035570 A1 US2001035570 A1 US 2001035570A1
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Prior art keywords
back side
insulating layers
wiring pattern
laminate
external connection
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Granted
Application number
US09/488,087
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US6340841B2 (en
Inventor
Takahiro Iijima
Akio Rokugawa
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Assigned to SHINKO ELECTRIC INDUSTRIES CO., LTD. reassignment SHINKO ELECTRIC INDUSTRIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: IIJIMA, TAKAHIRO, ROKUGAWA, AKIO
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H05K2201/09518—Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Definitions

  • the present invention relates to a package for semiconductor devices.
  • FIG. 1 shows a build-up board 10 having a core board 12 of an insulating material having base wiring patterns 13 and 14 formed on both sides and electrically connected to each other by a throughhole plated coating 15 .
  • Insulating layers 16 and 17 are formed on the base wiring patterns 13 and 14 , respectively, and contain viaholes 16 a and 17 a.
  • Electroless and the subsequent electrolytic plating treatments are conducted to form a copper plated coating on the insulating layers 16 and 17 and the side walls of the viaholes 16 a and 17 a.
  • the copper plated coating is then patterned by etching to form upper wiring patterns 18 and 19 , as a first layer, which are connected to the base wiring patterns 13 and 14 through the copper plated coating of the viaholes 16 a and 17 a.
  • the outermost wiring pattern 20 on the front side of the core board 12 has pads to which a semiconductor chip 21 is bonded by flip-chip bonding.
  • the outermost wiring pattern 22 on the back side of the core board 12 has external connection terminals on which solder bumps 23 are formed for external connection.
  • the throughholes and viaholes are filled with a resin and the front and back surfaces are covered with solder resist layers 24 , 24 for protection.
  • the build-up board 10 is advantageous because insulating layers are formed by application of a resin to provide a structure with a small height and the wiring patterns 18 , 19 , 20 and 22 are formed by plating to allow fine patterning, both enabling mounting of a high density semiconductor chip 21 .
  • the object of the present invention is to provide a package for semiconductor devices which can be produced in a reduced number of steps with a reduced cost.
  • a package for semiconductor devices comprising:
  • a core board having a front side with a front side base wiring pattern formed thereon and a back side with a back side base wiring pattern formed thereon, the front and back side wiring patterns being electrically connected to each other through a conductor segment penetrating the core board;
  • an external connection wiring pattern including external connection terminals on the back side laminate of insulating layers, wherein the external connection wiring pattern is electrically connected to the back side base wiring pattern through a via penetrating the back side laminate of insulating layers.
  • the present inventive structure provides a reduced number of production steps and a reduced production cost because there are no wiring patterns within the back side laminate of insulating layers, except for optional power or ground planes.
  • the intermediate insulating layers on the front side of the core board and the insulating layers of the back side laminate are in the same number to provide similar structures on both sides of the core board, thereby preventing distortion of the core board or a completed package.
  • the via penetrating the back side laminate of insulating layers may be either formed of a plated coating on a side wall of viaholes penetrating the back side laminate of insulating layers, or formed of a conductor segment filling the viaholes.
  • the package may include bumps formed on the external connection terminals.
  • the package may optionally include a power plane or a ground plane which intervenes between the insulating layers of the back side laminate and is electrically connected to the via penetrating the back side laminate.
  • FIG. 1 shows a conventional package structure for semiconductor device, in a cross-sectional view
  • FIG. 2 shows a preferred embodiment of the package structure for semiconductor devices according to the present invention, in a cross-sectional view
  • FIGS. 3A and 3B show a modified embodiment of the package structure according to the present invention, in a cross-sectional view and an enlarged cross-sectional view, respectively;
  • FIGS. 4A to 4 C show process steps of producing another preferred embodiment of the package structure according to the present invention, in cross-sectional views.
  • FIG. 2 schematically illustrates a cross section of a preferred embodiment of the package for semiconductor devices according to the present invention.
  • a package 30 for semiconductor devices includes a core board 31 of an insulating material having base wiring patterns 32 and 33 on both sides, respectively, which are formed by drilling a double-sided copper-clad board to open throughholes 34 , electroless- and electrolytic-copper plating the board to form a copper plated coating or conductor segment 35 on the side wall of the throughholes 34 , and then etching the copper cladding to form a desired base wiring patterns 32 and 33 on both sides of the board 31 .
  • the throughholes 34 are filled with a filler resin 36 .
  • the base wiring patterns may be of any metal other than copper.
  • the conductor segment 35 may not be composed of a plated coating but may be composed of a conducting material filling the throughholes 34 .
  • a front side insulating layer 38 and a back side insulating layer 39 are then formed by applying polyimide or other resin in the form of liquid or a resin sheet onto the base wiring pattern 32 on the front side of the board 31 and onto the base wiring pattern 33 on the back side of the board 31 .
  • the insulating layer 38 on the front side of the board 31 is then bored by a laser beam to form viaholes 40 . At this stage, no viaholes are formed in the insulating layer 39 on the back side of the board 31 .
  • Electroless and the subsequent electrolytic copper plating treatments are conducted to form a copper plated coating on the insulating layer 38 and on the side wall of the viaholes 40 .
  • the copper plated coating is then patterned by etching to form the first upper wiring pattern 42 , which is electrically connected to the front side base wiring pattern 32 through a via plated coating 41 on the side wall of the viaholes 40 .
  • the multilayer wiring patterns including the front side laminate and the base wiring pattern 32 provide leads from terminals of a semiconductor chip 70 mounted on the package 30 .
  • the insulating layers 39 and 45 on the back side of the core board 31 are bored by a laser beam to form viaholes 53 penetrating the insulating layers 39 and 45 so that portions of the back side base wiring pattern 33 are exposed.
  • the viaholes 53 having a relatively large depth can be bored by laser beam machining.
  • Electroless and subsequent electrolytic copper plating treatments are conducted to form a copper plated coating on the outermost back side insulating layer 45 and on the side wall of the viaholes 53 .
  • the copper plated coating is then patterned by etching to an external connection wiring pattern 54 , which is electrically connected to the back side base wiring pattern 33 on the back side of the core board 31 through the via plated coating 56 , which is part of the copper plated coating.
  • a solder resist layer 57 is formed on the outermost back side wiring pattern 54 , and then, is bored by photolithography to define external connection terminals 55 , which are part the wiring pattern 54 .
  • the package 30 may further include solder balls or other bumps 59 for external connection.
  • the wiring patterns on the front side of the core board 31 are sufficiently dense and fine to provide leads from a semiconductor chip so that extremely densely and finely disposed terminals of a semiconductor chip are electrically connected to far more sparsely disposed terminals of the base wiring pattern 32 step by step through a plurality of the front side wring patterns.
  • the package structure of the present invention only requires formation of multiple wiring patterns on the front side of the core board and, on the back side, does not require formation of wiring patterns except for an optional power or ground plane to enable reduction in the number of process steps and the production cost.
  • FIGS. 3A and 3B show a modified preferred embodiment of the package structure of the present invention, in which throughholes 34 of a core board 31 are closed on both ends with a plated metal 32 A formed on a filler resin 36 and on a portion of a base wiring pattern 32 surrounding the throughholes 34 and in which viaholes 53 are filled with a plated copper or other metal to form vias 61 instead of having the copper plated coating 56 shown in FIG. 2.
  • This embodiment is advantageous because vias can be formed on vias and external connection terminals such as pins 62 can be also formed on vias to provide a package with a further improved wiring density and a reduced electrical resistivity of vias.
  • FIGS. 4A to 4 C Another preferred embodiment of the package structure of the present invention will be described with reference to FIGS. 4A to 4 C, in which the corresponding parts are denoted by the same symbols as used in FIG. 2.
  • insulating layers 38 and 39 are formed on a core board 31 and viaholes 40 are bored through the insulating layer 38 . At this stage, no viaholes are formed in the insulating layer 39 .
  • Electroless and the subsequent electrolytic copper plating treatments are conducted to form a copper plated coating on the insulating layer 38 , the side wall of the viaholes 40 and the insulating layer 39 .
  • the copper plated coatings on the insulating layers 38 and 39 are patterned by etching to form a wiring pattern 42 and a flat conductor layer 60 .
  • a laminate of upper wiring patterns with intervening insulating layers is formed on the front side of the board 31 .
  • Insulating layers 45 and 46 are formed on the flat copper plated coating 60 on the back side of the board 31 .
  • the insulating layers 39 , 45 and 46 on the back side of the board 31 are bored by a laser beam to form viaholes 53 penetrating these insulating layers through.
  • This is advantageously effected in such a manner that viaholes 53 are first bored through the insulating layers 45 and 46 , and then, the laser beam is further focused to bore the flat copper layer 60 to form viaholes with a reduced diameter, followed by boring the insulating layer 39 to form viaholes 53 b with a diameter a little smaller than that of the viaholes 53 a.
  • boring of the copper layer 60 is effected by a laser beam having an energy a little higher than that of the laser beam used to bore the insulating layers 39 , 45 and 46 .
  • Boring of the viaholes 53 having a large depth can be carried out by laser beam machining as described above.
  • electroless and the subsequent electrolytic copper plating treatments are conducted to form a copper plated coating on the outermost insulating layer 46 and on the side wall of the viaholes 53 and the copper plated coating is then patterned by etching to form an outermost wiring pattern 54 having external connection terminals 55 and electrically connected to the back side base wiring pattern 33 on the back side of the core board 31 through a via 56 , which is part of the copper plated coating.
  • a solder resist layer 57 is formed on the outermost wiring pattern 54 and, then, is bored by photolithography to expose the external connection terminals 55 .
  • the package 30 may further include solder balls or other bumps 59 on the external connection terminals 55 .
  • the copper layer 60 can serve as a power plane or a ground plane.
  • the via 56 is stepped in the intermediate portion in which the copper layer 60 is partially exposed to provide an area to ensure secure bonding between the via 56 and a power plane or a ground plane formed by the copper layer 60 .
  • a power plane or a ground plane may be formed on any insulating layer other than the outermost insulating layer 46 .
  • This embodiment is advantageous because the package structure of the present invention only requires formation of multiple wiring patterns on the front side of the core board and, on the back side, does not require formation of wiring patterns except for the power or ground plane to enable reduction in the number of process steps and the production cost.
  • insulating layers are preferably formed in the same number on both sides of the core board 31 to prevent undesired distortion of a package.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A package for semiconductor devices, comprising a core board having a front side with a front side base wiring pattern formed thereon and a back side with a back side base wiring pattern formed thereon, the front and back side wiring patterns being electrically connected to each other through a conductor segment penetrating the core board; a front side laminate of upper wiring patterns with intermediate insulating layers intervening therebetween on the front side base wiring pattern, in which each adjacent pair of the upper wiring patterns are electrically connected to each other through a via plated coating on a side wall of viaholes penetrating one of the intermediate insulating layers that intervenes between the adjacent pair and in which an outermost one of the upper wiring patterns is patterned for electrical connection to a semiconductor chip; a back side laminate of insulating layers on the back side base wiring pattern; an external connection wiring pattern including external connection terminals on the back side laminate of insulating layers; wherein the external connection wiring pattern is electrically connected to the back side base wiring pattern through a via penetrating the back side laminate of insulating layers.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a package for semiconductor devices. [0002]
  • 2. Description of the Related Art [0003]
  • It is a growing trend to use a package for semiconductor devices in the form of a build-up board composed of a core board having multilayer wiring patterns formed on both sides by build-up process. [0004]
  • FIG. 1 shows a build-up [0005] board 10 having a core board 12 of an insulating material having base wiring patterns 13 and 14 formed on both sides and electrically connected to each other by a throughhole plated coating 15.
  • Insulating [0006] layers 16 and 17 are formed on the base wiring patterns 13 and 14, respectively, and contain viaholes 16 a and 17 a.
  • Electroless and the subsequent electrolytic plating treatments are conducted to form a copper plated coating on the [0007] insulating layers 16 and 17 and the side walls of the viaholes 16 a and 17 a. The copper plated coating is then patterned by etching to form upper wiring patterns 18 and 19, as a first layer, which are connected to the base wiring patterns 13 and 14 through the copper plated coating of the viaholes 16 a and 17 a.
  • The process is repeated to form a multilayer wiring patterns on both sides of the [0008] core board 12.
  • The [0009] outermost wiring pattern 20 on the front side of the core board 12 has pads to which a semiconductor chip 21 is bonded by flip-chip bonding.
  • The [0010] outermost wiring pattern 22 on the back side of the core board 12 has external connection terminals on which solder bumps 23 are formed for external connection.
  • The throughholes and viaholes are filled with a resin and the front and back surfaces are covered with [0011] solder resist layers 24, 24 for protection.
  • The build-up [0012] board 10 is advantageous because insulating layers are formed by application of a resin to provide a structure with a small height and the wiring patterns 18, 19, 20 and 22 are formed by plating to allow fine patterning, both enabling mounting of a high density semiconductor chip 21.
  • However, there is a problem in that the process requires a large number of steps causing an increased cost when forming insulating layers on both sides of a [0013] core board 12 by application of a resin or other materials, boring viaholes in each of the insulating layers by laser machining or other methods, plating and etching to form a wiring pattern on each of the insulating layers.
    • SUMMARY OF THE INVENTION
  • The object of the present invention is to provide a package for semiconductor devices which can be produced in a reduced number of steps with a reduced cost. [0014]
  • To achieve the object according to the present invention, there is provided a package for semiconductor devices, comprising: [0015]
  • a core board having a front side with a front side base wiring pattern formed thereon and a back side with a back side base wiring pattern formed thereon, the front and back side wiring patterns being electrically connected to each other through a conductor segment penetrating the core board; [0016]
  • a front side laminate of upper wiring patterns with intermediate insulating layers intervening therebetween on the front side base wiring pattern, in which each adjacent pair of the upper wiring patterns are electrically connected to each other through a via plated coating on a side wall of viaholes penetrating one of the intermediate insulating layers that intervenes between the adjacent pair and an outermost one of the upper wiring patterns is patterned for electrical connection to a semiconductor chip; [0017]
  • a back side laminate of insulating layers on the back side base wiring pattern; and [0018]
  • an external connection wiring pattern including external connection terminals on the back side laminate of insulating layers, wherein the external connection wiring pattern is electrically connected to the back side base wiring pattern through a via penetrating the back side laminate of insulating layers. [0019]
  • The present inventive structure provides a reduced number of production steps and a reduced production cost because there are no wiring patterns within the back side laminate of insulating layers, except for optional power or ground planes. [0020]
  • It is advantageous if the intermediate insulating layers on the front side of the core board and the insulating layers of the back side laminate are in the same number to provide similar structures on both sides of the core board, thereby preventing distortion of the core board or a completed package. [0021]
  • The via penetrating the back side laminate of insulating layers may be either formed of a plated coating on a side wall of viaholes penetrating the back side laminate of insulating layers, or formed of a conductor segment filling the viaholes. [0022]
  • The package may include bumps formed on the external connection terminals. [0023]
  • The package may optionally include a power plane or a ground plane which intervenes between the insulating layers of the back side laminate and is electrically connected to the via penetrating the back side laminate.[0024]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a conventional package structure for semiconductor device, in a cross-sectional view; [0025]
  • FIG. 2 shows a preferred embodiment of the package structure for semiconductor devices according to the present invention, in a cross-sectional view; [0026]
  • FIGS. 3A and 3B show a modified embodiment of the package structure according to the present invention, in a cross-sectional view and an enlarged cross-sectional view, respectively; and [0027]
  • FIGS. 4A to [0028] 4C show process steps of producing another preferred embodiment of the package structure according to the present invention, in cross-sectional views.
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS EXAMPLE 1
  • FIG. 2 schematically illustrates a cross section of a preferred embodiment of the package for semiconductor devices according to the present invention. [0029]
  • A [0030] package 30 for semiconductor devices includes a core board 31 of an insulating material having base wiring patterns 32 and 33 on both sides, respectively, which are formed by drilling a double-sided copper-clad board to open throughholes 34, electroless- and electrolytic-copper plating the board to form a copper plated coating or conductor segment 35 on the side wall of the throughholes 34, and then etching the copper cladding to form a desired base wiring patterns 32 and 33 on both sides of the board 31. The throughholes 34 are filled with a filler resin 36.
  • The base wiring patterns may be of any metal other than copper. [0031]
  • The [0032] conductor segment 35 may not be composed of a plated coating but may be composed of a conducting material filling the throughholes 34.
  • A front [0033] side insulating layer 38 and a back side insulating layer 39 are then formed by applying polyimide or other resin in the form of liquid or a resin sheet onto the base wiring pattern 32 on the front side of the board 31 and onto the base wiring pattern 33 on the back side of the board 31.
  • The [0034] insulating layer 38 on the front side of the board 31 is then bored by a laser beam to form viaholes 40. At this stage, no viaholes are formed in the insulating layer 39 on the back side of the board 31.
  • Electroless and the subsequent electrolytic copper plating treatments are conducted to form a copper plated coating on the [0035] insulating layer 38 and on the side wall of the viaholes 40.
  • The copper plated coating is then patterned by etching to form the first [0036] upper wiring pattern 42, which is electrically connected to the front side base wiring pattern 32 through a via plated coating 41 on the side wall of the viaholes 40.
  • The same process is repeated to form a front [0037] side insulating layer 44 and a back side insulating layer 45 on the upper wiring pattern 42 and on the back side insulating layer 39, respectively, followed by forming viaholes 47 in the front side insulating layer 44 and forming the second upper wiring pattern 50 electrically connected to the first upper wiring pattern 42 through a via plated coating 48 formed on the side wall of the viaholes 47.
  • This produces a front side laminate of [0038] upper wiring patterns 42 and 50 with intervening front side insulating layers 38 and 44 therebetween on the back side of the core board 31, and on the back side of the core board, a back side laminate of the back side insulating layers 39 and 45.
  • The multilayer wiring patterns including the front side laminate and the [0039] base wiring pattern 32 provide leads from terminals of a semiconductor chip 70 mounted on the package 30.
  • The [0040] insulating layers 39 and 45 on the back side of the core board 31 are bored by a laser beam to form viaholes 53 penetrating the insulating layers 39 and 45 so that portions of the back side base wiring pattern 33 are exposed. The viaholes 53 having a relatively large depth can be bored by laser beam machining.
  • Electroless and subsequent electrolytic copper plating treatments are conducted to form a copper plated coating on the outermost back [0041] side insulating layer 45 and on the side wall of the viaholes 53. The copper plated coating is then patterned by etching to an external connection wiring pattern 54, which is electrically connected to the back side base wiring pattern 33 on the back side of the core board 31 through the via plated coating 56, which is part of the copper plated coating.
  • A [0042] solder resist layer 57 is formed on the outermost back side wiring pattern 54, and then, is bored by photolithography to define external connection terminals 55, which are part the wiring pattern 54.
  • Thus, a [0043] package 30 for semiconductor devices is completed.
  • The [0044] package 30 may further include solder balls or other bumps 59 for external connection.
  • The wiring patterns on the front side of the [0045] core board 31 are sufficiently dense and fine to provide leads from a semiconductor chip so that extremely densely and finely disposed terminals of a semiconductor chip are electrically connected to far more sparsely disposed terminals of the base wiring pattern 32 step by step through a plurality of the front side wring patterns.
  • Thus, the package structure of the present invention only requires formation of multiple wiring patterns on the front side of the core board and, on the back side, does not require formation of wiring patterns except for an optional power or ground plane to enable reduction in the number of process steps and the production cost. [0046]
  • FIGS. 3A and 3B show a modified preferred embodiment of the package structure of the present invention, in which [0047] throughholes 34 of a core board 31 are closed on both ends with a plated metal 32A formed on a filler resin 36 and on a portion of a base wiring pattern 32 surrounding the throughholes 34 and in which viaholes 53 are filled with a plated copper or other metal to form vias 61 instead of having the copper plated coating 56 shown in FIG. 2.
  • This embodiment is advantageous because vias can be formed on vias and external connection terminals such as pins [0048] 62 can be also formed on vias to provide a package with a further improved wiring density and a reduced electrical resistivity of vias.
    • EXAMPLE 2
  • Another preferred embodiment of the package structure of the present invention will be described with reference to FIGS. 4A to [0049] 4C, in which the corresponding parts are denoted by the same symbols as used in FIG. 2.
  • As shown in FIG. 4A, insulating [0050] layers 38 and 39 are formed on a core board 31 and viaholes 40 are bored through the insulating layer 38. At this stage, no viaholes are formed in the insulating layer 39.
  • Electroless and the subsequent electrolytic copper plating treatments are conducted to form a copper plated coating on the insulating [0051] layer 38, the side wall of the viaholes 40 and the insulating layer 39.
  • The copper plated coatings on the insulating [0052] layers 38 and 39 are patterned by etching to form a wiring pattern 42 and a flat conductor layer 60.
  • A laminate of upper wiring patterns with intervening insulating layers is formed on the front side of the [0053] board 31.
  • Insulating [0054] layers 45 and 46 are formed on the flat copper plated coating 60 on the back side of the board 31.
  • Referring to FIG. 4B, the insulating [0055] layers 39, 45 and 46 on the back side of the board 31 are bored by a laser beam to form viaholes 53 penetrating these insulating layers through. This is advantageously effected in such a manner that viaholes 53 are first bored through the insulating layers 45 and 46, and then, the laser beam is further focused to bore the flat copper layer 60 to form viaholes with a reduced diameter, followed by boring the insulating layer 39 to form viaholes 53 b with a diameter a little smaller than that of the viaholes 53 a. Namely, boring of the copper layer 60 is effected by a laser beam having an energy a little higher than that of the laser beam used to bore the insulating layers 39, 45 and 46.
  • Boring of the [0056] viaholes 53 having a large depth can be carried out by laser beam machining as described above.
  • Referring to FIG. 4C, electroless and the subsequent electrolytic copper plating treatments are conducted to form a copper plated coating on the outermost insulating [0057] layer 46 and on the side wall of the viaholes 53 and the copper plated coating is then patterned by etching to form an outermost wiring pattern 54 having external connection terminals 55 and electrically connected to the back side base wiring pattern 33 on the back side of the core board 31 through a via 56, which is part of the copper plated coating.
  • A solder resist [0058] layer 57 is formed on the outermost wiring pattern 54 and, then, is bored by photolithography to expose the external connection terminals 55.
  • Thus, a [0059] package 30 for semiconductor devices is completed.
  • The [0060] package 30 may further include solder balls or other bumps 59 on the external connection terminals 55.
  • In this embodiment, the [0061] copper layer 60 can serve as a power plane or a ground plane.
  • As shown in FIG. 4C, the via [0062] 56 is stepped in the intermediate portion in which the copper layer 60 is partially exposed to provide an area to ensure secure bonding between the via 56 and a power plane or a ground plane formed by the copper layer 60.
  • A power plane or a ground plane may be formed on any insulating layer other than the outermost insulating [0063] layer 46.
  • This embodiment is advantageous because the package structure of the present invention only requires formation of multiple wiring patterns on the front side of the core board and, on the back side, does not require formation of wiring patterns except for the power or ground plane to enable reduction in the number of process steps and the production cost. [0064]
  • In either of Examples 1 and 2, insulating layers are preferably formed in the same number on both sides of the [0065] core board 31 to prevent undesired distortion of a package.
  • It will be readily recognized by a person skilled in the art that the present invention is not limited to the embodiments described herein but includes various modifications within the spirit of the present invention. [0066]

Claims (5)

1. A package for semiconductor devices, comprising:
a core board having a front side with a front side base wiring pattern formed thereon and a back side with a back side base wiring pattern formed thereon, the front and back side wiring patterns being electrically connected to each other through a conductor segment penetrating the core board;
a front side laminate of upper wiring patterns with intermediate insulating layers intervening therebetween on the front side base wiring pattern, in which each adjacent pair of the upper wiring patterns are electrically connected to each other through a via plated coating on a side wall of viaholes penetrating one of the intermediate insulating layers that intervenes between the adjacent pair and in which an outermost one of the upper wiring patterns is patterned for electrical connection to a semiconductor chip;
a back side laminate of insulating layers on the back side base wiring pattern; and
an external connection wiring pattern including external connection terminals on the back side laminate of insulating layers, wherein the external connection wiring pattern is electrically connected to the back side base wiring pattern through a via penetrating the back side laminate of insulating layers.
2. A package according to
claim 1
, wherein the via penetrating the back side laminate of insulating layers is either formed of a plated coating on a side wall of viaholes penetrating the back side laminate of insulating layers, or is formed of a conductor segment filling the viaholes.
3. A package according to
claim 1
, wherein the intermediate insulating layers on the front side of the core board and the insulating layers of the back side laminate are arranged in the same number.
4. A package according to
claim 1
, wherein the external connection terminals of the external connection wiring pattern have bumps or pins formed thereon.
5. A package according to
claim 1
, further comprising a power plane or a ground plane intervening between the insulating layers of the back side laminate and electrically connected to the via penetrating the back side laminate.
US09/488,087 1999-01-25 2000-01-20 Build-up board package for semiconductor devices Expired - Lifetime US6340841B2 (en)

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JP01599599A JP3577421B2 (en) 1999-01-25 1999-01-25 Package for semiconductor device

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