US20010026994A1 - Method for forming element isolating region - Google Patents
Method for forming element isolating region Download PDFInfo
- Publication number
- US20010026994A1 US20010026994A1 US09/812,876 US81287601A US2001026994A1 US 20010026994 A1 US20010026994 A1 US 20010026994A1 US 81287601 A US81287601 A US 81287601A US 2001026994 A1 US2001026994 A1 US 2001026994A1
- Authority
- US
- United States
- Prior art keywords
- oxide film
- silicon oxide
- silicon
- film
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
Abstract
Description
- 1. Field of the Invention
- The invention relates to a method for forming an element isolating region in a semiconductor device and, more particularly to, a method for forming a Shallow Trench Isolation (STI) by filling with an insulator film a shallow trench in a surface of a semiconductor substrate.
- The present application claims priority of Japanese Patent Application No.2000-078773 filed on Mar. 21, 2000, which is hereby incorporated by reference.
- 2. Description of the Related Art
- With improvements in fine patterning of semiconductor elements formed in a semiconductor silicon substrate, it has been difficult for a method for forming element isolating regions by use of a conventional LOCal Oxidation of Silicon (LOCOS) method to form accurately an active region having a width in an order of 0.1 μm or less, thus being mainly replaced by an STI method.
- FIGS. 7A to7E are schematically cross-sectional views for illustrating conventional steps of forming an element isolating region. As can be seen from FIGS. 7A to 7E, a conventional STI is formed as follows.
- First, a
pad oxide film 302 is formed on asilicon substrate 301 by thermal oxidation. Asilicon nitride film 303 is formed which covers thepad oxide film 302. The portions of thesilicon nitride film 303 and thepad oxide film 302 which exist on a formation-reserved element isolating region are patterned sequentially by anisotropic etching. By conducting anisotropic etching on thesilicon substrate 301 using thesilicon nitride film 303 as a mask,shallow trenches 305 are formed in the formation-reserved element isolating region on the surface of thesilicon substrate 301. - Next, a
thermal oxide film 307 is formed on the surface of thetrenches 305 by thermal oxidation. - High-Density Plasma-Enhanced CVD (HD-PECVD) accompanied by bias sputtering is conducted to form a
silicon oxide film 311 throughout on the surface to a predetermined film thickness to thereby fill and cover thetrenches 305 completely with the silicon oxide film 311 (see FIG. 7A). - Next, Chemical Mechanical Polishing (CMP) is conducted (using the
silicon nitride film 303 as a stopper) on thesilicon oxide film 311 until an upper surface of thesilicon nitride film 303 is exposed, to leave a silicon oxide film 311 a in the trenches 305 (see FIG. 7B). - Next, etching-back is conducted on the silicon oxide film311 a using buffered hydrofluoric acid (BHF) to leave a
silicon oxide film 311 b in thetrenches 305. At this point in time, an upper surface of thesilicon oxide film 311 b roughly agrees in level with an upper surface of thepad oxide film 302 in level (see FIG. 7C). - Next, for example, wet etching by use of hot phosphoric acid is conducted on the
silicon nitride film 303 to remove it (see FIG. 7D). - Subsequently, the
silicon oxide film 311 b and thepad oxide film 302 are removed by wet etching by use of hydrofluoric acid (e.g., buffered hydrofluoric acid). With this, portions of a surface of thesilicon substrate 301 which are expected to be an active region (element forming region) are exposed to leave asilicon oxide film 311 c in thetrenches 305, thus completing the conventional STI (see FIG. 7E). - The above-mentioned conventional STI forming method, however, may generate a fine scratch (hereinafter called micro-scratch)315 in the surface of the silicon oxide film 311 a as a result of CMP conducted thereon (see FIG. 7B). The micro-scratch 315 may sometimes measure about 0.1 μm to 100 μm in length.
- Further, since after the
trenches 305 are formed it is difficult to avoid etching thepad oxide film 302 during cleaning before thethermal oxide film 307 is formed, an under-cut is liable to be formed at the ends of thesilicon nitride film 303. Accordingly, when thesilicon oxide film 311 is formed, density of thesilicon oxide film 311 may decrease in vicinity of a lower edge of an end of thissilicon nitride film 303, thus further generating a void (not shown). - If the silicon oxide film311 a is anisotropically etched with buffered hydrofluoric acid with a presence of the micro-scratch 315, the micro-scratch 315 expands anisotropically. When, in this case, the micro-scratch 315 comes near the lower edge of the end of the above-mentioned
silicon nitride film 303, etching of thesilicon oxide film 311 rapidly spreads from there as a center to all around a belonging element forming region, to form a notch shape (hereinafter called debot 316) in thesilicon oxide film 311 b around that element forming region (see FIG. 7C). This debot 316 further develops to provide adebot 316 a during wet-etching in which thesilicon oxide film 311 c is left (see FIG. 7E). - Thus, the conventional STI forming method suffers from a problem that width of a specific element forming region becomes larger than its design value all over its peripheries. If a semiconductor device has MOS transistors therein, such a transistor MOS may be formed that has, for example, an extremely increased reverse narrow channel effect, thus deteriorating the electric characteristics of the MOS transistor. Also, in patterning of gate electrodes in post-steps, etch residues of a conductive film may be induced at the
debot 316 a. - In view of the above, it is an object of the present invention to provide a method for forming an STI to suppress an effective expansion of an element forming region. It is another object of the invention to provide a method for forming the STI easy to suppress an increase in a reverse channel effect, deterioration of electric characteristics, and induction of etch residues of gate electrodes in a post-step in some transistors in a semiconductor device containing MOS transistors. It is further another object of the invention to provide a method for forming the STI easy to suppress an occurrence of the debot even when the micro-scratch is present.
- According to a first aspect of the present invention, there is provided a method for forming an element isolating region, including the steps of:
- forming a pad oxide film on a surface of a silicon substrate by thermal oxidation and forming a silicon nitride film which covers the pad oxide film and then conducting anisotropic etching sequentially on portions of the silicon nitride film and the pad oxide film which exist on a formation-reserved element isolating region to then conduct anisotropic etching using the silicon nitride film as a mask in order to form a trench in a surface of the silicon substrate, thus forming a first silicon oxide film throughout on the surface by High-Density Plasma-Enhanced CVD (HD-PECVD) accompanied by bias sputtering;
- conducting Chemical Mechanical Polishing (CMP) on the first silicon oxide film until a surface of the silicon nitride film is exposed;
- forming by spin coating or liquid-phase deposition a second silicon oxide film which covers a surface of the silicon nitride film and a surface of the first silicon oxide film to thereby conduct heat treatment in an oxygen atmosphere, serving also to refine the second silicon oxide film;
- conducting such anisotropic etching using an etching gas that an etching rate for the silicon oxide film may be equal to an etching rate for the silicon nitride film to thereby remove the second silicon oxide film in order to remove the silicon nitride film and the first silicon oxide film; and
- remove by wet etching the pad oxide film, and the first silicon oxide film until at least the surface of the silicon substrate is exposed.
- In the foregoing first aspect, a preferable mode is one wherein the second silicon oxide film is formed by spin coating and consists of an inorganic SOG (Spin-On-Glass) film made of silicon hydride sesqui-oxide (HSiO{fraction (3/2)})n as a material.
- According to a second aspect of the present invention, there is provided a method for forming an element isolating region, including the steps of:
- forming a pad oxide film on a surface of a silicon substrate by thermal oxidation and forming a silicon nitride film which covers the pad oxide film and then conducting anisotropic etching sequentially on portions of the silicon nitride film and the pad oxide film which exist on a formation-reserved element isolating region to conduct anisotropic etching using the silicon nitride film as a mask in order to form a trench in a surface of the silicon substrate, thus forming a first silicon oxide film throughout on the surface by HD-PECVD accompanied by bias sputtering;
- conducting CMP on the first silicon oxide film until a surface of the silicon nitride film is exposed;
- forming by spin coating or LPD a second silicon oxide film which covers a surface of the silicon nitride film and a surface of the first silicon oxide film to thereby conduct heat treatment in an oxygen atmosphere, serving also to refine the second silicon oxide film;
- conducting such anisotropic etching using an etching gas that an etching rate for the silicon oxide film may be equal to an etching rate for the silicon nitride film to thereby remove the second silicon oxide film in order to remove the silicon nitride film and the first silicon oxide film partially;
- remove a residue of the silicon nitride film by wet etching; and
- removing by wet etching the residue of the second silicon oxide film, the pad oxide film and the first silicon oxide film until the surface of the silicon substrate is exposed. In the foregoing second aspect, a preferable mode is one wherein the second silicon oxide film is formed by spin coating and consists of an organic SOG film or an inorganic SOG film made of silicon hydride sesqui-oxide.
- According to a third aspect of the present invention, there is provided a method for forming an element isolating region, including the steps of:
- forming a pad oxide film on a surface of silicon substrate by thermal oxidation and forming a silicon nitride film which covers the pad oxide film and then conducting anisotropic etching sequentially on portions of the silicon nitride film and the pad oxide film which exist on a formation-reserved element isolating region to conduct anisotropic etching using the silicon nitride film as a mask in order to form a trench in the surface of the silicon substrate, thus forming a first silicon oxide film throughout on the surface by HD-PECVD accompanied by bias sputtering;
- conducting CMP on the first silicon oxide film until a surface of the silicon nitride film is exposed;
- forming by spin coating or LPD a second silicon oxide film which covers a surface of the silicon nitride film and a surface of the silicon oxide film to thereby conduct heat treatment in an oxygen atmosphere, serving also to refine the second silicon oxide film;
- conducting such anisotropic etching using an etching gas that an etching rate for the silicon oxide may be equal to an etching rate for silicon nitride film to thereby remove the second silicon oxide film in order to remove the silicon nitride film and the first silicon oxide film partially;
- remove a residue of the silicon nitride film by wet etching; and
- removing by wet etching the pad oxide film and the first silicon oxide film until the surface of the silicon substrate is exposed.
- In the foregoing third aspect, a preferable mode is one wherein the second silicon oxide film is formed by spin coating and consists of an organic SOG film or an inorganic SOG film made of silicon hydride sesqui-oxide as a material. According to a fourth aspect of the present invention, there is provided a method for forming an element isolating region, including the steps of:
- forming a pad oxide film on a surface of a silicon substrate by thermal oxidation and forming a silicon nitride film which covers the pad oxide film and then conducting anisotropic etching sequentially on portions of the silicon nitride film and the pad oxide film which exist on a formation-reserved element isolating region to conduct anisotropic etching using the silicon nitride film as a mask in order to form a trench in the surface of the silicon substrate, thus forming a first silicon oxide film throughout on the surface by HD-PECVD accompanied by bias sputtering;
- conducting CMP on the first silicon oxide film until a surface of the silicon nitride film is exposed;
- forming by spin coating or LPD a second silicon oxide film which covers the silicon nitride film and the first silicon oxide film to thereby conduct heat treatment, serving also to refine the second silicon oxide film;
- conducting such anisotropic etching using an etching gas that an etching rate for the silicon oxide film may be higher than an etching rate for the silicon nitride film to thereby remove the second silicon oxide film in order to remove the silicon nitride film partially at the same time as removing the first silicon oxide film until a surface of the first silicon oxide film is equal to a surface of the pad oxide film in level;
- removing a residue of the silicon nitride film by wet etching; and
- removing by wet etching the second oxide film, the pad oxide film, and the first silicon oxide film until the surface of the silicon substrate is exposed.
- In the foregoing fourth aspect, a preferable mode is one wherein the second silicon oxide film is formed by spin coating and consists of an organic SOG or an inorganic SOG film made of silicon hydride sesqui-oxide as a material. According to a fifth aspect of the present invention, there is provided a method for forming an element isolating region, including the steps of:
- forming a pad oxide film on a surface of a silicon substrate by thermal oxidation and forming a silicon nitride film which covers the pad oxide film and then conducting anisotropic etching sequentially on portions of the silicon nitride film and the pad oxide film which exist on a formation-reserved element isolating region to conduct anisotropic etching using the silicon nitride film as a mask in order to form a trench in the surface of the silicon substrate, thus forming a first silicon oxide film which has a film thickness smaller than ½ of a minimum width of the trench by Low Pressure CVD (LPCVD) throughout on the surface;
- forming by spin coating or LPD a second silicon oxide film which covers a surface of the first silicon oxide film to thereby conduct first heat treatment in an oxygen atmosphere, serving also to refine the second silicon oxide film;
- conducting CMP on the second and first silicon oxide films until a surface of the silicon nitride film is exposed;
- forming by spin coating or LPD a third silicon oxide film which covers the silicon nitride film and the first and second silicon oxide films to thereby conduct second heat treatment in an oxygen atmosphere, serving also to refine the third silicon oxide film;
- conducting such anisotropic etching using an etching gas that an etching rate for the silicon oxide film may be equal to an etching rate for the silicon nitride film to remove the third silicon oxide film and also remove the silicon nitride film, the second silicon oxide film, and the first silicon oxide film until the silicon nitride film is removed completely; and
- removing by wet etching the pad oxide film, the second silicon oxide film, and the first silicon oxide film until at least the surface of the silicon substrate is exposed. According to a sixth aspect of the present invention, there is provided a method for forming an element isolating region, including the steps of:
- forming a pad oxide film on a surface of a silicon substrate by thermal oxidation and forming a silicon nitride film which covers the pad oxide film and then conducting anisotropic etching sequentially on portions of the silicon nitride film and the pad oxide film which exist on a formation-reserved element isolating region to conduct anisotropic etching using the silicon nitride film as a mask in order to form a trench in the surface of the silicon substrate, thus forming a first silicon oxide film having a film thickness smaller than ½ of a minimum width of the trench throughout on the surface by LPCVD.
- forming by spin coating or LPD a second silicon oxide which covers a surface of the first silicon oxide film to thereby conduct first heat treatment in an oxygen atmosphere, serving also to refine the second silicon oxide film;
- conducting CMP on the second and first silicon oxide films until a surface of the silicon nitride film is exposed;
- forming by spin coating or LPD a third silicon oxide film which covers the silicon nitride film and the first and second silicon oxide films to thereby conduct second heat treatment, serving also to refine the third silicon oxide film;
- conducting such anisotropic etching using an etching gas that an etching rate for the silicon oxide film may be equal to an etching rate for the silicon nitride film to remove the third silicon oxide film and also remove the silicon nitride film, the second silicon oxide film, and the first silicon oxide film so as to leave a residue of the silicon nitride film partially;
- removing the residue of the silicon nitride film by wet etching; and
- removing by wet etching the residue of the third silicon oxide film, the pad oxide film, the second silicon oxide film, and the first silicon oxide film until the surface of the silicon substrate is exposed.
- According to a seventh aspect of the present invention, there is provided a method for forming an element isolating region, including the steps of:
- forming a pad oxide film on a surface of a silicon substrate by thermal oxidation and forming a silicon nitride film which covers the pad oxide film and then conducting anisotropic etching sequentially on portions of the silicon nitride film and the pad oxide film which exist on a formation-reserved element isolating region to conduct anisotropic etching using the silicon nitride film in order to form a trench in the surface of the silicon substrate, thus forming a first silicon oxide film having a film thickness smaller than ½ of a minimum width of the trench throughout on the surface by LPCVD;
- forming by spin coating or LPD a second silicon oxide film which covers a surface of the first silicon oxide film to thereby conduct first heat treatment in an oxygen atmosphere, serving also to refine the second silicon oxide film;
- conducting CMP on the second and first silicon oxide films until a surface of the silicon nitride film is exposed;
- forming by spin coating or LPD a third silicon oxide film which covers surfaces of the silicon nitride film and the first and second silicon oxide films to thereby conduct second heat treatment in an oxygen atmosphere, serving also to refine the third silicon oxide film;
- conducting anisotropic etching using such an etching gas that an etching rate for the silicon oxide film may be higher than an etching rate for the silicon nitride film to remove the third silicon oxide film, thus removing the silicon nitride film, the second silicon oxide film, and the first silicon oxide film partially;
- removing a residue of the silicon nitride film by wet etching; and
- removing by wet etching the pad oxide film, the second silicon oxide film, and the first silicon oxide film until the surface of the silicon substrate is exposed.
- According to a eighth aspect of the present invention, there is provided a method for forming an element isolating region, including the steps of:
- forming a pad oxide film on a surface of a silicon substrate by thermal oxidation and forming a silicon nitride film which covers the pad oxide film and then conducting anisotropic etching sequentially on portions of the silicon nitride film and the pad oxide film which exist on a formation-reserved element isolating region to conduct anisotropic etching using the silicon nitride film as a mask in order to form a trench in the surface of the silicon substrate, thus forming a first silicon oxide film having a film thickness smaller than ½ of a minimum width of the trench throughout on the surface by LPCVD;
- forming by spin coating or LPD a second silicon oxide film which covers a surface of the first silicon oxide film to thereby conduct first heat treatment in an oxygen atmosphere, serving also to refine the second silicon oxide film;
- conducting CMP on the second and first silicon oxide films until a surface of the silicon nitride film is exposed;
- forming by spin coating or LPD a third silicon oxide film which covers surfaces of the silicon nitride film and the first and second silicon oxide films to thereby conduct second heat treatment, serving also to refine the third silicon oxide film;
- conducting such anisotropic etching using an etching gas that an etching rate for the silicon oxide film may be higher than an etching rate for the silicon nitride film to remove the third silicon oxide film and remove the silicon nitride film partially and also remove the second and first silicon oxide films until a surface of the second silicon oxide film and an upper edge surface of the first silicon oxide film is equal to a surface of the pad oxide film in level;
- removing a residue of the silicon nitride film by wet etching; and
- removing by wet etching the third oxide film, the pad oxide film, the second silicon oxide film, and the first silicon oxide film until the surface of the silicon substrate is exposed.
- With the above configurations, the silicon nitride film is used as the mask to form the trenches, on the surface of which is formed the thermal-oxidized film to thereby fill the trenches completely in order to form buried silicon oxide film, which then undergoes CMP using the silicon nitride film as the stopper, after which the organic SOG film or the inorganic SOG film made of silicon hydride sesqui-oxide as the material undergoes spin coating or LPD to form covering silicon oxide film to thereby cover the surface of the above-mentioned buried silicon oxide film, thus effectively repairing the micro-scratch generated in the surface of the buried silicon oxide film during the CMP step.
- Accordingly, when heat treatment is conducted in an oxidation atmosphere for refinement also, a debot can be prevented from occurring even if wet etching is conducted after anisotropic etching conducted on both of the silicon oxide film and the silicon nitride film.
- As a result, the invention makes it possible to easily avoid occurrence of the debot even in presence of a micro-scratch and easily suppress the effective expansion of the element forming region. Also, in a semiconductor device containing MOS transistors, the invention makes it possible to easily suppress an increase in the reverse narrow channel effect, deterioration of electric characteristics, and induction of etch residues of gate electrodes in post-steps.
- The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings in which:
- FIGS. 1A to1F are schematic cross-sectional views for showing element-isolating region forming steps according to a first embodiment of the present invention;
- FIGS. 2A to2E are schematic cross-sectional views for showing element-isolating region forming steps according to a second embodiment of the present invention;
- FIGS. 3A to3E are schematic cross-sectional views for showing element-isolating region forming steps according to a third embodiment of the present invention;
- FIGS. 4A, 4B and4C are schematic cross-sectional views for showing element-isolating region forming steps according to a fourth embodiment of the present invention;
- FIGS. 5A, 5B and5C are schematic cross-sectional views for showing further element-isolating region forming steps according to the fourth embodiment of the present invention;
- FIGS. 6A and 6B are schematic cross-sectional views for showing still further element-isolating region forming steps according to the fourth embodiment of the present invention; and
- FIGS. 7A to7E are schematic cross-sectional views for showing conventional STI forming steps, illustrating its problems.
- Best modes for carrying out the present invention will be described in further detail using various embodiments with reference to the accompanying drawings.
- According to first, second, and third embodiments of the present invention, an STI trench (surface of which is covered by a thermal oxide film) is filled with a silicon oxide film formed by HD-PRCVD accompanied by bias sputtering. Also, according to the fourth embodiment of the present invention, the STI trench (surface of which is covered by a thermal oxide film) is filled with a first silicon oxide film formed by LPCVD and a second silicon oxide film formed by LPD or spin coating.
- FIGS. 1A to1F are schematic cross-sectional views for showing element-isolating region forming steps according to a first embodiment of the present invention;
- The following will describe a method for forming an STI according to the first embodiment with reference to FIGS. 1A to1F.
- First, a
pad oxide film 102 with a film thickness of, for example, about 20 nm is formed on a surface of asilicon substrate 101 by thermal oxidation. Then, asilicon nitride film 103 with a film thickness of, for example, about 200 nm is formed on thepad oxide film 102 by CVD. Thesilicon nitride film 103 and thepad oxide film 102 are sequentially patterned anisotropically on a formation-reserved region of an element isolating region. - Next,
trenches 105 are formed by anisotropic etching using thesilicon nitride film 103 as a mask.Trenches 105 have their minimum width of, for example, about 0.25 μm, a minimum inter-spacing of, for example, about 0.25 μm, and a depth of about 0.3-0.4 μm. This anisotropic etching employs HBr (+O2) or Cl2 (+O2) as its etching gas. - Next, on a surface of
trenches 105 is formed a thermal-oxidizedfilm 107 with a film thickness of up to about 20 nm by thermal oxidation at a temperature of 900-950° C. When the thermal-oxidizedfilm 107 is thus formed, an upper edge of thetrenches 105 is rounded off. Subsequently, a firstsilicon oxide film 111 with a film thickness of, for example, about 600 nm is formed by HD-PECVD (e.g., ECR) accompanied by bias sputtering. This firstsilicon oxide film 111 completely fills the trenches 105 (see FIG. 1A). - Next, CMP is conducted on the first
silicon oxide film 111 using thesilicon nitride film 103 as a stopper, to leave asilicon oxide film 111 a. In this embodiment also, when CMP is conducted, a micro-scratch 115 is generated in a surface of thesilicon oxide film 111 a (see FIG. 1B). - Note here that in this embodiment, it is not preferable to employ a silicon oxide film by use of LPCVD in place of the first
silicon oxide film 111 thus formed. This is because if the silicon oxide film by use of LPCVD has a large film thickness, it has a key-hole shaped void (key-hole void) formed at its trench, which cannot be eliminated by CMP, thus contributing to a variety of troubles. If this silicon oxide film by use of LPCVD has a small film thickness, on the other hand, a portion which fills thetrenches 105 have a recess in this silicon oxide film. By the above-mentioned CMP processing, however, slurry residues in this recess cannot easily be removed, which is not preferably from a viewpoint of reliability. - Next, a second
silicon oxide film 121 a consisting of an organic SOG (Spin-On-Glass) film is formed by spin coating to thereby cover the surface of thesilicon oxide film 111 a including thesilicon nitride film 103. The secondsilicon oxide film 121 a has a film thickness of, for example, about 280 nm and preferably about 0.1-0.4 μm. Since a starting material for forming thesilicon oxide film 121 a is in a liquid state, in contrast to a case of using CVD or PVD such as sputtering, the micro-scratch 115 formed in the surface of thesilicon oxide film 111 a has also part of this secondsilicon oxide film 121 a formed therein (see FIG. 1C). This secondsilicon oxide film 121 a comes in, for example, an organic SOG film made of a material containing, for example, a Si—R (R: alkyl group). - Subsequently, heat treatment is conducted in a dry-O2 atmosphere at a temperature of 900-950° C. to transform the second
silicon oxide film 121 a andsilicon oxide film 111 a into a silicon oxide film 121 aa and silicon oxide film 121 aaa respectively. This heat treatment makes the secondsilicon oxide film 121 a finer and sufficiently dehydrates it and liberates R groups therefrom (see FIG. 1D). It is not preferable to conduct this heat treatment in a steam atmosphere in this embodiment because the surface of thetrenches 105 are also oxidized. Prior to this heat treatment, cure processing may be conducted in a nitrogen atmosphere at a temperature of 500-600° C. in order to remove the R groups from thesilicon oxide film 111 a. - Note here that it is not preferable to employ a typical silica-based inorganic SOG film made of a material containing a Si—OH (silanol) bond, because it encounters drastic volumetric shrinkage during the above-mentioned heat treatment, thus being liable to generate a lot of cracks.
- Next, an etching gas is used which is made up of tetrafluoro-methane (CHF3) with a flow rate of 3.3×10−2 L/min, tetrafluoro-methane (CF4) with a flow rate of 2.7×10−2 L/min, argon (Ar) with a flow rate of 5×10−3 L/min, and oxygen (O2) with a flow rate of 1×10−3 L/min, to conduct anisotropic etching by use of a leaf-type RIE (Reactive Ion Etching) apparatus under conditions of a pressure of 10 Pa and a high-frequency source power of 1000 W (at a frequency of 13.56 MHz). In this anisotropic etching, an etching rate for the silicon oxide film is roughly equal to that for the
silicon nitride film 103. This anisotropic etching is continued until thesilicon nitride film 103 is removed to thus remove the silicon oxide film 121 aa, leaving thesilicon oxide film 111 aa as asilicon oxide film 111 ab. At this point in time, an upper surface of thesilicon oxide film 111 ab roughly agrees with a surface of thepad oxide film 102 in level. In this embodiment, this anisotropic etching is stopped from removing also thepad oxide film 102 in order not to damage by RIE a surface of portions of thesilicon substrate 101 which are reserved as an element forming region (see FIG. 1E). - In this anisotropic etching, an emission spectrum (with a wavelength of 483 nm) of carbon monoxide (CO) generated during the etching of the silicon oxide film is used by a monitor. Also, when an emission amount of the emission spectrum of CO starts to decrease, etching is terminated of the silicon oxide film121 aa and, when it starts to increase again, etching is terminated of the
silicon nitride film 103, thus stopping this anisotropic etching. - Subsequently, the
pad oxide film 102 is removed using a buffered hydrofluoric acid (or diluted hydrofluoric acid) until the surface of thesilicon substrate 101 is exposed. At the same time, the thermal-oxidizedfilm 107 and thesilicon oxide film 111 ab are also removed partially, to thereby provide a thermal-oxidizedfilm 107 a and asilicon oxide film 111 ac respectively. At this point in time, an upper edge of the thermal-oxidizedfilm 107 roughly agrees with an upper surface of thesilicon oxide film 107 a in level. With this, thetrenches 105 are filled by thesilicon oxide film 111 ac with the thermal-oxidizedfilm 107 therebetween, thus completing the STI according to this embodiment (see FIG. 1F). - With the first embodiment, even if the micro-scratch115 has already been formed on the surface of the
silicon oxide film 111 a immediately after CMP, the secondsilicon oxide film 121 a is formed to completely fill a void of the micro-scratch 115, so that the micro-scratch 115 can be considered to have disappeared effectively. When thesilicon oxide film 111 a undergoes anisotropic etching or wet etching to provide thesilicon oxide film 111 ab or thesilicon oxide film 111 ac, the micro-scratch 115 does not expand anisotropically. Accordingly, even if the above-mentioned micro-void is present near a lower edge of the end of thesilicon nitride film 103, occurrence of a debot is suppressed. - As a result, the element isolating region can be easily regulated from expanding effectively. Also, in a semiconductor device having MOS transistors therein, it is possible to easily suppress increases in reverse narrow channel effect, deterioration in electric characteristics, and induction of etch residue of gate electrodes in post-steps.
- FIGS. 2A to2E are schematic cross-sectional views for showing element-isolating region forming steps according to a second embodiment of the present invention;
- The following will describe a method for forming an STI according to the second embodiment with reference to FIGS. 2A to2E.
- First, like in the case of the above-mentioned first embodiment, a
pad oxide film 102 is formed by thermal oxidation on a surface of asilicon substrate 101 and then asilicon nitride film 103 is formed by CVD on a surface of thepad oxide film 102. Portions of thesilicon nitride film 103 and thepad oxide film 102 which exist on a formation-reserved element isolating region are sequentially patterned by anisotropic etching.Trenches 105 are formed by anisotropic etching using thesilicon nitride film 103 as a mask. On a surface of thetrenches 105 is formed a thermal-oxidizedfilm 107. The first silicon oxide film (not shown) having a film thickness of, for example, about 600 nm is formed by HD-PECVD accompanied by bias sputtering. Subsequently, CMP is conducted on the above-mentioned first silicon oxide film using thesilicon nitride film 103 as a stopper to thereby leave the firstsilicon oxide film 111 b. By this CMP processing, a micro-scratch 115 is generated in the surface of the firstsilicon oxide film 111 b. - Next, a second
silicon oxide film 121 b made of an organic SOG film containing silicon hydride sesqui-oxide (HSiO{fraction (3/2)})n (where n is an arbitrary natural number) as a material is formed by spin coating to thereby cover the first surface of thesilicon oxide film 111 b including thesilicon nitride film 103. The secondsilicon oxide film 121 b has preferably a film thickness of about 0.1-0.4 μm. Since a starting material for forming the secondsilicon oxide film 121 b is in a liquid state, the micro-scratch 115 formed in the surface of the firstsilicon oxide film 111 b also has part of the secondsilicon oxide film 121 b formed therein (see FIG. 2A). - Subsequently, heat treatment is conducted in a dry-O2 atmosphere at a temperature of 900-950° C. to thereby transform the second
silicon oxide film 121 b and the firstsilicon oxide film 111 b into a silicon oxide film 121 ba andsilicon oxide film 111 ba respectively. This heat treatment makes the secondsilicon oxide film 121 b finer and sufficiently dehydrates it and liberates R groups therefrom (see FIG. 2B). Prior to this heat treatment, cure processing may be conducted in a nitride atmosphere at a temperature of 500-600° C. in order to remove water contents from asilicon oxide film 121 b beforehand. - In contrast to typical inorganic SOG films made of a material containing silanol bonds, the above-mentioned second
silicon oxide film 121 b encounters little volumetric shrinkage, actually less than thesilicon oxide film 121 a (FIG. 1C) in the above-mentioned first embodiment, and also little crack generation. - Next, such anisotropic etching is conducted that an etching rate for the silicon oxide film and that for the
silicon nitride film 103 used in the above-mentioned first embodiment may be roughly equal to each other. This anisotropic etching is actually conducted not to remove thesilicon nitride film 103 completely, thus leaving asilicon nitride film 103 b and asilicon oxide film 111 bb respectively. An upper surface of thesilicon nitride film 103 b and that of thesilicon oxide film 111 bb roughly agree with each other, with thesilicon nitride film 103 b having a film thickness of, for example, about 10 nm (see FIG. 2C). - Next, wet etching by use of hot phosphoric acid is conducted on the
silicon nitride film 103 b to remove it locally, thus exposing a surface of the pad oxide film 102 (see FIG. 2D). - Subsequently, the
pad oxide film 102 is removed by buffered hydrofluoric acid (or diluted hydrofluoric acid) until a surface of thesilicon substrate 101 is exposed. At a same time, the thermal-oxidizedfilm 107 and thesilicon oxide film 111 bb are also removed partially to thereby provide a thermal-oxidizedfilm 107 b and asilicon oxide film 111 bc respectively. By this etching, it is not difficult to keep a level difference between an upper surface of thesilicon oxide film 111 bc and a surface of thesilicon substrate 101 within ±5 nm. In fact, at this point in time an upper edge of the thermal-oxidizedfilm 107 b has become lower than the upper surface of thesilicon oxide film 111 bc by about 10 nm in level. With this, thetrenches 105 are filled by thesilicon oxide film 111 bc with the thermal-oxidizedfilm 107 b therebetween to thus complete the STI according to the second embodiment of the present invention (see FIG. 2E). - With the second embodiment, in anisotropic etching for etching the silicon nitride film and silicon oxide films roughly at a same etching rate, the
silicon nitride film 103 is not completely removed to thereby leave its residues, thus avoiding thepad oxide film 102 from being subjected to this anisotropic etching. - Accordingly, controllability of a series of etching steps up to removing of the
pad oxide film 102 is more superior in the second embodiment than in the above-mentioned first embodiment. - Also, in the second embodiment, the second
silicon oxide film 121 b is not limited to an inorganic SOG film made of such a material as silicon hydride sesqui-oxide but may be an organic SOG film like in the case of the above-mentioned first embodiment. Similarly, the secondsilicon oxide film 121 b employed in the above-mentioned first embodiment may be an inorganic SOG film made of such a material as silicon hydride sesqui-oxide. - FIGS. 3A to3E are schematic cross-sectional views for showing element-isolating region forming steps according to a third embodiment of the present invention;
- The following will describe a method for forming an STI according to the third embodiment with reference to FIGS. 3A to3E.
- First, like in cases of the above-mentioned first embodiment and second embodiment, a
pad oxide film 102 is formed on a surface of asilicon substrate 101 by thermal oxidation and then asilicon nitride film 103 is formed by CVD on a surface of thepad oxide film 102. Portions of thesilicon nitride film 103 and thepad oxide film 102 which exit on a formation-reserved element isolating region are patterns by anisotropic etching respectively. Anisotropic etching by use of thesilicon nitride film 103 as a mask is conducted to formtrenches 105. On a surface oftrenches 105 is formed a thermal-oxidizedfilm 107. A first silicon oxide film (not shown) having a film thickness of, for example, about 600 nm is formed by HD-PECVD accompanied by bias sputtering. Subsequently, CMP is conducted on the above-mentioned first silicon oxide film using thesilicon nitride film 103 as a stopper to thereby leave a firstsilicon oxide film 111 c. By this CMP processing, the micro-scratch 115 is generated in a surface of the firstsilicon oxide film 111 c. - Next, liquid-phase deposition (LPD) is conducted to form a second
silicon oxide film 121 c to thereby cover a surface of the firstsilicon oxide film 111 c and thesilicon nitride film 103. An solution used in this LPD processing is prepared, as disclosed in Japanese Patent Application Laid-open No. Hei 6-61343, for example by adding 10-50 ml/h of a 0.6 wt % solution of ortho-acetic acid (H3BO3) to 1 L of a 40 wt % solution of hexa-fluoro silicic acid (H2SiF6). The secondsilicon oxide film 121 c has preferably a thickness of about 0.1-0.4 μm. Since the secondsilicon oxide film 121 c is formed in a liquid, the micro-scratch 115 formed in the surface of thesilicon oxide film 111 c has also part of this secondsilicon oxide film 121 c formed therein (see FIG. 3A). - Subsequently, heat treatment is conducted in a dry-O2 atmosphere at a temperature of 900-950° C. to thereby transform the second
silicon oxide film 121 c and thesilicon oxide film 111 c into a silicon oxide film 121 ca and a firstsilicon oxide film 111 ca respectively. This heat treatment makes the secondsilicon oxide film 121 c finer and sufficiently dehydrates it and liberates R groups therefrom (see FIG. 3B). Prior to this heat treatment, cure processing may be conducted in a nitrogen atmosphere at a temperature of 500-600° C. to remove water contents from the secondsilicon oxide film 121 c beforehand. - Next, the silicon oxide film and the silicon nitride film are subjected to such anisotropic etching by use of an etching gas that gives a higher etching rate for the former than that for the
silicon nitride film 103, to remove the silicon oxide film 121 ca completely, thus removing also thesilicon nitride film 103 and the firstsilicon oxide film 111 ca partially. For example, supposing an etching rate ratio is about 2.0, an etching gas consisting of octa-fluoro-cylcobutane (C4F4) with a flow rate of 1.8×10−2 L/min and argon with a flow rate of 0.4 L/min is used for a high-density plasma-etching apparatus (e.g., ECR etching apparatus) under conditions of a pressure of 2.7 Pa, a high-frequency source power of 2000 W (27 MHz) for an upper electrode, and a high-frequency source power of 1200 W (800 kHz) for a lower electrode to thereby conduct the above-mentioned anisotropic etching. This etching is actually conducted to leave asilicon nitride film 103 c with a film thickness of, for example, about 105 nm and asilicon oxide film 111 cb with its high surface higher by, for example, about 10 nm higher than a surface of thepad oxide film 102 in level (see FIG. 3C). - Note here that in the third embodiment, by the above-mentioned anisotropic etching, the
silicon nitride film 103 may be etched until an upper surface of the firstsilicon oxide film 111 ca roughly agrees with the surface of thepad oxide film 102 in level, to leave thesilicon nitride film 103 to a film thickness of about 100 nm. - Next, wet etching by use of hot phosphoric acid is conducted on the
silicon nitride film 103 c to remove it locally until the surface of thepad oxide film 102 is exposed (see FIG. 3D). - Subsequently, the
pad oxide film 102 is removed by buffered hydrofluoric acid (or diluted hydrofluoric acid) until a surface of thesilicon substrate 101 is exposed. At the same time, the thermal-oxidizedfilm 107 and thesilicon oxide film 111 cb are also removed partially to provide a thermal-oxidizedfilm 107 c and asilicon oxide film 111 cc respectively. By this etching also, it is not difficult to hold a level difference between an upper surface of thesilicon oxide film 111 cc and the surface of thesilicon substrate 101 within ±5 nm. An upper edge of the thermal-oxidizedfilm 107 c is roughly lower than the upper surface of thesilicon oxide film 111 cc by about 10 nm in level. Accordingly, thetrenches 105 are filled by thesilicon oxide film 111 cc with the thermal-oxidizedfilm 107 c therebetween, to complete the STI according to the third embodiment (see FIG. 3E). - The third embodiment has same effects as described in the above-mentioned second embodiment.
- Also, in the above-mentioned third embodiment, the second
silicon oxide film 121 c is not limited to one by LPD but may be an organic SOG film, an inorganic SOG film made of such a material as silicon hydride sesqui-oxide like in the case of the above-mentioned first embodiment and second embodiment. Likewise, the secondsilicon oxide film 121 c in the above-mentioned first embodiment and second embodiment may be formed by LPD. - FIGS. 4A to6B are schematic cross-sectional views for showing element-isolating region forming steps according to a fourth embodiment of the present invention;
- The following will describe a method for forming an STI according to the fourth embodiment with reference to FIGS. 4A to6B.
- First, a
pad oxide film 202 with a film thickness of, for example, about 20 nm is formed on asilicon substrate 201 by thermal oxidation. Asilicon nitride film 203 with a film thickness of, for example, about 200 nm is formed by CVD on a surface of thepad oxide film 202. Portions of thesilicon nitride film 203 and thepad oxide film 202 which exist on a formation-reserved element isolating region are sequentially patterned by anisotropic etching. - Next, anisotropic etching is conducted using the
silicon nitride film 203 to thereby formtrenches 205. Thetrenches 205 have a minimum width of, for example, about 0.25 μm, a minimum inter-spacing of, for example, about 0.25 μm, and a depth of about 0.3-0.4 μm. An etching gas used in this anisotropic etching is HBr (+O2) or Cl2 (+O2). - Next, on a surface of the
trenches 205 is formed a thermal-oxidizedfilm 207 with a film thickness of about up to 20 nm by thermal oxidation at a temperature of 900-950° C. The thermal-oxidizedfilm 207 is thus formed to round off an upper edge of thetrenches 205. Subsequently, a firstsilicon oxide film 212 having a film thickness of, for example, about 100 nm is formed by LPCVD. At this point in time, in thetrenches 205, a recess (not key hole void) has been formed in the firstsilicon oxide film 212. To fill thetrenches 205 only with the firstsilicon oxide film 212 formed by CVD, the firstsilicon oxide film 212 must have a film thickness not larger than ½ (e.g., 125 nm) of a minimum width of thetrenches 205 because thetrenches 205 have a key hole void formed therein due to the firstsilicon oxide film 212. - Next, a second
silicon oxide film 221 is formed by spin-coating an inorganic SOG film made of, for example, a silicon hydride sesqui-oxide as a material. To completely fill the recess in the firstsilicon oxide film 212 formed in thetrenches 205, the secondsilicon oxide film 221 must have a film thickness of about 550-700 nm (see FIG. 4A). Note here that in this embodiment, the secondsilicon oxide film 221 is not limited to the above-mentioned inorganic SOG film but may be an organic SOG film or even a silicon oxide film formed by LPD. - Subsequently, first heat treatment is conducted in a dry-O2 atmosphere at a temperature of 900-950° C. to thereby transform the second
silicon oxide film 221 and firstsilicon oxide film 212 intosilicon oxide film 221 a andsilicon oxide film 212 a respectively. This heat treatment makes the secondsilicon oxide film 221 finer and sufficiently dehydrates it (see FIG. 4B). Prior to this heat treatment, to remove water contents from the secondsilicon oxide film 221, cure processing may be conducted in a nitrogen atmosphere at a temperature of 500-600° C. - Next, CPM is conducted on the
silicon oxide film 221 a silicon oxide film and 212 a using thesilicon nitride film 203 as a stopper to thereby leave asilicon oxide film 221 b and asilicon oxide film 212 b respectively. In this embodiment also, when CMP is thus conducted, a micro-scratch 215 is generated in a surface of thesilicon oxide film 221 b (or thesilicon oxide film 212 b) (see FIG. 4C). - Next, an inorganic SOG film made of, for example, silicon hydride sesqui-oxide as a material is spin-coated to thereby form a third
silicon oxide film 222. The thirdsilicon oxide film 222 has preferably have a film thickness of about 0.1-0.4 μm. The surface of thesilicon oxide film 221 b and an upper edge surface of thesilicon oxide film 212 b are covered by the thirdsilicon oxide film 222. Like in a case of the above-mentioned first embodiment, a starting material of silicon oxide is also in a liquid state, so that a void due to the micro-scratch 215 is also filled with part of the third silicon oxide film 222 (see FIG. 5A). Note here that as the above-mentioned secondsilicon oxide film 221 in this embodiment, the thirdsilicon oxide film 222 in this embodiment is not limited to the above-mentioned SOG film but may be an organic SOG film or even a silicon oxide film formed by LPD. - Subsequently, second heat treatment is conducted in a dry-O2 atmosphere at a temperature of 900-950° C. to thereby transform the third
silicon oxide film 222 into asilicon oxide film 222 a. This heat treatment makes the thirdsilicon oxide film 222 finer and sufficiently dehydrates it (see FIG. 5B). Prior to this second heat treatment, in order to remove water contents from the thirdsilicon oxide film 222, cure processing may be conducted in a nitrogen atmosphere at a temperature of 500-600° C. - Next, anisotropic etching similar to, for example, that in the third embodiment is conducted to completely remove the
silicon oxide film 222 a, thus leaving asilicon nitride film 203 a with a film thickness of, for example, about 105 nm and asilicon oxide film 221 c and asilicon oxide film 212 c having their respective upper surface and upper edge surface higher than the surface by, for example, about 10 nm (see FIG. 5C). - Note here that in this embodiment also, the above-mentioned anisotropic etching may be conducted to etch the
silicon nitride film 203 until the upper surface of the second silicon oxide film 221 (and the upper edge surface of the first silicon oxide film 212) may roughly agree with the surface of thepad oxide film 202 in level. Further, this anisotropic etching may be conducted like in a case of the above-mentioned first embodiment or second embodiment. - Next, the
silicon nitride film 203 a is subjected to wet etching using hot phosphoric acid and locally removed to thereby expose a surface of the pad oxide film 202 (see FIG. 6A). - Subsequently, buffered hydrofluoric acid (or diluted hydrofluoric acid) is used to remove the
pad oxide film 202 until a surface of thesilicon substrate 201 is exposed. At a same time, the thermal-oxidizedfilm 207, thesilicon oxide film 212 c, and thesilicon oxide film 221 c are also removed partially to provide a thermal-oxidizedfilm 207 a, asilicon oxide film 212 d, and asilicon oxide film 221 d respectively. By this etching also, it is not difficult to hold a level difference between an upper end surface of thesilicon oxide film 212 d and an upper surface of thesilicon oxide film 221 d and a surface of thesilicon substrate 201 within 35 5 nm. An upper edge of the thermal-oxidizedfilm 207 a is lower than the upper surface of thesilicon oxide film 221 d (and the upper edge surface of thesilicon oxide film 212 d) by about 10 nm. With this, thetrenches 205 are filled by thesilicon oxide film 212 d and thesilicon oxide film 221 d with the thermal-oxidizedfilm 207 a to thereby complete the STI according to this embodiment (see FIG. 6B). - The fourth embodiment has same effects as described in the above-mentioned third embodiment. Also, the above-mentioned anisotropic etching thus selectively conducted on the silicon oxide film and the silicon nitride film permits the fourth embodiment to have effects equivalent to those of the above-mentioned first or second embodiment.
- It is apparent that the present invention is not limited to the above embodiments but may be changed and modified without departing from the scope and spirit of the invention.
Claims (22)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000078773A JP3492279B2 (en) | 2000-03-21 | 2000-03-21 | Method of forming element isolation region |
JP2000-078773 | 2000-03-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010026994A1 true US20010026994A1 (en) | 2001-10-04 |
US6417073B2 US6417073B2 (en) | 2002-07-09 |
Family
ID=18596138
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/812,876 Expired - Fee Related US6417073B2 (en) | 2000-03-21 | 2001-03-20 | Method for forming element isolating region |
Country Status (6)
Country | Link |
---|---|
US (1) | US6417073B2 (en) |
EP (1) | EP1137057A2 (en) |
JP (1) | JP3492279B2 (en) |
KR (1) | KR100399255B1 (en) |
CN (1) | CN1314706A (en) |
TW (1) | TW479320B (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040266127A1 (en) * | 2003-06-30 | 2004-12-30 | Hynix Semiconductor Inc. | Method for manufacturing alignment mark of semiconductor device using STI process |
US20060166463A1 (en) * | 2005-01-21 | 2006-07-27 | Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung, E.V. | Method of producing a device with a movable portion |
US20060258267A1 (en) * | 2003-08-27 | 2006-11-16 | Takashi Ito | Polishing composition and polishing method using same |
US20090309194A1 (en) * | 2008-06-12 | 2009-12-17 | Sanyo Electric Co., Ltd. | Mesa type semiconductor device and maufacturing method thereof |
US20090309193A1 (en) * | 2008-06-12 | 2009-12-17 | Sanyo Electric Co., Ltd. | Mesa type semiconductor device and manufacturing method thereof |
US8993398B1 (en) * | 2008-02-19 | 2015-03-31 | Marvell International Ltd. | Method for creating ultra-high-density holes and metallization |
US20150206794A1 (en) * | 2014-01-17 | 2015-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for Removing Micro Scratches In Chemical Mechanical Polishing Processes |
US9748111B2 (en) * | 2016-02-01 | 2017-08-29 | United Microelectronics Corp. | Method of fabricating semiconductor structure using planarization process and cleaning process |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6562691B2 (en) * | 2001-03-06 | 2003-05-13 | Macronix International Co., Ltd. | Method for forming protrusive alignment-mark |
US6737333B2 (en) * | 2001-07-03 | 2004-05-18 | Texas Instruments Incorporated | Semiconductor device isolation structure and method of forming |
JP2003031650A (en) * | 2001-07-13 | 2003-01-31 | Toshiba Corp | Method for manufacturing semiconductor device |
JP3418386B2 (en) * | 2001-08-16 | 2003-06-23 | 沖電気工業株式会社 | Method for manufacturing semiconductor device |
US6798038B2 (en) * | 2001-09-20 | 2004-09-28 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device with filling insulating film into trench |
KR20030054672A (en) * | 2001-12-26 | 2003-07-02 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
KR100426487B1 (en) * | 2001-12-28 | 2004-04-14 | 주식회사 하이닉스반도체 | Method of forming a floating gate in flash memory device |
KR20030080311A (en) * | 2002-04-08 | 2003-10-17 | 아남반도체 주식회사 | Method for protecting scratch defect of semiconductor device |
US20090069090A1 (en) * | 2006-11-10 | 2009-03-12 | Igt | Automated system for facilitating management of casino game table player rating information |
JP2004152851A (en) * | 2002-10-29 | 2004-05-27 | Oki Electric Ind Co Ltd | Method of manufacturing semiconductor device |
KR100826791B1 (en) * | 2002-12-05 | 2008-04-30 | 동부일렉트로닉스 주식회사 | Fabrication method of semiconductor device |
US6878644B2 (en) * | 2003-05-06 | 2005-04-12 | Applied Materials, Inc. | Multistep cure technique for spin-on-glass films |
US6693050B1 (en) | 2003-05-06 | 2004-02-17 | Applied Materials Inc. | Gapfill process using a combination of spin-on-glass deposition and chemical vapor deposition techniques |
CN100352034C (en) * | 2003-11-25 | 2007-11-28 | 上海华虹(集团)有限公司 | A method for controlling remaining silicon nitride thickness stability in STI CMP technique |
EP1700344B1 (en) * | 2003-12-24 | 2016-03-02 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor light emitting device and lighting module |
JP2005332885A (en) * | 2004-05-18 | 2005-12-02 | Toshiba Corp | Nonvolatile semiconductor memory device and its manufacturing method |
CN100375463C (en) * | 2004-07-02 | 2008-03-12 | 中国科学院计算技术研究所 | Method for realizing longest prifix address route search using sectioned compressed list |
JP2006108423A (en) | 2004-10-06 | 2006-04-20 | Oki Electric Ind Co Ltd | Manufacturing method of isolation structure |
DE102005002675B4 (en) * | 2005-01-20 | 2007-02-22 | Infineon Technologies Ag | Method for producing a planar spin-on layer on a semiconductor structure |
JP4237152B2 (en) | 2005-03-04 | 2009-03-11 | エルピーダメモリ株式会社 | Manufacturing method of semiconductor device |
US7393789B2 (en) * | 2005-09-01 | 2008-07-01 | Micron Technology, Inc. | Protective coating for planarization |
US7569875B2 (en) | 2006-03-14 | 2009-08-04 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Semiconductor device and a method for producing the same |
KR100757335B1 (en) * | 2006-10-18 | 2007-09-11 | 삼성전자주식회사 | Non-volatile memory device and method of manufacturing the same |
KR100894771B1 (en) * | 2006-10-31 | 2009-04-24 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory device |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US7892942B2 (en) * | 2007-07-09 | 2011-02-22 | Micron Technology Inc. | Methods of forming semiconductor constructions, and methods of forming isolation regions |
CN102082088B (en) * | 2009-11-30 | 2012-04-18 | 上海华虹Nec电子有限公司 | Method for sharing SL mask plate in products of DCMP (direct chemically mechanical polishing) process |
KR101053647B1 (en) * | 2009-12-29 | 2011-08-02 | 주식회사 하이닉스반도체 | Semiconductor device manufacturing method |
JP5556490B2 (en) * | 2010-08-06 | 2014-07-23 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
CN102386084B (en) * | 2010-09-01 | 2014-01-08 | 中芯国际集成电路制造(上海)有限公司 | Method for planarizing surface of wafer |
CN102569161B (en) * | 2010-12-22 | 2014-06-04 | 无锡华润上华半导体有限公司 | Semiconductor device manufacturing method |
CN102214597B (en) * | 2011-05-27 | 2015-07-29 | 上海华虹宏力半导体制造有限公司 | Fleet plough groove isolation structure and processing method thereof and method, semi-conductor device manufacturing method |
JP5977002B2 (en) * | 2011-08-25 | 2016-08-24 | 東京エレクトロン株式会社 | Trench filling method and semiconductor integrated circuit device manufacturing method |
CN104716035A (en) * | 2013-12-12 | 2015-06-17 | 中芯国际集成电路制造(上海)有限公司 | Chemical mechanical polishing method |
FR3051973B1 (en) | 2016-05-24 | 2018-10-19 | X-Fab France | PROCESS FOR FORMING TRANSISTORS PDSOI AND FDSOI ON THE SAME SUBSTRATE |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3109549B2 (en) | 1992-08-04 | 2000-11-20 | 日本電気株式会社 | Method for manufacturing semiconductor device |
US5872043A (en) * | 1996-07-25 | 1999-02-16 | Industrial Technology Research Institute | Method of planarizing wafers with shallow trench isolation |
US5728621A (en) * | 1997-04-28 | 1998-03-17 | Chartered Semiconductor Manufacturing Pte Ltd | Method for shallow trench isolation |
JPH11135613A (en) * | 1997-10-29 | 1999-05-21 | Hitachi Ltd | Manufacture of semiconductor device |
TW393720B (en) * | 1998-05-21 | 2000-06-11 | United Microelectronics Corp | Manufacturing method of a shallow trench isolation structure |
TW374947B (en) * | 1998-06-06 | 1999-11-21 | United Microelectronics Corp | Shallow trench isolation structure and the manufacturing method |
TW379409B (en) * | 1998-07-06 | 2000-01-11 | United Microelectronics Corp | Manufacturing method of shallow trench isolation structure |
US5960299A (en) * | 1998-10-28 | 1999-09-28 | United Microelectronics Corp. | Method of fabricating a shallow-trench isolation structure in integrated circuit |
JP2000294627A (en) * | 1999-04-09 | 2000-10-20 | Seiko Epson Corp | Manufacture of semiconductor device |
-
2000
- 2000-03-21 JP JP2000078773A patent/JP3492279B2/en not_active Expired - Fee Related
-
2001
- 2001-03-19 TW TW090106346A patent/TW479320B/en not_active IP Right Cessation
- 2001-03-20 US US09/812,876 patent/US6417073B2/en not_active Expired - Fee Related
- 2001-03-20 EP EP01250099A patent/EP1137057A2/en not_active Withdrawn
- 2001-03-20 KR KR10-2001-0014351A patent/KR100399255B1/en not_active IP Right Cessation
- 2001-03-21 CN CN01109191A patent/CN1314706A/en active Pending
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040266127A1 (en) * | 2003-06-30 | 2004-12-30 | Hynix Semiconductor Inc. | Method for manufacturing alignment mark of semiconductor device using STI process |
US6958280B2 (en) * | 2003-06-30 | 2005-10-25 | Hynix Semiconductor Inc. | Method for manufacturing alignment mark of semiconductor device using STI process |
US20060258267A1 (en) * | 2003-08-27 | 2006-11-16 | Takashi Ito | Polishing composition and polishing method using same |
US20060166463A1 (en) * | 2005-01-21 | 2006-07-27 | Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung, E.V. | Method of producing a device with a movable portion |
US7396740B2 (en) | 2005-01-21 | 2008-07-08 | Frauhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. | Method of producing a device with a movable portion |
US8993398B1 (en) * | 2008-02-19 | 2015-03-31 | Marvell International Ltd. | Method for creating ultra-high-density holes and metallization |
US20090309194A1 (en) * | 2008-06-12 | 2009-12-17 | Sanyo Electric Co., Ltd. | Mesa type semiconductor device and maufacturing method thereof |
US20090309193A1 (en) * | 2008-06-12 | 2009-12-17 | Sanyo Electric Co., Ltd. | Mesa type semiconductor device and manufacturing method thereof |
US8227901B2 (en) | 2008-06-12 | 2012-07-24 | Sanyo Semiconductor Co., Ltd. | Mesa type semiconductor device and manufacturing method thereof |
US8319317B2 (en) * | 2008-06-12 | 2012-11-27 | Sanyo Semiconductor Co., Ltd. | Mesa type semiconductor device and manufacturing method thereof |
US20150206794A1 (en) * | 2014-01-17 | 2015-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for Removing Micro Scratches In Chemical Mechanical Polishing Processes |
US9748111B2 (en) * | 2016-02-01 | 2017-08-29 | United Microelectronics Corp. | Method of fabricating semiconductor structure using planarization process and cleaning process |
Also Published As
Publication number | Publication date |
---|---|
JP3492279B2 (en) | 2004-02-03 |
JP2001267411A (en) | 2001-09-28 |
US6417073B2 (en) | 2002-07-09 |
KR100399255B1 (en) | 2003-09-26 |
EP1137057A2 (en) | 2001-09-26 |
CN1314706A (en) | 2001-09-26 |
TW479320B (en) | 2002-03-11 |
KR20010092398A (en) | 2001-10-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6417073B2 (en) | Method for forming element isolating region | |
JP3178412B2 (en) | Method of forming trench isolation structure | |
US5989977A (en) | Shallow trench isolation process | |
KR0151051B1 (en) | Method of forming insulation film for semiconductor device | |
US6468853B1 (en) | Method of fabricating a shallow trench isolation structure with reduced local oxide recess near corner | |
US6372605B1 (en) | Additional etching to decrease polishing time for shallow-trench isolation in semiconductor processing | |
US6258692B1 (en) | Method forming shallow trench isolation | |
US5858858A (en) | Annealing methods for forming isolation trenches | |
JP2006156471A (en) | Semiconductor device and its manufacturing method | |
US6015757A (en) | Method of oxide etching with high selectivity to silicon nitride by using polysilicon layer | |
US5554560A (en) | Method for forming a planar field oxide (fox) on substrates for integrated circuit | |
KR100251280B1 (en) | Sti method | |
US6475875B1 (en) | Shallow trench isolation elevation uniformity via insertion of a polysilicon etch layer | |
US20080081433A1 (en) | Method for Forming a Shallow Trench Isolation Structure | |
US7410873B2 (en) | Method of manufacturing a semiconductor device | |
KR19990006860A (en) | Manufacturing Method of Semiconductor Device | |
US6355539B1 (en) | Method for forming shallow trench isolation | |
US6716718B2 (en) | Method of producing a semiconductor device | |
US6180492B1 (en) | Method of forming a liner for shallow trench isolation | |
US6066543A (en) | Method of manufacturing a gap filling for shallow trench isolation | |
US20050054204A1 (en) | Method of rounding top corner of trench | |
US6303467B1 (en) | Method for manufacturing trench isolation | |
US6368973B1 (en) | Method of manufacturing a shallow trench isolation structure | |
KR100200751B1 (en) | Isolation method for a semiconductor device | |
KR100559042B1 (en) | Method of shallow trench isolation film in a semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: NEC CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WATANABE, DAISUKE;REEL/FRAME:011673/0626 Effective date: 20010305 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: NEC ELECTRONICS CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC CORPORATION;REEL/FRAME:013774/0295 Effective date: 20021101 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: ELPIDA MEMORY, INC., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC ELECTRONICS CORPORATION;REEL/FRAME:020762/0477 Effective date: 20080321 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20100709 |