KR100559042B1 - Shallow Trench Isolation Method for Semiconductor Devices - Google Patents
Shallow Trench Isolation Method for Semiconductor Devices Download PDFInfo
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- KR100559042B1 KR100559042B1 KR1019990043178A KR19990043178A KR100559042B1 KR 100559042 B1 KR100559042 B1 KR 100559042B1 KR 1019990043178 A KR1019990043178 A KR 1019990043178A KR 19990043178 A KR19990043178 A KR 19990043178A KR 100559042 B1 KR100559042 B1 KR 100559042B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000002955 isolation Methods 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 45
- 238000005530 etching Methods 0.000 claims abstract description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 22
- 230000001590 oxidative effect Effects 0.000 claims description 9
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- 239000011737 fluorine Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052801 chlorine Inorganic materials 0.000 claims description 2
- 239000000460 chlorine Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 abstract description 10
- 238000009413 insulation Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 abstract 3
- 239000010409 thin film Substances 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000005498 polishing Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000003912 environmental pollution Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
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Abstract
본 발명은 반도체 소자의 쉘로우 트렌치 소자분리막 형성 방법에 관한 것으로, 트렌치 형성을 위한 식각 마스크로 질화막을 이용하는 경우, 질화막 자체의 두께로 인해 매립해야 할 실제 트렌치의 에스펙트 비(aspect ratio)가 증가하여, 트렌치가 완전히 매립되지 않고 보이드(void)가 발생하는 문제점을 해결하기 위하여, 트렌치 형성을 위한 식각 마스크로 얇은 두께의 산화막을 이용하고, 상기 산화막을 제거한 후 트렌치를 매립하므로써, 트렌치의 에스펙트 비가 감소되어 보이드의 발생을 방지할 수 있고 소자간 절연 특성이 개선된 반도체 소자의 쉘로우 트렌치 소자분리막 형성 방법이 개시된다.The present invention relates to a method for forming a shallow trench isolation layer of a semiconductor device. When using a nitride film as an etching mask for forming a trench, an aspect ratio of an actual trench to be filled is increased due to the thickness of the nitride film itself. In order to solve the problem that the trench is not completely buried and voids are generated, a thin film oxide is used as an etching mask for forming the trench, and the aspect ratio of the trench is removed by filling the trench after removing the oxide film. Disclosed is a method of forming a shallow trench isolation layer of a semiconductor device, which can reduce the occurrence of voids and improve the inter-device insulation property.
STI, 산화막, 비정질 실리콘층STI, Oxide, Amorphous Silicon Layer
Description
도 1a 내지 1f는 본 발명에 따른 반도체 소자의 쉘로우 트렌치 소자분리막 형성 방법을 설명하기 위해 순차적으로 도시한 소자의 단면도.1A to 1F are cross-sectional views of devices sequentially shown to explain a method of forming a shallow trench isolation layer in a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
11 : 반도체 기판 12 : 산화막11
13 : 포토레지스트막 14 ; 트렌치13:
15 : 비정질 실리콘층 16 : 트렌치 매립 산화막15
17 : 산화된 비정질 실리콘층17: oxidized amorphous silicon layer
본 발명은 반도체 소자의 쉘로우 트렌치 소자분리막(Shallow Trench Isolation; STI) 형성 방법에 관한 것으로, 특히 트렌치 형성시 식각 마스크로 질화막을 이용하는 대신 산화막을 이용하므로써, 매립하고자 하는 전체 트렌치의 에스펙트 비(aspect ratio)를 줄여 보이드(void)가 없는 트렌치를 형성할 수 있는 반도체 소자의 쉘로우 트렌치 소자분리막 항성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a shallow trench isolation layer (STI) in a semiconductor device, and in particular, an aspect ratio of an entire trench to be buried by using an oxide film instead of using a nitride film as an etching mask when forming a trench. The present invention relates to a shallow trench isolation layer staring method of a semiconductor device capable of forming a void-free trench by reducing a ratio.
일반적인 쉘로우 트렌치 소자분리막 형성 방법은 다음과 같다.A general shallow trench isolation layer formation method is as follows.
먼저, 반도체 기판 상부에 패드 산화막 및 패드 질화막을 순차적으로 형성한 후 ISO 마스크를 이용한 식각 공정으로 패드 질화막 및 패드 산화막을 식각한 다음, 트렌치 식각 공정으로 실리콘 기판을 식각하여 트렌치를 형성한다. 이후, 열산화 공정을 실시하여 트렌치가 형성된 실리콘 기판 저부 및 측부에 사이드월 실리콘 산화막을 형성한다. 다음에, 전체 구조 상부에 트렌치 매립 산화막을 형성하고 화학적 기계적 연마(CMP) 공정으로 평탄화한 후 패드 질화막을 제거하므로써 소자분리막이 형성되게 된다.First, after the pad oxide film and the pad nitride film are sequentially formed on the semiconductor substrate, the pad nitride film and the pad oxide film are etched by an etching process using an ISO mask, and then a trench is formed by etching the silicon substrate by a trench etching process. Thereafter, a thermal oxidation process is performed to form a sidewall silicon oxide film on the bottom and side of the silicon substrate on which the trench is formed. Next, a trench isolation oxide film is formed over the entire structure, and the device isolation film is formed by removing the pad nitride film after planarization by chemical mechanical polishing (CMP) process.
이와 같은 쉘로우 트렌치 소자분리막 형성 방법에서는 액티브 영역 상에 형성되어 식각 마스크로 사용되는 패드 질화막이 두껍게 형성되기 때문에, 트렌치 형성 후 매립해야 하는 전체 트렌치의 에스펙트 비(aspect ratio)가 증가하게 된다. 이에 따라, 트렌치 매립 산화막 형성시 갭 매립이 완전히 되지 않고 보이드가 발생하게 되어, 소자간의 절연이 제대로 되지 않는 문제점이 있다.In such a shallow trench isolation layer formation method, since a pad nitride film formed on the active region and used as an etch mask is formed thick, the aspect ratio of the entire trench to be filled after trench formation is increased. Accordingly, when the trench buried oxide film is formed, gap filling is not completed and voids are generated, and insulation between devices is not properly performed.
따라서, 본 발명은 트렌치 형성시 식각 마스크로 질화막을 사용하는 대신 산 화막을 적용하므로써, 매립하고자 하는 전체 트렌치의 에스펙트 비를 감소시켜 보이드가 발생하지 않는 반도체 소자의 쉘로우 트렌치 소자분리막 형성 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention provides a shallow trench isolation layer formation method of a semiconductor device in which voids are not generated by reducing the aspect ratio of the entire trench to be filled by applying an oxide film instead of using a nitride film as an etching mask when forming the trench. Its purpose is to.
상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 쉘로우 트렌치 소자분리막 형성 방법은 반도체 기판 상부에 산화막을 형성한 후 상기 산화막의 소정 영역을 식각하여 산화막 패턴을 형성하는 단계; 상기 산화막 패턴을 식각 마스크로 하여 상기 반도체 기판을 식각하므로써 트렌치를 형성하는 단계; 상기 산화막을 제거한 후 상기 반도체 기판을 산화시키는 단계; 전체 구조 상부에 비정질 실리콘층을 형성하고 상기 트렌치가 매립되도록 트렌치 매립 산화막을 형성하는 단계; 상기 비정질 실리콘층이 노출되며, 상기 트렌치 내부에만 트렌치 매립 산화막이 잔류되도록 하는 단계; 및 상기 비정질 실리콘층을 산화시키는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an embodiment of the present disclosure, a method of forming a shallow trench device isolation layer of a semiconductor device may include forming an oxide layer on an upper surface of a semiconductor substrate and etching a predetermined region of the oxide layer to form an oxide layer pattern; Forming a trench by etching the semiconductor substrate using the oxide pattern as an etching mask; Oxidizing the semiconductor substrate after removing the oxide film; Forming an amorphous silicon layer over the entire structure and forming a trench buried oxide film to fill the trench; Exposing the amorphous silicon layer and leaving a trench buried oxide film only inside the trench; And oxidizing the amorphous silicon layer.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1a 내지 1f는 본 발명에 따른 반도체 소자의 쉘로우 트렌치 소자분리막 형성 방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.1A to 1F are cross-sectional views of devices sequentially illustrated to explain a method of forming a shallow trench isolation layer in a semiconductor device according to the present invention.
도 1a에 도시된 바와 같이, 반도체 기판(11) 상에 산화막(12)을 형성하고 포토레지스트막(13)을 형성한 후 ISO 마스크 작업으로 포토레지스트막(13)을 패터닝한다. 여기에서, 산화막(12)은 반도체 기판(11) 산화하여 형성하거나, 반도체 기판(11)을 산화한 후 산화막을 증착하므로써 형성하며, 300 내지 2000Å의 두께를 갖도록 한다.As shown in FIG. 1A, the
도 1b에 도시된 바와 같이, 패터닝된 포토레지스트막(13)을 마스크로 이용하여 산화막(12)을 식각하여 트렌치가 형성될 반도체 기판(11)을 노출시킨다. 이때 산화막(12)은 불소계 가스를 이용하여 식각한다.As shown in FIG. 1B, the
도 1c에 도시된 바와 같이, 포토레지스트막(13)을 제거하지 않은 상태에서 노출된 반도체 기판(11)을 식각하여 트렌치(14)를 형성한다. 트렌치 식각 공정은 불소계 가스 또는 염소계 가스를 이용하여 실시하며, 트렌치 저부는 라운딩진 형태로 형성되게 된다.As illustrated in FIG. 1C, the
도 1d는 포토레지스트막(13) 및 산화막(12)을 모두 제거한 후, 반도체 기판(11)을 산화시켜 얇은 산화막(도시하지 않음)을 형성하고, 전체 구조 상에 비정질 실리콘층(15)을 형성한 다음, 화학기상증착(CVD) 방법으로 트렌치 매립 산화막(16)을 형성한 상태를 나타낸다. 여기에서 산화막(12)은 습식 식각 공정으로 제거하며, 습식 식각 공정시에는 HF 또는 BOE를 이용한다. 또한, 산화 공정은 900 내지 1200℃의 온도에서 실시하며, 이로 인해 성장된 산화막(도시하지 않음)은 50 내지 300Å의 두께를 갖도록 한다.In FIG. 1D, after removing both the
도 1e는 화학적기계적 연마(CMP) 공정을 실시하여 트렌치 내부에만 화학기상증착 산화막(16)이 잔류되도록 한 상태는 나타낸다. 이때의 CMP 공정시 반도체 기판(11) 상에 형성된 비정질 실리콘층(15)이 연마 베리어막으로 작용하게 된다.FIG. 1E shows a state in which the chemical vapor
도 1f는 열처리 공정을 실시하여 반도체 기판(11) 상의 노출된 비정질 실리콘층(15)을 산화시켜 산화된 비정질 실리콘층(17)으로 변화시키고, 이에 의해 쉘로 우 트렌치 소자분리막 형성 공정이 완료된 상태를 나타낸다. 여기에서, 열처리 공정은 800 내지 1200℃의 온도에서 실시한다.1F illustrates a state in which the exposed
이와 같은 쉘로우 트렌치 소자분리막 형성 방법은 트렌치 형성시의 식각 마스크로 얇은 두께를 갖는 산화막을 이용하며, 이 산화막을 제거한 다음 트렌치 매립 공정을 실시하기 때문에 매립하고자 하는 트렌치의 에스펙트 비를 감소시킬 수 있다. 따라서, 보이드가 발생되지 않고 절연특성이 우수한 쉘로우 트렌치 소자분리막을 형성할 수 있게 된다.Such a shallow trench isolation layer formation method uses an oxide film having a thin thickness as an etch mask for forming a trench, and removes the oxide layer and then performs a trench filling process, thereby reducing the aspect ratio of the trench to be buried. . Therefore, it is possible to form a shallow trench isolation layer without generating voids and having excellent insulation characteristics.
상술한 바와 같이 본 발명에 의하면 트렌치 형성을 위한 식각 마스크로 산화막을 이용하고, 트렌치를 형성하기 전 이 산화막을 제거하기 때문에 보이드가 없는 쉘로우 트렌치 소자분리막을 형성할 수 있다. 또한, 트렌치 매립 후의 연마 공정시 연마 베리어층으로 질화막이 아닌 비정질 실리콘층을 적용하기 때문에, 질화막 제거시 필요한 인산 화학물질을 사용하지 않아도 되므로 환경오염 측면에서 유리한 청정 프로세스를 진행할 수 있는 효과가 있다.As described above, according to the present invention, since the oxide film is used as an etching mask for forming the trench and the oxide film is removed before the trench is formed, a shallow trench isolation device without voids can be formed. In addition, since the amorphous barrier layer, not the nitride layer, is applied to the polishing barrier layer in the polishing process after the trench filling, the phosphoric acid chemicals required for removing the nitride layer do not need to be used, and thus, an advantageous clean process may be performed in terms of environmental pollution.
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| US4666556A (en) * | 1986-05-12 | 1987-05-19 | International Business Machines Corporation | Trench sidewall isolation by polysilicon oxidation |
| KR970053432A (en) * | 1995-12-26 | 1997-07-31 | 김광호 | Device Separation Method of Semiconductor Device |
| KR19980063291A (en) * | 1996-12-17 | 1998-10-07 | 윤종용 | Trench device isolation |
| KR19990023196A (en) * | 1997-08-07 | 1999-03-25 | 포만 제프리 엘 | Trench insulating structure forming method and semiconductor device and manufacturing method thereof |
| KR19990055199A (en) * | 1997-12-27 | 1999-07-15 | 김영환 | Method of forming device isolation film in semiconductor device |
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| US4666556A (en) * | 1986-05-12 | 1987-05-19 | International Business Machines Corporation | Trench sidewall isolation by polysilicon oxidation |
| KR970053432A (en) * | 1995-12-26 | 1997-07-31 | 김광호 | Device Separation Method of Semiconductor Device |
| KR19980063291A (en) * | 1996-12-17 | 1998-10-07 | 윤종용 | Trench device isolation |
| KR19990023196A (en) * | 1997-08-07 | 1999-03-25 | 포만 제프리 엘 | Trench insulating structure forming method and semiconductor device and manufacturing method thereof |
| KR19990055199A (en) * | 1997-12-27 | 1999-07-15 | 김영환 | Method of forming device isolation film in semiconductor device |
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