US20010022738A1 - Controlling a sense amplifier - Google Patents
Controlling a sense amplifier Download PDFInfo
- Publication number
- US20010022738A1 US20010022738A1 US09/749,599 US74959900A US2001022738A1 US 20010022738 A1 US20010022738 A1 US 20010022738A1 US 74959900 A US74959900 A US 74959900A US 2001022738 A1 US2001022738 A1 US 2001022738A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
Definitions
- the inventions claimed herein relate in general to semiconductor memory devices. More specifically, the claimed inventions relate to circuit arrangements for driving a sense amplifier for use with semiconductor memory devices.
- a sense amplifier is caused to achieve a high sensitivity by increasing a voltage difference between a data I/O line and a complementary data I/O line.
- data read out from a specific memory cell is transferred via a data input/output (I/O) line pair to a sense amplifier.
- the sense amplifier senses and amplifies a small voltage difference between the to lines of the data I/O line pair and outputs an amplified signal that has a predetermined logic level.
- FIG. 1 is a block diagram showing a conventional semiconductor memory device arrangement 10 containing a two-stage sense amplifier structure.
- the conventional arrangement of a semiconductor memory device includes a memory cell 11 , a first sense amplifier 12 , a second sense amplifier 13 and a delay unit 14 .
- a data stored in the memory cell 11 is read out in response to a column select signal COLUMN_SELECT applied to the memory cell.
- the read data is applied to a data I/O line DB and a complementary data I/O line /DB.
- the first sense amplifier 12 which is enabled in response to a sense amplifier strobe signal SA_STROBE, senses and amplifies a voltage difference between the data I/O line DB and the complementary data I/O line /DB to thereby generate an amplified signal.
- the delay unit 14 delays the sense amplifier strobe signal SA_STROBE for a predetermined time to generate a delayed sense amplifier strobe signal. Then, the second sense amplifier 13 senses and amplifies the amplified signal in response to the delayed sense amplified strobe signal.
- the voltage difference between the data I/O line DB and the complementary data I/O line /DB are greatly increased through two sense amplifiers 12 and 13 , so that an erroneous operation due to various noise factors can be effectively prevented.
- the second sense amplifier 13 is operated a predetermined time after the operation of the first sense amplifier 12 , the operation speed of the semiconductor memory device is limited.
- the inventions claimed herein feature, at least in part, an arrangement for improving the sensitivity of a sense amplifier. This sensitivity increase is accomplished by increasing a voltage difference between a data I/O line an a complementary data I/O line.
- a semiconductor memory device comprising a plurality of memory cells for storing data.
- a data input/output (I/O) line pair (including a data I/O line and a complementary data I/O line), coupled to the memory cells, transfers the data.
- a sense amplifier senses and amplifies a voltage difference between the data I/O line and the complementary data I/O line.
- a capacitor is arranged so as to have a first of its terminals coupled to the data I/O line.
- a first switch transfers the data applied to the data I/O line pair to two terminals of the capacitor in response to a first control signal.
- a second switch means couples the second terminal of the capacitor to the data I/O line in response to a second control signal.
- FIG. 1 (Prior Art) is a block diagram showing a conventional semiconductor memory device arrangement
- FIG. 2 is a schematic diagram illustrating a semiconductor memory device arrangement in accordance with the present invention.
- FIG. 3 is a graphical representation of a simulation comparing results of sensing operations of the prior art arrangement and the arrangement according to the inventions described herein.
- FIG. 2 is a schematic diagram of a semiconductor memory device arrangement in accordance with the present invention.
- the semiconductor memory device 20 in accordance with the present invention includes a memory cell 21 , a sense amplifier 22 , a capacitor C 21 coupled between a data I/O line DB and a complementary data I/O line /DB, a first switching unit 23 for transferring a data applied to the data I/O line pair DB and /DB to two terminals of the capacitor C 21 in response to a first control signal SW_CNT 1 , a second switching unit 24 which is responsive to a second control signal SW_CNT 2 and is coupled between one, e.g., DB, of the data I/O line pair and one terminal of the capacitor C 21 .
- First control signal SW_CNT 1 is provided by NANDing (using gate ND 22 ) a column select signal COLUMN_SELECT and an inverted (inverted by INV 21 ) sense amplifier strobe signal.
- the second control signal SW_CNT 2 is provided by NANDing (using gate ND 21 ) the column select signal COLUMN_SELECT and a sense amplifier strobe signal SA_STROBE and delaying the output of gate ND 21 for a predetermined time using a delay unit 25 .
- Sense Amplifier 22 is strobed by SA_STROBE delayed by a delay unit 26 .
- Capacitor C 21 is constructed and arranged so that its capacitance is larger than a static capacitance of an input terminal of the sense amplifier and smaller than a parasitic capacitance of the data I/O line pair
- the first switching unit 23 includes a PMOS transistor MP 21 for coupling the data I/O line DB to one input terminal of the sense amplifier 22 in response to the first control signal SW_CNT 1 , and a PMOS transistor MP 22 , coupled between the capacitor C 21 and the complementary data I/O line /DB, whose gate receives the first control signal SW_CNT 1 .
- the second switching unit 24 is implemented with a PMOS transistor MP 23 , coupled between one terminal of the capacitor C 21 and the data I/O line DB, whose gate receives the second control signal SW_CNT 2 .
- capacitor C 21 (the one that is not coupled to one input terminal of the sense amplifier 22 ) is electrically coupled to the second switching unit 24 .
- the PMOS transistor MP 3 contained in the second switching unit 24 is turned on in response to an activated sense amplifier strobe signal SA_STROBE.
- Delay unit 25 has a minimum delay time required to prevent the second switching unit 24 from being turned on before the first switching unit 23 is turned off. That is, data damage, which is caused by a potential applied to two terminals of the capacitor C 21 when the PMOS transistor MP 3 is turned on, can be effectively prevented due the delay unit 25 .
- FIG. 3 is a graphical representation of a simulated comparison of the resulting operation of the prior art arrangement with that of the claimed inventions. Compared with the prior art, a voltage difference according to the present invention becomes larger, thereby obtaining an improved sensitivity of the sense amplifier.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Abstract
Description
- 1. Field of the Invention
- The inventions claimed herein relate in general to semiconductor memory devices. More specifically, the claimed inventions relate to circuit arrangements for driving a sense amplifier for use with semiconductor memory devices. A sense amplifier is caused to achieve a high sensitivity by increasing a voltage difference between a data I/O line and a complementary data I/O line.
- 2. General Background and Related Art
- In a semiconductor memory device, data read out from a specific memory cell is transferred via a data input/output (I/O) line pair to a sense amplifier. The sense amplifier senses and amplifies a small voltage difference between the to lines of the data I/O line pair and outputs an amplified signal that has a predetermined logic level.
- FIG. 1 (Prior Art) is a block diagram showing a conventional semiconductor
memory device arrangement 10 containing a two-stage sense amplifier structure. The conventional arrangement of a semiconductor memory device includes amemory cell 11, afirst sense amplifier 12, asecond sense amplifier 13 and adelay unit 14. - In a read operation, a data stored in the
memory cell 11 is read out in response to a column select signal COLUMN_SELECT applied to the memory cell. The read data is applied to a data I/O line DB and a complementary data I/O line /DB. Then, thefirst sense amplifier 12, which is enabled in response to a sense amplifier strobe signal SA_STROBE, senses and amplifies a voltage difference between the data I/O line DB and the complementary data I/O line /DB to thereby generate an amplified signal. - The
delay unit 14 delays the sense amplifier strobe signal SA_STROBE for a predetermined time to generate a delayed sense amplifier strobe signal. Then, the second sense amplifier 13 senses and amplifies the amplified signal in response to the delayed sense amplified strobe signal. - In the conventional
semiconductor memory device 10 having the two-stage sense amplifier structure, the voltage difference between the data I/O line DB and the complementary data I/O line /DB are greatly increased through twosense amplifiers - However, since the
second sense amplifier 13 is operated a predetermined time after the operation of thefirst sense amplifier 12, the operation speed of the semiconductor memory device is limited. - The inventions claimed herein feature, at least in part, an arrangement for improving the sensitivity of a sense amplifier. This sensitivity increase is accomplished by increasing a voltage difference between a data I/O line an a complementary data I/O line.
- In accordance with an aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of memory cells for storing data. A data input/output (I/O) line pair (including a data I/O line and a complementary data I/O line), coupled to the memory cells, transfers the data. A sense amplifier senses and amplifies a voltage difference between the data I/O line and the complementary data I/O line. A capacitor is arranged so as to have a first of its terminals coupled to the data I/O line. A first switch transfers the data applied to the data I/O line pair to two terminals of the capacitor in response to a first control signal. A second switch means couples the second terminal of the capacitor to the data I/O line in response to a second control signal.
- The claimed inventions will be further explained by describing in detail exemplary embodiments illustrating the principles of the inventions. These exemplary embodiments are described with reference to the drawings, in which:
- FIG. 1 (Prior Art) is a block diagram showing a conventional semiconductor memory device arrangement;
- FIG. 2 is a schematic diagram illustrating a semiconductor memory device arrangement in accordance with the present invention; and
- FIG. 3 is a graphical representation of a simulation comparing results of sensing operations of the prior art arrangement and the arrangement according to the inventions described herein.
- FIG. 2 is a schematic diagram of a semiconductor memory device arrangement in accordance with the present invention. The
semiconductor memory device 20 in accordance with the present invention includes amemory cell 21, asense amplifier 22, a capacitor C21 coupled between a data I/O line DB and a complementary data I/O line /DB, afirst switching unit 23 for transferring a data applied to the data I/O line pair DB and /DB to two terminals of the capacitor C21 in response to a first control signal SW_CNT1, asecond switching unit 24 which is responsive to a second control signal SW_CNT2 and is coupled between one, e.g., DB, of the data I/O line pair and one terminal of the capacitor C21. - First control signal SW_CNT1 is provided by NANDing (using gate ND22) a column select signal COLUMN_SELECT and an inverted (inverted by INV21) sense amplifier strobe signal. The second control signal SW_CNT2 is provided by NANDing (using gate ND21) the column select signal COLUMN_SELECT and a sense amplifier strobe signal SA_STROBE and delaying the output of gate ND21 for a predetermined time using a
delay unit 25. Sense Amplifier 22 is strobed by SA_STROBE delayed by adelay unit 26. - Capacitor C21 is constructed and arranged so that its capacitance is larger than a static capacitance of an input terminal of the sense amplifier and smaller than a parasitic capacitance of the data I/O line pair
- The
first switching unit 23 includes a PMOS transistor MP21 for coupling the data I/O line DB to one input terminal of thesense amplifier 22 in response to the first control signal SW_CNT1, and a PMOS transistor MP22, coupled between the capacitor C21 and the complementary data I/O line /DB, whose gate receives the first control signal SW_CNT1. - The
second switching unit 24 is implemented with a PMOS transistor MP23, coupled between one terminal of the capacitor C21 and the data I/O line DB, whose gate receives the second control signal SW_CNT2. - Operation of the semiconductor
memory device arrangement 20 in accordance with the present invention will be described with reference to FIG. 2. When the column select signal COLUMN_SELECT is activated, the PMOS transistors MP21 and MP22 contained in thefirst switching unit 23 are turned on so that a potential corresponding to the data read out from thememory cell 21 is applied to two terminals of the capacitor C21. Then, when the sense amplifier strobe signal SA_STROBE is activated to a low level, the PMOS transistors MP1 and MP2 are turned off in response to the second control signal SW_CNT2 of a high level. - The other terminal of capacitor C21 (the one that is not coupled to one input terminal of the sense amplifier 22) is electrically coupled to the
second switching unit 24. As a result, the PMOS transistor MP3 contained in thesecond switching unit 24 is turned on in response to an activated sense amplifier strobe signal SA_STROBE. -
Delay unit 25 has a minimum delay time required to prevent thesecond switching unit 24 from being turned on before thefirst switching unit 23 is turned off. That is, data damage, which is caused by a potential applied to two terminals of the capacitor C21 when the PMOS transistor MP3 is turned on, can be effectively prevented due thedelay unit 25. - When the PMOS transistor MP3 is turned on, one terminal of the capacitor C21 is electrically coupled to the data I/O line DB. Therefore, a potential on the data I/O line DB is increased by a voltage difference induced to the capacitor C21. Accordingly, a voltage difference inputted to the
sense amplifier 22 becomes about twice the voltage difference between the data I/O line DB and the complementary data I/O line /DB. - FIG. 3 is a graphical representation of a simulated comparison of the resulting operation of the prior art arrangement with that of the claimed inventions. Compared with the prior art, a voltage difference according to the present invention becomes larger, thereby obtaining an improved sensitivity of the sense amplifier.
- Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
Claims (14)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1999-63873 | 1999-12-28 | ||
KR99-63873 | 1999-12-28 | ||
KR1019990063873A KR100335275B1 (en) | 1999-12-28 | 1999-12-28 | Sense amplifier driving controller |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010022738A1 true US20010022738A1 (en) | 2001-09-20 |
US6295240B1 US6295240B1 (en) | 2001-09-25 |
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ID=19631192
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/749,599 Expired - Fee Related US6295240B1 (en) | 1999-12-28 | 2000-12-28 | Controlling a sense amplifier |
Country Status (3)
Country | Link |
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US (1) | US6295240B1 (en) |
JP (1) | JP4375644B2 (en) |
KR (1) | KR100335275B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030210078A1 (en) * | 2002-05-08 | 2003-11-13 | University Of Southern California | Current source evaluation sense-amplifier |
US20040001364A1 (en) * | 2002-06-26 | 2004-01-01 | Silicon Graphics, Inc. | System and method for a self-calibrating sense-amplifier strobe |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100377169B1 (en) * | 2000-12-28 | 2003-03-26 | 주식회사 하이닉스반도체 | Data bus line sense amplifiers |
KR100721193B1 (en) * | 2001-07-19 | 2007-05-23 | 주식회사 하이닉스반도체 | DRAM Bitline Sense Amplifier Circuit |
KR100847761B1 (en) * | 2002-03-29 | 2008-07-23 | 주식회사 하이닉스반도체 | Sence Amplifier for sencing current |
KR100510737B1 (en) * | 2002-06-29 | 2005-08-30 | 매그나칩 반도체 유한회사 | semiconductor memory device |
JP4278414B2 (en) * | 2003-03-18 | 2009-06-17 | 株式会社ルネサステクノロジ | Semiconductor memory device |
KR100935720B1 (en) * | 2007-05-17 | 2010-01-08 | 주식회사 하이닉스반도체 | Input output line sense amplifier and semiconductor device |
KR100863032B1 (en) | 2007-08-14 | 2008-10-13 | 주식회사 하이닉스반도체 | Data bus sense-amplifier circuit |
JP7234178B2 (en) * | 2020-03-19 | 2023-03-07 | 株式会社東芝 | Storage device |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5684736A (en) * | 1996-06-17 | 1997-11-04 | Nuram Technology, Inc. | Multilevel memory cell sense amplifier system |
JP3183331B2 (en) * | 1997-09-22 | 2001-07-09 | 日本電気株式会社 | Dynamic semiconductor memory device |
-
1999
- 1999-12-28 KR KR1019990063873A patent/KR100335275B1/en not_active IP Right Cessation
-
2000
- 2000-12-22 JP JP2000391303A patent/JP4375644B2/en not_active Expired - Fee Related
- 2000-12-28 US US09/749,599 patent/US6295240B1/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030210078A1 (en) * | 2002-05-08 | 2003-11-13 | University Of Southern California | Current source evaluation sense-amplifier |
US7023243B2 (en) | 2002-05-08 | 2006-04-04 | University Of Southern California | Current source evaluation sense-amplifier |
US20040001364A1 (en) * | 2002-06-26 | 2004-01-01 | Silicon Graphics, Inc. | System and method for a self-calibrating sense-amplifier strobe |
US6714464B2 (en) * | 2002-06-26 | 2004-03-30 | Silicon Graphics, Inc. | System and method for a self-calibrating sense-amplifier strobe |
Also Published As
Publication number | Publication date |
---|---|
US6295240B1 (en) | 2001-09-25 |
JP2001202784A (en) | 2001-07-27 |
KR20010061379A (en) | 2001-07-07 |
JP4375644B2 (en) | 2009-12-02 |
KR100335275B1 (en) | 2002-05-03 |
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