KR20010059962A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to prevent a mis-operation of a main amp by inserting a local data line amp between a bit line sense amp and the main amp. CONSTITUTION: A sub memory array(10) comprises a plurality of memory cells, and a bit line sense amp array(20) comprises a plurality of bit line sense amps sensing data loaded on bit lines(BL,/BL) by being connected to both sides of the sub memory array. A row decoder enables a word line(WL) to drive a memory cell corresponding to a row address by decoding the row address, and a column selection switch(CSW) transfers data amplified by the bit line sense amp to local data buses(LDB0,/LDB0)(LDB2,/LDB2). A local data line sense amp(50) senses data loaded on the above local data buses by being controlled by a sense amp enable signal(SAEN). And a block selection switch(BSW) transfers data loaded on the above local data buses to global data buses(GDB0,/GDB0)(GDB2,/GDB2) selectively.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, by inserting a local data line sense amplifier between a bit line sense amplifier and a main amplifier so that accurate data can be transmitted even when data is transmitted by a data line under heavy load. A semiconductor memory device.

FIG. 1 is a block diagram illustrating a data bus structure in a general DRAM. As shown in FIG. 1, a plurality of sub memory arrays 1 including a plurality of memory cells are arranged, and both sides of the sub memory array 1 are arranged. A bit line sense amplifier 2 connected to an end and configured with a plurality of bit line sense amplifiers configured to sense data carried on the bit lines BL and / BL, and a memory cell corresponding to the row address by decoding a row address. A row decoder 3 for driving a word line WL, a column select switch CSW for selectively transferring data amplified by the bit line sense amplifiers to local data buses LDB and / LDB; Block selection switch (BSW) for selectively transferring data on the local data bus (LDB, / LDB) to the global data bus (GDB, / GDB), and on the global data bus (GDB, / GDB) Sensing the data to be configured to include a main amplifier 4, for output to an output buffer (not shown) through a global input and output lines (GIO0-GIO3).

FIG. 2 is a block diagram illustrating a portion of FIG. 1. As shown in FIG. 1, a sub memory array 1 including a plurality of memory cells and a bit line BL are connected to both ends of the sub memory array 1. And a bit line sense amplifier array (2) consisting of a plurality of bit line sense amplifiers for sensing data contained in the < RTI ID = 0.0 > / BL < / RTI > and a word line WL for decoding a row address and driving a memory cell corresponding to the row address. A row decoder (3) for enabling a signal, a column select switch (CSW) for selectively transferring data amplified by the bit line sense amplifiers to local data buses (LDB0, / LDB0) (LDB2, / LDB2); A block select switch BSW for selectively transferring data carried on the local data buses LDB0, / LDB0 (LDB2, / LDB2) to the global data buses GDB0, / GDB0) GDB2, / GDB2 is shown. .

The operation of the general DRAM illustrated in this manner will be described below.

First, when a row address is input, the row decoder of the selected block is activated to enable the word line WL. Therefore, the memory cell connected to the enabled word line WL transfers the stored data to the bit lines BL and / BL.

Subsequently, the data carried on the bit lines BL and / BL is sensed by the bit line sense amplifier of the bit line sense amplifier array 2 and transferred to the local data buses LDB and / LDB by the column select switch CSW. do.

Subsequently, the data loaded on the local data buses LDB and / LDB are transferred to the global data buses GDB and / GDB by the block select switch BSW, and the data loaded on the global data buses GDB and / GDB are stored. The sensor is sensed by the main amplifier 4 and output to the outside through an output buffer (not shown) through the global input / output line GIO.

The local data buses LDB and / LDB generally exchange data with bit line sense amplifiers corresponding to a plurality of sub memory arrays, and are arranged parallel to the memory array.

The data passed from the bitline sense amplifier to the local data buses (LDB, / LDB). In general, since the driving ability of the bit line sense amplifier is weak due to the chip area, a small amount of data is also transferred to the local data buses (LDB and / LDB). For example, when 2.0 V is used as the power supply voltage VDD, the voltage difference between the bit lines BL and / BL is about 2.0 V, but the voltage difference between the local data buses LDB and / LDB is about 0.1 V −. Very little around 0.2.

Data carried on the local data buses (LDB, / LDB) is transferred to the global data buses (GDB, / GDB) via the block select switch (BSW), which is under load by the global data buses (GDB, / GDB). The amount of data is further reduced.

Therefore, the probability of generating an error in the main amplifier 4 increases.

In order to solve such a problem, when the data is input for a long time to increase the amount of input voltage input to the main amplifier 4, the probability of generating an error is reduced, but in the current semiconductor memory device using an operating frequency of 200 MHz This method is not available.

As described above, in the conventional DRAM, a method of amplifying data carried on the bit lines BL and / BL by a bit line sense amplifier and then directly transferring the data to the main amplifier 4 is used. However, as the memory density increases, the number of bit line sense amplifiers connected to the data bus increases or increases in length, while the driving capacity is reduced to reduce the area of the bit line sense amplifiers, which are transferred to the data bus. The amount of data is reduced. Therefore, the main amplifier 4 senses a small amount of voltage difference transmitted to the data bus and transfers it to the output buffer. However, as the input voltage difference decreases, there is a problem in that a probability of malfunction occurs.

In order to compensate for such a decrease in the amount of data, when the size is increased to increase the driving capability of the bit line sense amplifier, a problem arises in that the chip area is increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of preventing a malfunction of a main amplifier by inserting a local data line amplifier between a bit line sense amplifier and a main amplifier.

The semiconductor memory device of the present invention for achieving the above object,

A sub memory array consisting of a plurality of memory cells,

A bit line sense amplifier array connected to both ends of the sub memory array and configured of a plurality of bit line sense amplifiers configured to sense data carried on bit lines;

A row decoder that decodes a row address and enables a word line to drive a memory cell corresponding to that row address;

A column select switch controlled by a column select signal and selectively transferring data amplified by the bit line sense amplifier to a local data bus;

A local data line sense amplifier configured to sense and control data carried on the local data bus by a sense amplifier enable signal;

A block selection switch for selectively transferring data on the local data bus to a global data bus;

And a main amplifier configured to sense data carried on the global data bus and deliver the data to the output buffer through a global input / output line.

Or a sub memory array consisting of a plurality of memory cells;

A bit line sense amplifier array connected to both ends of the sub memory array and configured of a plurality of bit line sense amplifiers configured to sense data carried on bit lines;

A row decoder that decodes a row address and enables a word line to drive a memory cell corresponding to that row address;

A column select switch for selectively transferring data amplified by the bit line sense amplifier to a local data bus;

A block select switch for selectively passing data on the local data bus to the global data bus;

A global data line sense amplifier controlled by a sense amplifier enable signal to sense and amplify data carried on the global data bus;

And a main amplifier for sensing the data amplified by the global data line sense amplifier and outputting the amplified data to the output buffer through the global input / output line.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a data bus structure of a general DRAM (DRAM).

FIG. 2 is a block diagram illustrating a portion of the data bus structure of FIG. 1. FIG.

3 is a block diagram illustrating one embodiment of a local data sense amplifier arrangement in accordance with the present invention.

4 is a detailed circuit diagram of a local data sense amplifier of one embodiment of FIG.

5 is an operation timing diagram of the local data sense amplifier of FIG. 4;

6 is a block diagram illustrating another embodiment of a local data sense amplifier arrangement in accordance with the present invention.

<Description of Symbols for Major Parts of Drawings>

10: sub memory array

20: bit line sense amplifier array

30: low decoder

50: local data line sense amplifier

60: global data line sense amplifier

CSW: Column Selector Switch

BSW: Block Selector Switch

PM1, PM2: PMOS transistor

NM1, NM2, NM11, NM12: NMOS transistor

FIG. 3 is a block diagram of an intermediate sense amplifier arranged to amplify a voltage difference between local data buses LDB and / LDB in a semiconductor memory device according to the present invention. As shown in FIG. A bit line sense amplifier array 20 having a plurality of bit line sense amplifiers connected to both ends of the sub memory array 10 and configured to sense data carried on bit lines BL and / BL; A row decoder 30 for enabling a word line WL to decode a row address and drive a memory cell corresponding to the row address, and selectively converts data amplified by the bit line sense amplifier into a local data bus ( A column select switch (CSW) for transmitting to LDB0, / LDB0) (LDB2, / LDB2) and a sense amplifier enable signal (SAEN) for data loaded on the local data buses (LDB0, / LDB0) (LDB2, / LDB2). On The local data line sense amplifier 50 that is controlled and sensed and the data contained in the local data buses LDB0 and / LDB0 (LDB2 and / LDB2) are selectively global data buses GDB0 and / GDB0 (GDB2, /). A block select switch (BSW) to GDB2 is shown.

The memory cell array has a structure in which sub memory array blocks 10 are arranged to access cells. Here, the memory cell is a typical DRAM cell structure consisting of a transistor and a capacitor, a word line WL is connected to a gate of a transistor, a capacitor is connected to a source, and a drain thereof is connected to a bit line BL or / BL.

The bit line sense amplifier amplifies the data carried on the bit lines BL and / BL to full swing (VDD-VSS), and then transfers the data to the local data buses LDB and / LDB by the column select switch CSW. do.

The bit line sense amplifier array 20 is a switch for connecting the bit line and the sense amplifier selectively and means for equalizing and precharging the sensing means having a cross-coupled latch form, the bit lines BL and / BL in a conventional structure. It consists of means, a column switch which selectively connects the sense amplifier and the local data buses (LDB, / LDB).

Here, the switch means connects two points to be intermitted to the source and the drain using an NMOS transistor and uses a control signal for the gate.

The local data line sense amplifier used as the intermediate sense amplifier may be an NMOS type sense amplifier in which two NMOS transistors NM1 and NM2 are cross-coupled as shown in FIG. 4A or FIG. 4B. As shown in FIG. 2, the PMOS transistors PM1 and PM2 and the NMOS transistors NM11 and NM12 may use a cross coupled sense amplifier that is cross coupled.

Operation of the output structure of the semiconductor memory device using the local data line sense amplifier 50 according to the present invention configured as described above is as follows.

First, when a row address is input, the row decoder of the selected block is activated to enable the word line WL. Therefore, the memory cell connected to the enabled word line WL transfers the stored data to the bit lines BL and / BL.

Subsequently, the data carried on the bit lines BL and / BL is sensed by the bit line sense amplifier of the bit line sense amplifier array 20 and transferred to the local data buses LDB and / LDB by the column select switch CSW. do.

At this time, the voltage difference between the local data buses LDB and / LDB is sensed and amplified by the local data line sense amplifier 50 controlled by the sense amplifier enable signal SAEN.

Subsequently, the data amplified by the local data line sense amplifier 50 is transferred to the global data buses GDB and / GDB by the block select switch BSW, and loaded onto the global data buses GDB and / GDB. The data is sensed by the main amplifier and output to the outside through an output buffer (not shown) through the global input / output line (GIO).

FIG. 5 is an operation timing diagram of the output operation as described above. As shown in FIG. 5, the column amplification signal YI is enabled and the column select switch CSW is turned on so that the data amplified by the bit line sense amplifier is turned on. It is transmitted to the data bus (LDB, / LDB), but in the prior art (A) the voltage difference between the local data bus (LDB, / LDB) was about 0.2V at most, in the present invention (B) sense amplifier enable signal (SAEN) Since the local data line sense amplifier 50 amplifies and outputs the voltage difference between the local data buses LDB and / LDB again, the main amplifier senses and amplifies a sufficient voltage difference, and then amplifies the global input / output line GIO. Data can be delivered via

The sense amplifier enable signal SAEN is a global signal enabled about 1 nsec after the column select signal YI is enabled.

FIG. 6 illustrates an embodiment in which an intermediate sense amplifier is arranged to amplify the voltage difference between the global data buses GDB and / GDB in the output structure of the semiconductor memory device of the present invention. As shown in FIG. A bit line sense amplifier array 20 having a plurality of bit line sense amplifiers connected to both ends of the array 10 and the sub memory array 10 and configured to sense data carried on the bit lines BL and / BL; And a row decoder 30 for enabling the word line WL to decode the row address and drive the memory cell corresponding to the row address, and selectively convert the data amplified by the bit line sense amplifier into a local data bus. Column data selector switch (CSW) to (LDB0, / LDB0) (LDB2, / LDB2) and data loaded on local data buses (LDB0, / LDB0) (LDB2, / LDB2). The global data buses GDB0, / GDB0, GDB2, / GDB2 are controlled by the block select switch BSW to be transmitted to (GDB0, / GDB0) (GDB2, / GDB2) and the sense amplifier enable signal SAEN. A global data line sense amplifier 60 for sensing and amplifying the data contained in FIG.

Operation of the output structure of the semiconductor memory device using the local data line sense amplifier 50 according to the present invention configured as described above is as follows.

First, when a row address is input, the row decoder of the selected block is activated to enable the word line WL. Therefore, the memory cell connected to the enabled word line WL transfers the stored data to the bit lines BL and / BL.

Subsequently, the data carried on the bit lines BL and / BL is sensed by the bit line sense amplifier of the bit line sense amplifier array 20 and transferred to the local data buses LDB and / LDB by the column select switch CSW. do.

Subsequently, the data amplified by the local data line sense amplifier 50 is transferred to the global data buses GDB and / GDB by the block select switch BSW.

In this case, the voltage difference between the global data buses GDB and / GDB is sensed and amplified by the global data line sense amplifier 60 controlled by the sense amplifier enable signal SAEN.

Therefore, the data amplified by the global data line sense amplifier 60 is sensed by the main amplifier and output to the outside through an output buffer (not shown) through the global input / output line GIO.

As described above, the data on the bit lines BL and / BL are amplified by the sense amplifier 20 and transferred to the main amplifier, thereby causing a malfunction of the main amplifier and a delay of the operation speed to be generated between the sense amplifier 20 and the main amplifier. An intermediate sense amplifier for amplifying a local data bus (LDB, / LDB) or a global data bus (GDB, / GDB) may be arranged and amplified once more to prevent malfunction of the main amplifier and delay of an operation speed.

As described above, the present invention can amplify the data on the local data bus or the global data bus once more to prevent malfunction of the main amplifier and to transmit accurate data without delay in the operation speed even when a low voltage is used. There is.

Claims (8)

A sub memory array consisting of a plurality of memory cells, A bit line sense amplifier array connected to both ends of the sub memory array and configured of a plurality of bit line sense amplifiers configured to sense data carried on bit lines; A row decoder that decodes a row address and enables a word line to drive a memory cell corresponding to that row address; A column select switch controlled by a column select signal and selectively transferring data amplified by the bit line sense amplifier to a local data bus; A local data line sense amplifier configured to sense and control data carried on the local data bus by a sense amplifier enable signal; A block selection switch for selectively transferring data on the local data bus to a global data bus; And a main amplifier configured to sense data carried on the global data bus and output the output data to an output buffer through a global input / output line. In the semiconductor memory device of claim 1, The local data line sense amplifier, A semiconductor memory device comprising: an NMOS type sense amplifier comprising two NMOS type transistors connected to a local data bus by applying a sense amplifier enable signal inverted to a common connected source and a gate connected to a drain of each other; . In the semiconductor memory device of claim 1, The local data line sense amplifier, And a cross coupled sense amplifier comprising two CMOSs connected in parallel between the sense amplifier enable signal and its inverted signal, the gates of which are commonly connected, and connected to a local data bus. In the semiconductor memory device of claim 1, And the sense amplifier enable signal is a global signal generated by the column address. A sub memory array consisting of a plurality of memory cells, A bit line sense amplifier array connected to both ends of the sub memory array and configured of a plurality of bit line sense amplifiers configured to sense data carried on bit lines; A row decoder that decodes a row address and enables a word line to drive a memory cell corresponding to that row address; A column select switch for selectively transferring data amplified by the bit line sense amplifier to a local data bus; A block select switch for selectively passing data on the local data bus to the global data bus; A global data line sense amplifier controlled by a sense amplifier enable signal to sense and amplify data carried on the global data bus; And a main amplifier configured to sense data amplified by the global data line sense amplifier and to output the amplified data to an output buffer through a global input / output line. The semiconductor memory device of claim 5, wherein The global data line sense amplifier, Inverted sense amplifier enable signal is applied to a common connected source, the semiconductor memory device characterized in that the gate is an NMOS type sense amplifier consisting of two NMOS transistors connected to the drain of each other and connected to the global data bus . The semiconductor memory device of claim 5, wherein The global data line sense amplifier, And a cross coupled sense amplifier comprising two CMOSs connected in parallel between the sense amplifier enable signal and the inverted signal thereof, the gates being connected in common, and connected to a global data bus. The semiconductor memory device of claim 5, wherein And the sense amplifier enable signal is a global signal generated by the column address.