KR100278278B1 - Content address memory for high speed - Google Patents

Abstract

According to the present invention, when the comparison result is matched, the comparison result signal of the memory cell is output not only to a low value but also to a high value, and to sense the comparison result signal through a sense amplifier. In order to provide a content address memory that can reduce the capacitance of a contact in which a search result output line of a plurality of memory cells is coupled, thereby improving the operation speed. A memory cell area for latching and storing any address data input from an external device in response to a write enable signal, and outputting a signal indicating whether the address data matches the stored data during a read operation, and an output of the memory cell area; Contents addressing with sense amplifier that detects the signal, amplifies it, and outputs the final match signal. In an exemplary embodiment, when the content address memory read operation is performed, the memory cell area may set a signal indicating a high or low value when the stored data coincides with an inversion data of the address data input from an external value. And outputs a signal having a predetermined value and plots the data when the stored data and the inverted data of the address data do not coincide with each other. After precharging an arbitrary line connected to one signal to a predetermined value, a signal indicating whether a match having a low or high value is input from the memory cell region at a search timing is detected and outputs a final match signal. It is composed.

Description

Content address memory for high speed processing {CONTENT ADDRESS MEMORY FOR HIGH SPEED}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a content address memory (CAM), and more particularly, a low or high signal representing a case where an address data input from an external device and data stored therein coincide with each other. By outputting from the area, and sensed by the sense amplifier to output a match, the capacitance is reduced by almost half, and eventually the operation speed of the content address memory (CAM) is improved. ).

1 shows a configuration diagram of a conventional content address memory CAM.

The memory cell of the content address memory has a function of storing data input from the outside and a search function of comparing the address data input from the external with the stored data and determining whether they match.

The memory cell of the conventional content address memory shown in FIG. 1 has a latch structure in which input and output terminals of two inverters are connected to each other, and data input from the outside through a switch transistor controlled by a write control signal WE. Is stored in the latch.

The comparison function of the memory cells is performed through the following process. The address data cmp value from the outside to be compared with the value of the node l, which is already stored data, or the cmpb value, which is the inverted value of the cmp value, which is the address data to be compared, and the node which is already stored data. If the value of 2 coincides, the NMOS transistor N3, N4 or the NMOS transistors N5, N6 are turned on and the node 3 is switched to the ground power supply (low value). The sense amplifier detects the change to the ground power supply and outputs a match signal high to indicate that the address data to be compared with the stored data match.

If the cmp value, which is the address data to be compared, and the value of nodel, which is already stored data, do not match, or the value of cmpb, which is the address data, to be compared with the value of node2, which is already stored data, Otherwise, the NMOS transistors N3 and N4 or the NMOS transistors N5 and N6 are turned off. For this reason, node 3 has a floating value, and the sense amplifier senses this and pulls a match signal low (to indicate that the stored address data does not match). low) to output.

As described above, a plurality of memory cells exist, and the search result output lines of the plurality of memory cells are connected to one sense amplifier, so that node 3 has a large capacitance. In other words, the delay time and the capacitance are proportional to each other. Therefore, the conventional content address memory CAM has a problem that the delay time is long because the capacitance is large and the speed is slow.

The present invention devised to solve the above problems of the prior art, when the comparison result is the same, the comparison result signal of the memory cell to be output as a high value as well as a low value (low) By sensing the result of the comparison signal through the sense amplifier, the capacitance of the contact point where the search result output lines of the plurality of memory cells are combined can be reduced by about half, thereby improving the content address memory. The purpose is to provide.

1 is a block diagram of a conventional content address memory.

2 is a diagram illustrating a memory cell circuit of a content address memory according to an exemplary embodiment of the present invention.

3 is a circuit diagram illustrating a sense amplifier of a content address memory according to an embodiment of the present invention.

4 is an overall configuration diagram of a content address memory according to an embodiment of the present invention.

In order to achieve the above object, the present invention latches and stores arbitrary address data input from an external device in response to a write enable signal during a write operation, and provides a signal indicating whether the address data matches the stored data during a read operation. A content address memory having a memory cell area for outputting and a sense amplifier configured to sense an output of the memory cell area, amplify the output signal, and output a final match signal, wherein the memory cell area is read during the read operation of the content address memory. Outputs a signal indicating a high or low value when the stored data and the inverted data of the address data input from the outside coincide with an arbitrary value, and outputs a signal having a high or low value, and inverted data of the stored data and the address data. If the values of do not match, they are plotted. And the sense amplifier precharges an arbitrary line connected to an arbitrary signal indicating a match input from the memory cell region to an arbitrary value prior to the search timing, and then, at the search timing, the memory cell region at the search timing. When a signal indicating a match having a low or high value from the input is detected, it is configured to output the final match signal.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4.

2 is a block diagram illustrating a memory cell circuit of a content address memory according to an exemplary embodiment of the present invention.

In general, the content address memory CAM has a longer searching time for reading and comparing the data than the writing time for storing the data in the memory cell. In the present invention, the write function for storing data in the memory cell is characterized in that the data inputted through the NMOS transistor MN1, which is a switch transistor under the control of the write enable signal WE, receives two inverters I11 and I12. Having a latch structure. In addition to the above method, if necessary, switch transistors may be respectively coupled to bidirectionally in a latch structure in which two inverters are combined to store input data in a latch.

The search function in the content address memory CAM according to the present invention is performed using an NMOS transistor and a PMOS transistor, unlike the conventional configuration.

In Fig. 2, the inverted address data CADB to be compared is input to the gate terminals of the NMOS transistor MN3 and the PMOS transistor MP1. Data stored in the latch (data stored in node 3) and its inverted data (data stored in node 4) are input to the gate terminals of the NMOS transistors MN2 and MN4, respectively.

Therefore, when the inverted address data CADB to be compared with the data stored in the latch (data stored in node 3) coincide with a high value, the NMOS transistors MN2 and MN3 are turned on to invert the match signal. (MATB) becomes a low value, where the match signal (MAT) is floating. On the contrary, when the inverted address data CADB and the data stored in the latch (the data stored in the node 3) coincide with the low value, the PMOS transistor MP1 and the NMOS transistor MN4 are turned on and the match signal MATB is turned on. The value becomes high and the inverted match signal MATB becomes flexible.

When the address data CADB to be compared with the data stored in the latch (data stored in node 3) are different from each other, the transistors are turned off, so that the match signal MAT and its inverted signal MATB are both It is floating.

3 is a circuit diagram of a sense amplifier improved to detect a comparison result of the memory cells.

The retarder combining the three inverters I21 to I23 is inverted for a predetermined time to precharge the node 11 to an arbitrary value having a high value at the search timing. The searchb is delayed to output an opposite signal of the inverted search timing control signal Searchb having an arbitrary time difference. In other words, the inverted search timing control signal Searchb has a low value at a time other than the search timing, and the inverted search timing control signal Searchb has a high value at the search timing. As a result, the gate terminal of the NMOS transistor MN10 receives a high value. Therefore, the NMOS transistor MN10 having a source terminal connected to Vdd and the drain terminal connected to node 11 becomes conductive so that node 11 has a high value sufficient to conduct NMOS transistor MN12. Precharged by

When the inverted search timing control signal Searchb has a high value due to the search timing, the NMOS transistor MN13 that receives the inverted search timing control signal to the gate terminal is turned on to form a ground channel.

If the match signal MAT, which is a search result signal applied from one of the plurality of memory cells, has a high value at this search timing, or the match bar signal MATB, which is an inverted signal thereof, has a low value, The output match signal Match_OUT is output as a high value to indicate that the same data as the address data to be compared is stored in the content address memory CAM.

Looking at this process in more detail with reference to Figure 3 as follows. First, when a match signal MAT having a high value is always applied to a high value from a memory cell, the match signal MAT is output as a final output match signal Match_OUT, which is an output of the content address memory. The match signal MAT is also applied to the gate terminals of the PMOS transistor MP11 and the NMOS transistor MN11. As a result, since the transistor MN11 is turned on, the node 11, which was precharged to a high value before the search timing, is changed to a low value. Here, the match bar signal MATB, which always has a low value, is floating when the match signal is applied at a high value, so that the value of node 11 is almost unchanged.

Each gate terminal of the PMOS transistor MP12 and the NMOS transistor MN12 is connected to the node 11. As described above, when the node 11 changes to a low value, the PMOS transistor MP12 having the source terminal connected to Vdd is turned on so that the final address of the content address memory CAM is maintained. Allows the output match signal (Match_OUT) to remain high continuously.

Before the end of the search timing, the high value is applied from the delay to the gate terminal of the transistor MN10, so node 11 is again precharged to the high value. Accordingly, the NMOS transistor MN12 having the gate terminal connected to the node 11 is turned on, thereby converting the final output match signal of the content address memory CAM to a low value.

Next, when the match bar signal MATB, which always has a low value, is applied from the memory cell to the low value, the node 11 precharged to the high value is converted to the low value.

As described above, when node 11 changes to a low value, the gate terminal is connected to node 11, and the PMOS transistor MP12 having a source terminal connected to Vdd is turned on so that the final output match signal Match_OUT of the content address memory CAM has a high value. Have Similarly, when the match bar signal MATB has a low value, the value of the node 11 hardly changes since the match signal MAT is flexible.

As described above, since the high value is applied to the gate terminal of the transistor MN10 before the search timing ends, the node 11 is precharged to the high value again, and the content address memory is stored by the NMOS transistor MN12 having the gate terminal connected to the node 11. The final output match signal of (CAM) is converted to a low value.

Finally, if there is no data that matches the address data to be compared in the memory cell, and the match signal MAT and its inverted match bar signal MATB are both floating, the node 11 precharges to a high value. Therefore, the final output match signal of the content address memory CAM has a low value at the search timing.

FIG. 4 shows an overall configuration diagram of a content address memory according to the present invention having a memory cell and a sense amplifier described with reference to FIGS. 2 and 3.

As can be seen from the figure, search result signals of a plurality of memory cells are divided into a match signal MAT and a match bar signal MATB and applied to a sense amplifier.

The present invention described above is capable of various substitutions, modifications, and changes within the scope without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains, and thus is limited to the above-described embodiments and drawings. It is not.

Accordingly, in the present invention as described above, when the address data to be compared with the data stored therein coincide, a low or high signal is output from the memory cell region as a signal indicating this. By distributing, the parasitic capacitance of the output line of the memory cell can be reduced by about half compared to the conventional method, thereby improving the processing speed of the contents address memory CAM.

Claims (12)

A memory cell area for latching and storing arbitrary address data input from an external device in response to a write enable signal during a write operation, and outputting a signal indicating whether the address data matches the stored data during a read operation; A content address memory having a sense amplifier which senses an output of an area, amplifies it, and outputs a final match signal. When reading the contents address memory, The memory cell area is When the stored data and the inverted data of the address data input from the outside coincide with an arbitrary value, a signal indicating this is output as a signal having a high or low value, and the value of the inverted data of the stored data and the address data. If this does not match, it is configured to plot. The sense amplifier, Pre-charge any line connected to any one signal indicating whether or not a match is input from the memory cell region before the search timing to an arbitrary value, and then match with a low or high value from the memory cell region at the search timing. Content address memory, characterized in that configured to output a final match signal by detecting the signal indicating whether or not. The memory cell of claim 1, wherein the memory cell area comprises: Means for latching the address data under control of the write enable signal; Means for generating a match signal when a data stored in the latching means and inverted data of the address data inputted from the outside coincide with a low value during a read operation; And Means for generating a match bar signal that is an inverted signal of the match signal when data stored in the latch means and inverted data of the address data input from the outside coincide with a high value during a read operation; Content address memory, characterized in that comprises a. The method of claim 2, wherein the latch means, A transistor for switching input data under the control of the write enable signal; And A latch unit including two inverters, the input terminal and the output terminal of each inverter is connected to latch the address data input through the transistor Content address memory, characterized in that comprises a. The method of claim 2, wherein the latch means, A first transistor configured to switch input address data under the control of the write enable signal; A second transistor configured to switch data having an opposite value to the address data under the control of the write enable signal; And A latch unit including two inverters, the input terminal and the output terminal of each inverter is connected to latch the data input through the first and second transistors Content address memory, characterized in that comprises a. The match signal generating means according to any one of claims 2 to 4, wherein A first PMOS transistor controlled according to the value of the address data to form a channel with a reference power source; And A first NMOS transistor controlled according to a value of data stored in the latching means and connected to the first PMOS transistor to output the match signal to a high value through a channel; Content address memory, characterized in that comprises a. The method of claim 5, wherein the match bar signal generating means, A second NMOS transistor controlled according to the value of the address data to form a channel with a ground power source; And A third NMOS transistor controlled according to the value of data stored in the latching means and connected to the second NMOS transistor to output the match bar signal to a low value through a channel; Content address memory, characterized in that comprises a. The method of claim 6, wherein the sense amplifier, Delay means for delaying and outputting the search timing control signal by an arbitrary time; Means for precharging a line connected to an input line of the match bar signal to an arbitrary value under the control of a signal input from the delay means; A fourth NMOS transistor configured to form a channel with a ground power source under the control of the search timing control signal; And Connected to the precharge means and a fourth NMOS transistor to output a final match signal to a high value if the input match signal has a high value, and to output a final match signal to a high value if the input match bar signal has a low value And a final match signal generating means for outputting the final match signal to a low value when the match signal and the match bar signal are fluidized. Content address memory, characterized in that comprises a. The method of claim 7, wherein the delay means, Content address memory, characterized in that configured by connecting a plurality of inverters in series. The method of claim 8, wherein the delay means, The search timing control signal is delayed for a predetermined time to output a signal having a value opposite to the search timing control signal, the precharge is completed before the start of the search timing, and the precharge is performed again before the completion of the search timing. Content address memory, characterized in that for controlling the charging means. The method of claim 9, wherein the precharge means, A fifth NMOS transistor controlled by receiving an output of the delay means from a gate terminal and having a reference power source and a channel having an arbitrary value; Content address memory, characterized in that comprises a. The method of claim 10, wherein the last match signal generating means, A sixth NMOS transistor controlled according to the match signal, wherein one side of a channel is connected to a contact point of the precharge means and an input line of the match bar signal, and the other side of the channel is connected to the fourth NMOS transistor; A second PMOS transistor having a gate terminal connected to a contact point of the precharge means and an input line of the match bar signal, and forming a channel between a reference power supply and a final match signal output terminal; And A seventh NMOS transistor having a gate terminal connected to the precharge means and an input line of the match bar signal, and having a channel formed between the fourth NMOS transistor and the final match signal output terminal; Content address memory, characterized in that comprises a. The method of claim 11, wherein the last match signal generating means, A third PMOS transistor having an input line of the match signal connected to a gate terminal and having a channel formed between a reference power supply and the sixth NMOS transistor; Content address memory, characterized in that further comprises a.

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