KR19990005462A - Content address memory for high speed processing - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Content address memory (CAM) for high speed processing.

2. The technical problem to be solved by the invention

The parasitic capacitance of the memory cell area and the connection of the sense amplifier is reduced by half to improve the processing speed.

3. Summary of Solution to Invention

In the memory address area and the contents address memory having a sense amplifier, the memory cell area outputs a signal indicating a high or low value when the stored data and the data to be compared coincide with an arbitrary value. And the sense amplifier precharges any line connected to any one signal indicating whether or not a match is input from the memory cell region before the search timing to an arbitrary value, and then outputs the memory cell region at the search timing. It is configured to amplify and output.

4. Important uses of the invention

Used for tag blocks such as microprocessors.

Description

Content address memory for high speed processing

The present invention relates to a content address memory (CAM), and more particularly, a signal indicating when a data to be compared with a previously stored data is matched. A low or high signal is generated from a memory cell region. By outputting it, and detecting it through a sense amplifier and outputting a match signal, the capacitance is reduced by about half, and eventually the operation speed of the content address memory CAM is improved to the content address memory CAM. It is about.

1 shows a configuration diagram of a conventional content address memory CAM.

The memory cell of the content address memory has a function of storing data input from the outside and a search function of comparing the address input from the external with the stored data and determining whether or not it matches.

The memory cell of the conventional content address memory shown in FIG. 1 has a latch structure in which input and output terminals of two inverters are connected to each other, and data input from the outside through a switch transistor controlled by a write control signal WE. Is stored in the latch.

The comparison function of the memory cells is performed through the following process. The value of cmp, the data to be compared, and the value of nodel, which is already stored data, or the value of compb, the inverted value of cmp, and the value of node2, which is already stored data, If they match (the same as the high value in the figure), the NMOS transistors N3, N4 or NMOS transistors N5, N6 are turned on and node3 is switched to ground power (low value). The sense amplifier senses the change to the ground supply and outputs a match signal high to indicate that the data to be compared and the stored data match.

If the value of cmp, the data to be compared, and the value of nodel, which is already stored data, do not match, or the value of compb, the data to be compared, and node2, which is already stored data, do not match. NMOS transistors N3, N4 or NMOS transistors N5, N6 are turned off. For this reason, node 3 has a floating value, and the sense amplifier senses it and sets the match signal low to indicate that the data to be compared and the stored data do not match. Will be printed as

As described above, a plurality of memory cells exist, and the search result output lines of the plurality of memory cells are connected to one sense amplifier, so that node 3 has a large capacitance. In other words, the delay time and the capacitance are proportional to each other. Therefore, the conventional content address memory CAM has a problem that the delay time is long because the capacitance is large and the speed is slow.

The present invention devised to solve the problems of the prior art as described above, when the comparison result is the same, the comparison result signal of the memory cell is to be output as a high value as well as a low (low) value, By detecting the result of the comparison signal through a sense amplifier, the capacitance of the contact point where the search result output lines of a plurality of memory cells are combined can be reduced by about half, thereby providing a content address memory that can improve the operation speed. Its purpose is to.

1 is a block diagram of a conventional content address memory;

2 is a configuration diagram of a memory cell circuit of a content address memory according to the present invention;

3 is a circuit diagram of a sense amplifier of a content address memory according to the present invention;

4 is an overall configuration diagram of a content address memory according to the present invention;

According to an aspect of the present invention, a memory cell region for latching arbitrary data by a write enable signal, and outputting a signal indicating whether data to be compared with stored data is matched with each other, A content address memory having a sense amplifier which senses an output, amplifies it, and outputs a final match signal, wherein the memory cell area indicates when the data to be compared with the stored data matches an arbitrary value. Outputs a signal as a signal having a high or low value, and is configured to operate fluidly if the value of the data to be compared with the stored data does not match, and the sense amplifier is configured to move from the memory cell region before the search timing. Any that is connected to any one signal that indicates whether or not an input is matched That it is configured after the precharge line to an arbitrary value, when the signal indicative of the match having a low or high value from the memory cell region in the input search detects the timing to output the final match signal is characterized.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4.

2 is a block diagram illustrating a memory cell circuit of a content address memory according to the present invention.

In general, the content address memory CAM has a longer searching time for reading and comparing data than a writing time for storing data in a memory cell. In the present invention, the write function for storing data in the memory cell is characterized in that the data inputted through the NMOS transistor MN1, which is a switch transistor under the control of the write enable signal WE, receives two inverters I11 and I12. By being stored in the latch structure having the same. In addition to the above method, if necessary, switch transistors may be respectively coupled to bidirectionally in a latch structure in which two inverters are combined to store input data in a latch.

The search function in the content address memory CAM according to the present invention is performed using an NMOS transistor and a PMOS transistor, unlike the conventional configuration.

In Fig. 2, the inverted comparison address data CADB is input to the gate terminals of the NMOS transistor MN3 and the PMOS transistor MP1. The data stored in the latch and the inverted data thereof are input to the gate terminals of the NMOS transistors MN2 and MN4, respectively.

Therefore, when the inverted comparison address data CADB and the data stored in the latch coincide with the high value, the NMOS transistors MN2 and MN3 are turned on so that the inverted match signal MATB becomes a low value. In this case, the match signal MAT is floating. On the contrary, when the inverted comparison address data CADB and the data stored in the latch coincide with the low value, the PMOS transistor MP1 and the NMOS transistor MN4 are turned on so that the match signal MATB becomes high. The match signal MATB is made flexible.

When the comparison address data and the data stored in the latch are different from each other, since the transistors are turned off, the match signal MAT and its inverted signal MATB are both floating.

3 is a circuit diagram of a sense amplifier improved to detect a comparison result of the memory cells.

The retarder combining the three inverters I21 to I23 is inverted for a predetermined time to precharge the node 11 to an arbitrary value having a high value at the search timing. The searchb is delayed to output an opposite signal of the inverted search timing control signal Searchb having an arbitrary time difference. In other words, the inverted search timing control signal Searchb has a low value at a time other than the search timing, and the inverted search timing control signal Searchb has a high value at the search timing. As a result, the gate terminal of the NMOS transistor MN10 receives a high value. Therefore, the source terminal is connected to Vdd and the drain terminal is connected to node 11 and transistor MN10 becomes conductive so that node 11 is precharged to a high value having a value sufficient to conduct NMOS transistor MN12.

When the inverted search timing control signal Searchb has a high value due to the search timing, the NMOS transistor MN13 that receives the inverted search timing control signal to the gate terminal is turned on to form a ground channel.

If the match signal MAT, which is a search result signal applied from one of the plurality of memory cells, has a high value at this search timing, or the match bar signal MATB, which is an inverted signal thereof, has a low value, The output match signal Match_OUT is output as a high value, indicating that data identical to the address to be compared is stored in the content address memory CAM.

Looking at this process in more detail with reference to Figure 3 as follows. First, when a match signal MAT having a high value is always applied to a high value from a memory cell, the match signal MAT is output as a final output match signal Match_OUT, which is an output of the content address memory. The match signal MAT is also applied to the gate terminals of the PMOS transistor MP11 and the NMOS transistor MN11. As a result, since the transistor MN11 is turned on, the node 11, which was precharged to a high value before the search timing, is changed to a low value. Here, the match bar signal MATB, which always has a low value, is floating when the match signal is applied at a high value, so that the value of node 11 is almost unchanged.

Each gate terminal of the PMOS transistor MP12 and the NMOS transistor MN12 is connected to the node 11. As described above, when the node 11 changes to a low value, the PMOS transistor MP12 having the source terminal connected to Vdd is turned on so that the final address of the content address memory CAM is maintained. Allows the output match signal (Match_OUT) to remain high continuously.

Before the end of the search timing, the high value is applied from the delay to the gate terminal of the transistor MN10, so node 11 is again precharged to the high value. Therefore, the NMOS transistor MN12 having the gate terminal connected to the node 11 is turned on, so that the final output match signal of the content address memory CAM is converted to a low value.

Next, when the match bar signal MATB, which always has a low value, is applied from the memory cell to the low value, the node 11 precharged to the high value is converted to the low value.

As described above, when node 11 changes to a low value, the gate terminal is connected to node 11, and the PMOS transistor MP12 having a source terminal connected to Vdd is turned on so that the final output match signal Match_OUT of the content address memory CAM has a high value. Have Similarly, when the match bar signal MATB has a low value, the value of the node 11 hardly changes since the match signal MAT is flexible.

As described above, since the high value is applied to the gate terminal of the transistor MN10 before the search timing ends, the node 11 is precharged to the high value again, and the content address memory is stored by the NMOS transistor MN12 having the gate terminal connected to the node 11. The final output match signal of (CAM) is converted to a low value.

Lastly, if the match signal MAT and its inverted match bar signal MATB are both floating because no data matching the comparison address data exists in the memory cell, the node 11 is precharged to a high value. At the search timing, the final output match signal of the content address memory CAM has a low value.

FIG. 4 shows an overall configuration diagram of a content address memory according to the present invention having a memory cell and a sense amplifier described with reference to FIGS. 2 and 3.

As can be seen from the figure, search result signals of a plurality of memory cells are divided into a match signal MAT and a match bar signal MATB and applied to a sense amplifier.

The present invention described above is capable of various substitutions, modifications, and changes within the scope without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains, and thus is limited to the above-described embodiments and drawings. It is not.

Accordingly, the present invention is achieved by dispersing the output line of a memory cell by outputting a low or high signal from the memory cell region as a signal indicating that the data to be compared and the data already stored are the same. The parasitic capacitance of the output line of the memory cell can be reduced by about half as compared with the conventional method, thereby improving the processing speed of the content address memory (CAM).

Claims (12)

After latching any data by a write enable signal, a memory cell area for outputting a signal indicating whether data to be compared with stored data is matched, and an output of the memory cell area are sensed and amplified, and a final match is made. A content address memory having a sense amplifier for outputting a signal, wherein the memory cell area is a signal having a high or low value when the data to be compared with the stored data matches an arbitrary value. And output the data, and if the value of the data to be compared with the stored data does not match, the sense amplifier is connected to any one signal indicating whether or not a match is input from the memory cell region before the search timing. Precharge to any value In the timing information, a memory address, characterized in that configured to output a final match signal when it detects a signal indicating a match with a low or high value from the memory cell region input. The memory cell area of claim 1, wherein the memory cell area is configured to latch data input from the outside under the control of a write enable signal, and that the data stored in the latching means coincide with a row value. Means for generating a match signal, and means for generating a match bar signal which is an inverted signal of the match signal when the data stored in the latch means and the data to be compared coincide with a high value. Address address memory. The method of claim 2, wherein the latching means includes a transistor for switching input data under the control of a write enable signal, and two inverters, wherein the input terminal and the output terminal of each inverter are connected to the transistor. And a latch unit for latching data input through the content address memory. 3. The apparatus of claim 2, wherein the latching means comprises: a first transistor for switching input data under the control of a write enable signal, and data having a value opposite to the input data under the control of the write enable signal; And a second transistor for switching and a latch unit including two inverters, the input terminal and the output terminal of each inverter being connected to latch a data input through the first and second transistors. Address memory. The first PMOS transistor according to any one of claims 2 to 4, wherein the match signal generating means includes: a first PMOS transistor configured to control a value of the data to be compared to form a channel with a reference power supply; And a first NMOS transistor controlled according to a value of stored data and connected to the first PMOS transistor to output a match signal at a high value through a channel. The control circuit according to claim 5, wherein the match bar signal generating means is controlled according to the value of the data stored in the latch means and the second NMOS transistor which is controlled according to the value of the data to be compared to form a channel with a ground power source. And a third NMOS transistor connected to the second NMOS transistor and outputting a match bar signal at a low value through a channel. The apparatus of claim 6, wherein the sense amplifier comprises delay means for delaying and outputting a search timing control signal by a predetermined time, and a line connected to an input line of the match bar signal under control of a signal input from the delay means. Means for precharging to an arbitrary value, a fourth NMOS transistor for forming a channel with a ground power source under the control of the search timing control signal, and the input match signal connected to the precharge means and the fourth NMOS transistor; Outputs a final match signal to a high value if has a high value; outputs the final match signal to a high value if the input match bar signal has a low value; And a final match signal generating means for outputting a match signal at a low value. 8. The content address memory according to claim 7, wherein the delay means is configured by connecting inverters in series. The method of claim 8, wherein the delay unit outputs a signal having a value opposite to that of the search timing control signal by delaying the search timing control signal for a predetermined time, and completes precharge before starting the search timing. And the precharge means for precharging again before timing completion. 10. The contents address memory as claimed in claim 9, wherein the precharge means includes a fifth NMOS transistor having a reference power source having a random value and a channel formed thereon, the output of the delay means being input to a gate terminal. . 11. The apparatus of claim 10, wherein the final match signal generating means is controlled according to the match signal, wherein one side of a channel is connected to a contact point of the precharge means and an input line of the match bar signal, and the other side of the channel is the first match. A sixth NMOS transistor connected to a fourth NMOS transistor, a second PMOS transistor connected to a gate terminal of the precharge means and an input line of the match bar signal, and forming a channel between a reference power supply and a final match signal output; And a seventh NMOS transistor having a gate terminal connected to the precharge means and an input line of the match bar signal, and having a channel formed between the fourth NMOS transistor and the final match signal output terminal. Address memory. 12. The contents address memory as claimed in claim 11, further comprising a third PMOS transistor having an input line of the match signal connected to a gate terminal and having a channel formed between a reference power supply and the sixth NMOS transistor.