KR950008450B1 - Operating voltage detecting circuit of memory cell - Google Patents

Abstract

This circuit comprises word lines which are connected with the gates of output transistors of memory cells in order to control the bi-directional data transfer, dummy word lines which detect the operation point of memory cells, a decoding unit (1) which outputs cell operation word signals (Wφ) in the word lines after decoding input address (ADD), a dummy decoding unit (2) which outputs the word signals (Wφ) and synchronized dummy word line (DWL) operation dummy signals (Dφ) to the dummy word lines, a sense amplifier (7) which detects and amplifies bit line data that is outputted from the memory cell, a bit line precharge voltage generator which has two transistors to precharge the bit line.

Description

Operating voltage detection circuit of memory cell

1 is an operating voltage detection circuit diagram of a memory cell of the present invention.

Figure 2 is a (a) to (d) is the operation waveform of each part according to the invention.

* Explanation of symbols for main parts of the drawings

1: Decoder unit 2: Dummy decoder unit

3: word line 4: dummy word line

6: operation voltage detector 7: sense amplifier

MN1, MN2: NMOS Transistors I1, I2: Inverter

The present invention relates to detecting an operating voltage of a memory cell. In particular, the present invention relates to detecting a time point at which a memory cell is turned on, thereby driving a sense amplifier, which can occur between a word line and a sense amplifier operation. The present invention relates to an operating voltage detection circuit of a memory cell suitable for optimizing delay.

Conventionally, in order to detect an operating voltage of a memory cell, an inverter sets a logic threshold voltage to a bit line precharge voltage (V _BLO ) and a threshold voltage (V _TN ) of a memory cell to turn on the memory cell. The operating voltage was detected at that time.

However, in the operation voltage circuit of the conventional memory cell, when the threshold voltages of the NMOS transistor and the PMOS transistor change according to a process, the bit line precharge voltage V _BLP level changes and the threshold voltage V of the memory cell. _TN ) was changed according to the process, there was a problem that can not respond to this change.

The present invention provides a PMO transistor of the bit line precharge voltage generator to cope with a change in the bit line precharge voltage as the threshold voltages of the NMOS and PMOS transistors change. The ratio of the same size as the ratio of the NMOS transistor size is applied to the inverter for detecting the bit line precharge voltage and the threshold voltage, and the transistor of the memory cell to cope with the change in the threshold voltage of the memory cell according to the process. An operating voltage detection circuit of a memory cell in which a size is applied to an NMOS transistor to cope with a process change is provided.

1 is an operation voltage detection circuit diagram of a memory cell of the present invention, as shown therein, a decoder 1 for outputting a signal W? To decode the address ADD under pressure to cause a delay, and an address to be input. A dummy decoder 2 for decoding the signal ADD and outputting a signal D? Having the same delay as the output time W? Of the decoder 1, the decoder 1 and the dummy decoder 2 A word line 3 and a dummy word line 4 which are operated by signals W ø and D ø outputted by the output lines, and output constant delay signals W 1 and D 1, respectively, and the word line 3. The memory cell 5 which is operated according to the delay signal W1 from the memory cell 5 to transmit the stored data to the bit line BL, and the output signal D1 of the dummy word line 4 is transferred to the NMOS transistor MN1. In addition to the gate, the source of the NMOS transistor MN1 is applied to the source by the inverter I1. The lane is applied to the gate of the connected NMOS transistor NIN2, and the signal SR output from the source and drain joint connection points of the NMOS transistors MN1 and MN2 is detected by the inverter I2. And a sense amplifier 7 which is operated by the output of the voltage detector 6 and the output of the operating voltage detector 6 to sense and amplify the data of the memory cell 5.

The operation and effect of the present invention configured as described above will be described with reference to the waveform diagrams shown in (a) to (d) of FIG. 2.

First, when the address ADD is input to the decoder unit 1 and the dummy decoder unit 2 at a high level as shown in (a) of FIG. 2, in the decoder unit 1, the word signal W? Reaches the gate of the memory cell 5 and simultaneously generates a dummy signal D? And the dummy decoder 2 digitizes the dummy signal to have the same delay as the word signal W? Of the decoder 1. (Dø) is generated. The generated word signal Wø reaches the bit line precharge voltage and the memory cell threshold voltage detection unit 6 via the dummy word line 4. In this case, the word line 3 and the dummy word line 4 are generated. The output signals W1 and (D1) from V1 have the same delay.

Here, in the case where the memory cell 5 uses one transistor and one cap, the data of the memory cell 5 must be loaded on the bit line BL when the word signal W1 is in a high state. Enable it to detect and amplify the data.

If the sense amplifier 7 operates before the data of the memory cell 5 is loaded on the bit line BL, it may sense and amplify wrong information, which may cause a defect during the read operation.

Therefore, detecting a time point at which the data of the memory cell 5 is loaded on the bit line BL can minimize delays that may occur during a read operation.

Therefore, the word and dummy delay signals W? And D? From the decoder section 1 and the dummy decoder section 2 are TW? = TD? And from the word line 3 and the dummy word line 4, respectively. Since the signals W1 and D1 are TW1 = TD1, it is only necessary to detect a time when the memory cell 5 is turned on to find a time when the data of the memory cell 5 is loaded. Since the bit line BL is precharged to the bit line precharge voltage V _BLP in the precharge state, the turn-on voltage Von of the memory cell 5 is the threshold voltage of the memory cell 5. It is the sum of (V _IN ) and the bit line precharge voltage (V _BLP ). That is, Von = V _TN + V _BLP

Therefore, the turn-on voltage Von of the memory cell 5 is detected in the operation voltage detector 6 for detecting the bit line precharge voltage and the memory cell threshold voltage as follows. That is, as shown in FIG. 2B, when the voltage of the dummy delay signal D1 reaches the threshold voltage V _IN of the memory cell 5, the NMOS transistor MN1 is turned on and operates. As shown in FIG. 2 (c),? V (V _A -V _D1 ) = V _IN .

When the voltage of the signal A output from the source of the NMOS transistor MN1 reaches the bit line precharge voltage V _BLP , the output signal SR of the inverter 12 becomes (d) in FIG. 2. Change the phase at this voltage as Therefore, the timing at which V _SR operates is the same as the timing at which the dummy delay signal D1 reaches V _BLP + V _TN , and the output signal SR operates the sense amplifier 7 to operate the memory cell ( The data in 5) is detected and amplified.

As described in detail above, the present invention can accurately detect the time point at which a memory cell is turned on, thereby driving a sense amplifier to optimize a delay that may occur between a word line and a sense amplifier operation, regardless of process change. The bit line precharge voltage and the threshold voltage of the memory cell can be detected. As a result, the present invention can accurately detect not only the start point but also the end point of the operation of the memory cell, and as a result, it provides an advantage that the sense amplifier can be precisely driven only from the start point of the memory cell to the end point. do.

Therefore, the present invention is used for an important purpose in all device devices using DRAM memory cells and DRAM sense amplifiers.

Claims (1)

A word line connected to the gates of the output transistors of the memory cells to control bidirectional data transfer between the memory cells and the bit line, and a dummy word line formed in the same form as the word line to detect a driving time of the memory cell; A semiconductor memory comprising: a decoder (1) for decoding an input address (ADD) and outputting the word cell (W?) For driving the memory cell to the word line after a time corresponding to a propagation delay time of the memory cell; The dummy signal Dø for driving the dummy word line DWL synchronized with the word signal Wø by being delayed by the propagation delay time of the decoder 1 by decoding the address ADD to the dummy word line. A dummy decoder (2) for outputting, a sense amplifier (7) for sensing and amplifying data on a bit line output from the memory cell, and the bit line Precharge voltage on the bit line and the threshold of the memory cell are driven by a bit line precharge voltage generator having two transistors for precharging and a delayed dummy word signal D1 applied via the dummy word line. In order to detect the operating point of the memory cell 5 by detecting a voltage and to drive the sense amplifier accordingly as a result, A) is connected between a first voltage source and an arbitrary connection point and via the dummy word line. Driven by the delayed dummy word line signal D1, and connected between a first transistor having the same size as a transistor included in the memory cell, B) a second voltage source and the arbitrary connection point, and Complementary driving with the first transistor by the delayed dummy word signal D1 via the dummy word line. And a second transistor having an appropriate size compared to the size of the first transistor so as to match the ratio of the size of the two transistors of the precharge voltage generator, which is the bit line, and C) according to the voltage on the arbitrary connection point. An operating voltage detection circuit of a memory cell, comprising an operating voltage detection section comprising an inverter having a comparison function for selectively driving a sensor amplifier.