KR0123829B1 - Column decoder enable signal generator - Google Patents

Abstract

In a DRAM having a dummy bit line in a memory cell array, a column decoder enable signal generator detects the voltage level of the dummy bit line and uses it as column decode enable signal when data of the bit line is sensed, thereby removing unnecessary timing margin during sensing operation to improve access time. The column decoder enable signal generator includes a sensing amplifier for sensing and amplifying data of the bit line, a sensing amplifier enable signal generator for generating a signal which controls the operation of the sensing amplifier, a detector for detecting the voltage level of the dummy bit line, and a column decoder for selecting a cell corresponding to the column address using the output signal of the detector and column address output signal.

Description

Column Decoder Enable Signal Generator

1 is a circuit diagram of a conventional column decoder enable signal generator.

2 is a timing diagram showing a relationship between respective signals.

3 is a circuit diagram of a column decoder enable signal generator of the present invention.

4 is a timing diagram between signals according to the present invention.

5 is a circuit diagram of a bit line voltage detector used in the present invention.

* Explanation of symbols for main parts of the drawings

101 to 103: Delay circuit 104: Bit line voltage level detector

105: voltage detector 106: amplifier

107: output driver

The present invention relates to a column decoder enable signal generator. In particular, the DRAM (Dynamic Ramdom Access Memory) detects the voltage level of the dummy bit line during the sensing operation to determine the enable time of the column decoder. The present invention relates to a column decoder enable signal generator capable of determining the sensing degree of bit lines BL and / BL.

In general, a row address and a column address are used to access data in a memory device. At the same time as the Ras signal is enabled (low), the word line corresponding to the row address is enabled (high), and the cell data corresponding to the enabled word line is passed through the cell transistor to the bit line (BL, / BL). Cause a slight voltage difference. This minute voltage difference is amplified to the power supply voltage (Vcc) and ground voltage (Vss) levels using a bit line sense amplifier. In this case, the signal enabling the bit line sense amplifier is caused by enabling the sense amplifier enable signal θSg (delay) delayed from the ras signal.

The data of the bit lines BL and / BL amplified by the sense amplifier enable signal θSg may include data of the bit lines corresponding to the column addresses input by the output yi of the column decoder. / DB).

As described above, an access time of the memory data is determined according to a timing of turning on the output yi of the column decoder when the memory data is accessed.

1 is a circuit diagram of a conventional column decoder enable signal generator, the node N1 for inputting a ras signal, the inverter G1 connected between the node N1 and the node N2, and A delay circuit 101 connected between the node N2 and the node N3, an inverter G2 connected between the node N3 and the node N4, and the node N4 and the node N5. An inverter G3 connected therebetween, a first output terminal for outputting a sense amplifier enable signal θSg from the node N5, and an inverter G4 connected between the node N5 and the node N6. ), A delay circuit 102 connected between the node N6 and the node N7, an inverter G5 connected between the node N7 and the node N8, and the nodes N2 and N8. ) And a NAND gate G6 connected between the node N9 and a second output terminal for outputting a chip enable signal θCSB from the node N9, between the node N9 and the node N10. An inverter G7 connected to the A node N11 for inputting a column address output signal, a NAND gate G8 connected between the nodes N10, N11, and a node N12, and a node N11 and a node N13 connected between the node N11 and the node N13. An inverter G9 and a third output terminal for outputting the column decoder output signal yi from the node N13 are provided.

The operation of the conventional column decoder enable signal generator will be described with reference to the timing diagram of FIG. 2.

When the Ras signal is inputted and shifted low, the signal delayed for a predetermined time through the inverters G1 to G3 and the delay circuit 101 is transmitted to the first output terminal N5. Output (θSg). Accordingly, the sense amplifier is driven by the sense amplifier enable signal θSg to sense data of the bit lines BL and / BL.

The sense amplifier enable signal θSg combines the signal delayed for a predetermined time with the ras signal through the inverters G4 and G5 and the delay circuit 102 to output the chip enable signal θCSB. Done. The output chip enable signal θCSB is then combined with the column address output signal to form a column decoder output signal yi.

Accordingly, the column decoder is operated by the column decoder output signal yi to transfer the data sensed by the sense amplifier from the bit lines BL and BL to the data lines DB and / DB.

The conventional column decoder enable signal generator arbitrarily estimates the time at which sensing occurs in the sense amplifier to enable the column decoder using the signal (θCSB) in which the sense amplifier enable signal (θSg) is delayed.

In general, the enable time of the column decoder enables the column decoder when the voltage difference between the bit lines BL and / BL is about 1 Vth (Vth: threshold voltage). However, the sensing degree of the bit lines BL and / BL may vary depending on the operating environment, that is, the power supply voltage Vcc and the temperature. As a result, the timing of turning on the column decoder may not be known accurately, which requires a lot of timing margins, resulting in a burden of access time.

Accordingly, an object of the present invention is to provide a column decoder enable signal generator capable of accurately determining the degree of sensing of a bit line by determining an enable time of a column decoder.

In order to achieve the above object, the column decoder enable signal generator of the present invention includes a dummy bit line in a memory cell array to detect a voltage level of the dummy bit line during a sensing operation to determine an enable time of the column decoder. Implemented

Hereinafter, with reference to the accompanying drawings, the present invention will be described in more detail.

3 is a circuit diagram of a column decoder enable signal generator of the present invention, comprising: a node N4 for inputting a ras signal, an inverter G10 connected between the node N1 and a node N15, A delay circuit 103 connected between the node N15 and a node N16, an inverter G11 connected between the node N16 and a node N17, the node N17, and a node N18. Bit line voltage level connected between the inverter N12 connected between the inverter G12 and the node N18 for outputting the sense amplifier enable signal θSg, and the dummy bit lines N19 and N20 and the node N21. A detector 104, a bit line voltage level detector 104 connected between the node N21 and a node N22, an inverter G13 connected between the node N21 and a node N22, Inverter G14 connected between node N22 and node G23, between node N23 that outputs a chip enable signal θCSB, and between node N23 and node N24. Inverter G15, a node N25 for inputting a column address output signal, a NAND gate G16 connected between the nodes N24, N25, and node N26, the node N26, and a node. An inverter G17 connected between the N27 units and the node N27 for outputting a column decoder output signal.

The operation of the column enable signal generator of the present invention will be described with reference to the timing diagram of FIG.

When a ras signal is inputted to the node N14 and transitioned low, the sense amplifier enable signal is delayed for a predetermined time through the inverters G10 to G12 and the delay circuit 103. (θSg) becomes an output.

The dummy bit line DBL / DBL, which is the same as the normal bit line BL // BL, is placed in the cell array to detect the voltage level of the dummy bit line from the bit line voltage level detector 104. do. The chip enable signal θCSB is generated by the detection signal, and the column decoder is enabled by the chip enable signal θCSB to transfer data of the selected bit line to the data line DB // DB. do.

When the sense amplifier is driven by the sense amplifier enable signal θSg to sense the data of the bit line, one bit line of the dummy bit lines DBL and / DBL is at the power supply voltage Vcc level. The other one is changed to the ground voltage level (Vcc), and the voltage levels of the two dummy bit lines are detected by the bit line voltage detector.

5 is a circuit diagram of a bit line voltage detector used in the present invention, a voltage detector 105 for sensing a voltage level of the dummy bit line, an amplifier 106 for amplifying a voltage output from the voltage detector, And an output driver 107 for buffering the data from the amplifier and transferring the data to the output terminal.

The voltage detector is connected between a power supply voltage Vcc and a node N14 and is connected between a PMOS transistor Q1 having a gate connected to the ground voltage Vss and the node N14 and a bit line precharge voltage VBLP. NMOS transistor Q2 connected and whose gate is connected to the authentic dummy bit line DBL, and the node N14 and the bit line precharge voltage VBLP are connected, and a gate is connected to the maintenance dummy bit line / DBL. A voltage detector 105 composed of an NMOS transistor Q3, and a PMOS transistor Q4 connected between a power supply voltage Vcc and a node N15 and whose gate is connected to the node N14, and the node N15. And a PMOS connected between the ground voltage Vss and a gate connected to the NMOS transistor Q6 connected to the node N15, a power supply voltage Vcc and a node N6, and a gate connected to the ground voltage Vss. Connected between a transistor Q5 and the node N16 and a ground voltage Vss. An amplifier 106 composed of an NMOS transistor Q7 having a gate connected to the node N15, and an inverter G10 connected between the node N16 and the node N18, and the node N18 and the node. An output driver comprising an inverter G11 connected between N19 and an output terminal for outputting a detector signal from the node M19.

Referring to the operation of the circuit, the authentic dummy bit line signal DBL and the complement dummy bit line signal / DBL are inputs of gates of two NMOS transistors having a bit line precharge voltage Vblp as a source. Before the sensing occurs, the dummy bit lines DBL and / DBL have a bit line precharge voltage Vblp level. When sensing occurs, the dummy bit lines DBL and / DBL select a power supply voltage Vcc to a ground voltage Vss, and have a dummy line precharge voltage Vblp + threshold voltage Vth. The node N14 is discharged from the power supply voltage Vcc to the bit line precharge voltage Vblp by the bit lines DBL and / DBL, thereby turning on the PMOS transistor Q4. Accordingly, the NMOS transistors Q6 and Q7 are operated to bring the detector signal from the output terminal M19 low. The chip enable signal θCSB of FIG. 3 is generated by the signal of the detector, and the column decoder is enabled by the chip enable signal θCSB to transfer data of the selected bit line to the data line.

When the column decoder enable signal generator of the present invention described above is implemented in the semiconductor device, unnecessary margin is sensed during the sensing operation by enabling the column decoder by detecting the voltage level of the dummy bit line during the sensing operation of the DRAM. It is possible to obtain the effect of eliminating the problem and improving the access time.

Claims (5)

A semiconductor memory device comprising: a bit line and a dummy bit line for transferring data stored in a cell array, a sense amplifier for sensing and amplifying data of the bit line, and a signal for controlling an operation of the sense amplifier. Selecting a cell corresponding to the column address by using a sense amplifier enable signal generating means for detecting the voltage level of the dummy bit line, an output signal and a column address output signal from the detecting means; And a column decoder means for the column decoder. 2. The column decoder of claim 1, wherein the sense amplifier enable signal generating means generates a signal for enabling the sense amplifier after a predetermined time elapses after the Ras signal is low. Enable signal generator. The method of claim 1, wherein the detecting means comprises: a voltage detector for sensing a voltage level of the dummy bit line, an amplifier for amplifying a voltage output from the voltage detector, and buffering data from the amplifier to an output terminal. And a output driver for transmitting. 4. The PMOS transistor (Q1) according to claim 3, wherein said detecting means is connected between a power supply voltage (Vcc) and a node (N14) and whose gate is connected to a ground voltage (Vss). A NMOS transistor Q2 connected between the voltage VBLP and a gate connected to the dummy bit line DBL, the node N14 and the bit line precharge voltage VBLP, and a gate connected to the dummy bit line DB / A voltage detector 105 composed of an NMOS transistor Q3 connected to a DBL, a PMOS transistor Q4 connected between a power supply voltage Vcc and a node N15 and whose gate is connected to the node N14, and The node is connected between the node N15 and the ground voltage Vss, and the gate is connected between the NMOS transistor Q6 connected to the node N15, the power supply voltage Vcc and the node N16, and the gate is connected to the ground voltage Vss. Is connected between the PMOS transistor Q5 and the node N16 and the ground voltage Vss An amplifier 106 comprising a NMOS transistor Q7 whose gate is connected to the node N15, and an inverter G10 connected between the node N15 and the node N18, the node N18 and And an output driver comprising an inverter (G11) connected between the nodes (N19) and an output terminal for outputting a detector signal from the node (N19). The method according to claim 1, wherein the column decoder means comprises: inverters G13 to G15 connected in series between the output line N21 and the node N24 of the detector, a node N25 for inputting a column address output signal, From the NAND gate G16 connected between the nodes N24 and N25 and the node N26, the inverter G17 connected between the node N26 and the node N27, and from the node N27. A column decoder enable signal generator comprising an output terminal (yi) for outputting data.