KR100669548B1 - Non-volatile ferroelectric memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile ferroelectric memory, and in particular, discloses a technique for accurately detecting a reference level of cell data using a reference cell in a column direction. The present invention includes a columnar reference generator in a cell array block, writes a data row value in one reference subcell array, and writes a data high value in another reference subcell array. The average value of the data stored in the reference subcell array is obtained and supplied as the reference value of the sense amplifier.

Description

Non-volatile ferroelectric memory

1 is a block diagram of a nonvolatile ferroelectric memory according to the present invention;

FIG. 2 is a detailed circuit diagram of the main bit line pull-up control unit of FIG. 1. FIG.

3 is a detailed circuit diagram illustrating a main bit line sensing rod unit of FIG. 1.

FIG. 4 is a detailed circuit diagram of the column select array unit of FIG. 1. FIG.

FIG. 5 is a detailed circuit diagram of the subcell array of FIG. 1. FIG.

FIG. 6 is a detailed configuration diagram illustrating the cell array block and the reference generator of FIG. 1. FIG.

7 and 8 are detailed circuit diagrams of the reference subcell array of FIG.

FIG. 9 is a detailed circuit diagram illustrating a reference buffer unit of FIG. 1. FIG.

FIG. 10 is an operation waveform diagram illustrating a reference subcell array and a reference buffer unit of FIG. 6. FIG.

11 is another embodiment of a nonvolatile ferroelectric memory in accordance with the present invention.

12 is an operation timing diagram of a nonvolatile ferroelectric memory in write mode according to the present invention;

13 is an operation timing diagram of a nonvolatile ferroelectric memory in read mode according to the present invention;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile ferroelectric memory. In particular, in a cell array having a hierarchical bit line structure, a reference level of a cell data can be accurately detected using a reference cell in a column direction.

In general, the nonvolatile ferroelectric memory, or ferroelectric random access memory (FeRAM), has a data processing speed of about DRAM (DRAM) and is attracting attention as a next-generation memory device due to its characteristic that data is preserved even when the power is turned off. have.

The FeRAM is a memory device having a structure almost similar to that of a DRAM, and uses a ferroelectric material as a capacitor material to utilize high residual polarization characteristic of the ferroelectric material. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

Description of the above-described FeRAM has been disclosed in Korean Patent Application No. 2001-57275 filed by the same inventor as the present invention.

When sensing cell data in such a conventional nonvolatile ferroelectric memory, the level of the sensing reference voltage should be set to an appropriate level.

However, as the chip operating voltage of FeRAM became low, the level of the reference voltage for sensing the cell gradually decreased. When the sensing voltage level of the cell data is low, the voltage margin with the reference voltage becomes small, and data determination becomes difficult.

In addition, there is a problem that the sensing margin is reduced by the voltage level variation of the reference voltage itself. Accordingly, there is a problem in that the FeRAM chip having a 1T1C (1transistor, 1capacitor) structure realizes a high density of memory capacity and a high operating speed is difficult.

The present invention has been made to solve the above problems, and an object thereof is to accurately detect a reference level change of cell data due to temperature using a reference cell in a column direction.

The nonvolatile ferroelectric memory of the present invention for achieving the above object includes a plurality of sub bit lines selectively connected to the main bit line, and converts the sensing voltage of the sub bit line into a current to induce the main bit line sensing voltage. A nonvolatile ferroelectric memory control device including a multi-bitline structure cell array, comprising: a plurality of reference generators for controlling a reference voltage level of data read from a subcell array block including a nonvolatile ferroelectric element Cell array blocks; A common data bus for inputting / outputting data applied from a plurality of cell array blocks; A reference buffer unit for averaging and buffering different output data of the reference generator applied through the common data bus; And a sense amplifier array configured to sense and amplify the output data of the subcell array block applied through the common data bus based on the output value applied from the reference buffer unit.

In addition, the present invention includes a cell array of a multi-bit line structure including a plurality of sub bit lines selectively connected to the main bit line and converting the sensing voltage of the sub bit line into a current to derive the main bit line sensing voltage. A nonvolatile ferroelectric memory control device, comprising: a plurality of cell arrays including a reference generator for generating a plurality of multi-level reference voltages for controlling reference voltage levels of data read from a subcell array block including a nonvolatile ferroelectric element block; A common data bus for inputting / outputting data applied from a plurality of cell array blocks; A plurality of reference buffer units configured to generate a plurality of reference output signals by averaging a plurality of different output data of the reference generator applied through a common data bus; And a sense amplifier array configured to sense and amplify output data of a subcell array block applied through a common data bus based on a plurality of output values applied from the plurality of reference buffer units.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is a block diagram of a nonvolatile ferroelectric memory according to the present invention.

The present invention includes a cell array block 100, a common data bus 200, a data bus 210, a reference bus 220, a reference buffer unit 300, and a sense amplifier array unit 400. Here, the cell array block 100 includes the main bit line (MBL) pull-up control unit 110, the MBL sensing load unit 120, the sub cell array 130, the column select array unit 140, and the reference generator 150. It is provided.

Each cell array block 100 includes a plurality of subcell arrays 130 for data storage. In particular, the sub cell array 130 of the present invention includes a sub bit line and a main bit line, and converts a sensing voltage of the sub bit line into a current to induce a main bit line sensing voltage to thereby induce a main bit line sensing voltage. Has an array.

Here, the plurality of cell array blocks 100 share a common data bus 200. The plurality of cell array blocks 100 output the cell data read through the data bus 210 to the sense amplifier array 400. The output signals of the plurality of reference generators 150 arranged in the column direction in the cell array block 100 are output to the reference buffer 300 through the reference bus 220.

In addition, the reference buffer 300 buffers the reference input signal REF_EN applied from the reference bus 220 according to the control signals CON1_EN and CON2_EN to supply the reference output signal REF_OUT to the sense amplifier array 400. The sense amplifier array 400 senses and amplifies data read from the cell array block 100 through the data bus 210 based on the reference output signal REF_OUT applied from the reference buffer 300.

FIG. 2 is a detailed circuit diagram of the MBL pull-up control unit 110 of FIG. 1.

The MBL pull-up control unit 110 includes a PMOS transistor P1 for pulling up the main bit line MBL upon precharging. The source terminal of the PMOS transistor P1 is connected to the supply voltage VCC applying terminal, the drain terminal is connected to the main bit line MBL, and the main bit line pull-up control signal MBLPUC is applied through the gate terminal.

3 is a detailed circuit diagram of the MBL sensing rod unit 120 of FIG. 1.

The main bit line sensing load unit 120 includes a PMOS transistor P2 for controlling the sensing load of the main bit line MBL. The source terminal of the PMOS transistor P2 is connected between the supply voltage VCC applying terminal, the drain terminal is connected to the main bit line MBL, and the main bit line control signal MBLC is applied through the gate terminal.

4 is a detailed circuit diagram illustrating the column select array unit 140 of FIG. 1.

The column select array unit 140 includes an NMOS transistor N1 and a PMOS transistor P3. Here, the NMOS transistor N1 is connected between the main bit line MBL and the common data bus 200 to apply the column select signal CSN through the gate terminal. In addition, the PMOS transistor P3 is connected between the main bit line MBL and the common data bus 200 so that the column select signal CSP is applied through the gate terminal.

FIG. 5 is a detailed circuit diagram illustrating the sub cell array 130 of FIG. 1.

Each main bit line MBL of the sub cell array 130 is selectively connected to one sub bit line SBL among the plurality of sub bit lines SBL. That is, when one of the plurality of sub bit line selection signals SBSW1 is activated, a corresponding NMOS transistor N6 is turned on to activate one sub bit line SBL. In addition, a plurality of cells C are connected to one sub bit line SBL.

The sub bit line SBL is pulled down to the ground level according to the turn-on of the NMOS transistor N4 when the sub bit line pull-down signal SBPD is activated. The sub bit line pull-up signal SBPU is a signal for controlling the power supplied to the sub bit line SBL. That is, at a low voltage, a voltage higher than the power supply voltage VCC is generated and supplied to the sub bit line SBL.

The sub bit line selection signal SBSW2 controls the connection between the sub bit line pull-up signal SBPU applying terminal and the sub bit line SBL according to the switching of the NMOS transistor N5.

In addition, the NMOS transistor N3 is connected between the NMOS transistor N2 and the main bit line MBL, and the gate terminal is connected to the sub bit line SBL. The NMOS transistor N2 is connected between the ground voltage terminal and the NMOS transistor N3, and the main bit line pull-down signal MBPD is applied through the gate to adjust the sensing voltage of the main bit line MBL.

6 is a detailed block diagram of the cell array block 100 and the reference generator 150 of FIG. 1.

The plurality of main bit lines MBL of the cell array block 100 are respectively connected to the plurality of sub cell arrays 130. The plurality of sub cell arrays 130 are connected to the common data bus 200 through the plurality of column selection array units 140 corresponding thereto. The common data bus 200 is connected to the plurality of sense amplifiers 400. In this case, the plurality of sense amplifiers 400 are connected in one-to-one correspondence with the plurality of main bit lines MBL.

In addition, the pair of reference main bit lines RMBL0 and RMBL1 of the reference generator 150 are connected to the reference subcell arrays 151 and 152 corresponding thereto. The reference subcell arrays 151 and 152 are connected to the reference bus 220 through the reference column select switching unit 153. The reference input signal REF_IN applied from the reference bus 220 is used as an input of the reference buffer unit 300.

The output signals of the reference buses RBUS0 and RBUS1 are connected to the input terminals of the reference buffer unit 300 and shorted to generate one reference input signal REF_IN. That is, the reference input signal REF_IN is an average value of a pair of data applied from the reference main bit lines RMBL0 and RMBL1.

The reference buffer unit 300 differentially amplifies the reference input signal REF_IN according to the control signals CON1_EN and CON2_EN and outputs the reference output signal REF_OUT to the respective sense amplifiers 400. The plurality of sense amplifiers 400 sense and amplify signals of the main bit lines MBL1 and MBL2 applied through the common data bus 200 using the reference output signal REF_OUT in common.

At this time, the reference buffer unit 300 amplifies the driving capability of the reference input signal REF_IN to output the reference output signal REF_OUT, and the reference input signal REF_IN and the reference output signal REF_OUT have the same voltage level.

FIG. 7 is a detailed circuit diagram of the reference subcell array 151 of FIG. 6.

The reference main bit line RMBL0 of the reference subcell array 151 is selectively connected to one reference subbitline RSBL0 of the plurality of reference subbitline RSBLs.

The NMOS transistor N8 is connected between the NMOS transistor N7 and the reference main bit line RMBL0, and a gate terminal thereof is connected to the reference sub bit line RSBL0. The NMOS transistor N7 is connected between the ground voltage terminal and the NMOS transistor N8, and the main bit line pull-down signal MBPD is applied through the gate terminal to adjust the sensing voltage of the reference main bit line RMBL0.

In addition, a plurality of reference cells RC is connected to one reference sub bit line RSBL0. The reference sub bit line RSBL0 is pulled down to the ground level according to the turn-on of the NMOS transistor N9 when the sub bit line pull-down signal SBPD is activated.

The sub bit line selection signal SBSW2 controls the connection between the sub bit line pull-up signal SBPU applying terminal and the reference sub bit line RSBL0 according to the switching of the NMOS transistor N10.

That is, the connection between the NMOS transistors N10 and N11 is blocked to block the transmission of the sub bit line pull-up signal SBPU to the reference sub bit line RSBL0. Accordingly, by blocking the sub bit line pull-up signal SBPU having the high level from being supplied to the reference sub bit line RSBL0, the plurality of reference cell RCs all store data “0”. Therefore, all data "0" can be stored in the reference subcell array 151.

FIG. 8 is a detailed circuit diagram of the reference subcell array 152 of FIG. 6.

The reference main bit line RMBL1 of the reference sub cell array 152 is selectively connected to one reference sub bit line RSBL1 among the plurality of reference sub bit lines RSBL.

The NMOS transistor N13 is connected between the NMOS transistor N12 and the reference main bit line RMBL1, and a gate terminal thereof is connected to the reference sub bit line RSBL1. The NMOS transistor N12 is connected between the ground voltage terminal and the NMOS transistor N13, and the main bit line pull-down signal MBPD is applied through the gate to adjust the sensing voltage of the reference main bit line RMBL1.

In addition, a plurality of reference cells RC is connected to one reference sub bit line RSBL1. The reference sub bit line RSBL1 is pulled down to the ground level according to the turn-on of the NMOS transistor N14 when the sub bit line pull-down signal SBPD is activated.

The sub bit line selection signal SBSW2 controls the connection between the sub bit line pull-up signal SBPU applying terminal and the reference sub bit line RSBL1 according to the switching of the NMOS transistor N15.

Accordingly, when the sub bit line pull-up signal SBPU is activated, the NMOS transistor N15 is turned on to supply a high level signal to the reference sub bit line RSBL1. Accordingly, the plurality of reference cells RC all store data “1”, and thus all of data “1” can be stored in the reference subcell array 152. At this time, the connection of the NMOS transistor N16 is cut off to prevent the signal of the reference sub bit line RSBL0 from being supplied to the reference main bit line RMBL1.

FIG. 9 is a detailed circuit diagram illustrating the reference buffer unit 300 of FIG. 1.

The reference buffer unit 300 includes a first buffer unit 310 and a second buffer unit 320. Here, the first buffer unit 310 differentially amplifies the reference input signal REF_IN and the reference output signal REF_IN according to the control signal CON1_EN to feedback and output the signals of the output nodes NO2 and NO4 to the second buffer unit 320, respectively.

The second buffer unit 320 differentially amplifies the output node NO2 and NO4 signals of the first buffer unit 310 according to the control signals CON1_EN and CON2_EN to output the reference output signal REF_OUT. Here, the control signal CON1_EN of the control signals CON1_EN and CON2_EN is activated first, and the control signal CON2_EN is activated after a predetermined time.

The configuration of the reference buffer unit 300 will be described in more detail as follows.

The first buffer unit 310 includes a first differential amplifier 311 composed of PMOS transistors P4 to P6 and NMOS transistors N17 to N19, and a second differential amplifier 312 composed of PMOS transistors P7 to P9 and NMOS transistors N20 to N22. It is provided.

Here, when the control signal CON1_EN is activated, the first differential amplifier 311 differentially amplifies the reference input signal REF_IN applied through the NMOS transistor N17 and the reference output signal REF_OUT applied through the NMOS transistor N18 when the control signal CON1_EN is activated. . When the control signal CON1_EN is inactivated, the PMOS transistor P6 is turned on to control the voltage levels of the nodes NO1 and NO2 in the same manner.

When the control signal CON1_EN is activated, the first differential amplifier 312 differentially amplifies the reference output signal REF_OUT applied through the NMOS transistor N20 and the reference input signal REF_IN applied through the NMOS transistor N21 when the control signal CON1_EN is activated. . When the control signal CON1_EN is inactivated, the PMOS transistor P9 is turned on to control the voltage levels of the nodes NO3 and NO4 in the same manner.

In addition, the second buffer unit 320 includes PMOS transistors P10 and P12, and NMOS transistors N23 to N28.

When the control signal CON1_EN is activated, the second buffer unit 320 turns on the NMOS transistor N25, and the second differential applied through the NMOS transistor N24 and the output signal of the first differential amplifier 311 applied through the NMOS transistor N23. Differential amplify the output signal of the amplifier 312. When the control signal CON2_EN is activated after a predetermined time and the control signal CON1_EN is activated, the NMOS transistors N27 and N28 are turned on to output the reference output signal REF_OUT.

FIG. 10 is an operational waveform diagram of the reference subcell arrays 151 and 152 and the reference buffer unit 300 of FIG. 6.

In the operation waveform diagram of FIG. 10, the reference sub bit line RSBL0 has a value of data "0", and the reference sub bit line RSBL1 has a value of data "1". Accordingly, the value of the reference main bit line RMBL0 is determined according to the value of the reference sub bit line RSBL0, and the value of the reference main bit line RMBL1 is determined according to the value of the reference sub bit line RSBL1.

Data stored in the reference main bit lines RMBL0 and RMBL1 are output to the input terminal of the reference buffer unit 300 through the reference bus 22. Therefore, the average value of the data stored in the reference main bit lines RMBL0 and RMBL1 becomes the reference input signal REF_IN.

The reference buffer unit 3000 differentially amplifies the reference input signal REF_IN by activating the control signal CON1_EN according to the sensing operation of the cell, and activates the control signal CON2_EN at the output time of the reference main bit lines RMBL0 and RMBL1. The reference output signal REF_OUT having the same value as is output.

Here, the reference main bit lines RMBL0 and RMBL1 have the same values as the main bit lines MBL0 and MBL1, and the reference sub bit lines RSBL0 and RSBL1 have the same values as the sub bit lines SBL0 and SBL1.

11 is another embodiment of a nonvolatile ferroelectric memory according to the present invention.

In the embodiment of FIG. 11 having multiple levels, the reference generator 150 includes a plurality of reference main bit line pairs RMBL0, RMBL1 to RMBLn0, and RMBLn1. Here, the reference main bit lines RMBL0 and RMBLn0 are connected to the reference subcell array 151 having the structure as shown in FIG. 7. The reference main bit lines RMBL1 and RMBLn1 are connected to the reference subcell array 152 having the structure shown in FIG. 8.

In addition, the reference subcell array 151 storing the value of data "0" and the reference subcell array 152 storing the value of data "1" are multiple level references through respective reference column switching units 153. It is connected to the bus 220.

Reference input signals REF_IN0 and REF_INn applied from the reference bus 220 are used as respective inputs of the plurality of reference buffer units 300. Accordingly, the output signals of the pair of reference buses RBUS0 and RBUS1 are connected to the input terminal of the reference buffer unit 0300 and shorted to generate one reference input signal REF_IN0. That is, the reference input signal REF_IN0 is an average value of data applied from the reference main bit lines RMBL0 and RMBL1.

The output signals of the pair of reference buses RBUSn0 and RBUSn1 are connected to the input terminal of the reference buffer unit 300 to be shorted to generate one reference input signal REF_INn. That is, the reference input signal REF_INn is an average value of data applied from the reference main bit lines RMBLn0 and RMBLn1.

In addition, the plurality of reference buffer units 300 differentially amplifies the plurality of reference input signals REF_IN0 to REF_INn and outputs the plurality of reference output signals REF_OUT0 to REF_OUTn to the respective sense amplifiers 400. The plurality of sense amplifiers 400 sense and amplify data applied from the main bit lines MBL1 and MBL2 through the common data bus 200 using the corresponding plurality of reference output signals REF_OUT0 to REF_OUTn.

In this case, the reference buffer unit 300 amplifies the driving capability of the plurality of reference input signals REF_IN0 to REF_INn and outputs the plurality of reference output signals REF_OUT0 to REF_OUTn. The plurality of reference input signals REF_IN0 to REF_INn and the plurality of reference output signals REF_OUT0 to REF_OUTn respectively have the same voltage level.

12 is a timing diagram of an operation in the write mode of the nonvolatile ferroelectric memory according to the present invention.

First, when the chip select signal CSB and the write enable signal / WE are low when the t1 period is entered, the write mode is activated. At this time, the sub bit line pull-down signal SBPD and the main bit line control signal MBLC are disabled low. Then, the main bit line pull-up control signal MBLPUC is enabled high.

Subsequently, when the word line WL and the plate line PL are enabled at the pumping voltage VPP level at the entry of the t2 section, the voltage level of the sub bit line SBL increases. The column select signal CSN is enabled to connect the main bit line MBL and the common data bus 200. At this time, the control signal CON1_EN of the reference buffer unit 220 transitions high, and after a predetermined time, the control signal CON2_EN is activated.

Next, upon entering the t3 section, which is a data sensing section, the sense amplifier enable signal SEN is enabled to apply cell data to the main bit line MBL. Then, the control signals CON1_EN and CON2_EN of the reference buffer unit 220 transition low.

Subsequently, upon entering the t4 period, the plate line PL is disabled low and the sub bit line select signal SBSW2 is enabled high. Then, the sub bit line SBL is disabled low.

In section t5, hidden data "1" is recorded. Upon entering the t5 section, the word line WL voltage rises and the sub bit line selection signal SBSW2 is enabled to the pumping voltage VPP level according to the enable of the sub bit line pull-up signal SBPU signal. Thus, the voltage level of the sub bit line SBL rises to the pumping voltage VPP level.

Next, in the period t6, valid data can be recorded in the cell according to the enable of the write enable signal / WE. Upon entering the t6 section, the plate line PL is enabled high again. Then, the sub bit line selection signal SBSW1 rises to the pumping voltage VPP level, and the sub bit line selection signal SBSW2 is disabled. At this time, the main bit line control signal MBLC is enabled high. The column select signal CSN is enabled to connect the main bit line MBL and the common data bus 200.

Therefore, a plurality of pieces of data can be written in the memory cell according to the voltage level applied to the sub bit line SBL and the main bit line MBL during the period in which the sub bit line selection signal SBSW1 is the pumping voltage VPP level.

Thereafter, the word line WL, the plate line PL, the sub bit line selection signal SBSW1, and the sub bit line pull-up signal SBPU are disabled when the t7 period is entered. Then, the sub bit line pulldown signal SBPD is enabled, and the sense amplifier enable signal SEN is disabled. In addition, the main bit line pull-up control signal MBLPUC is disabled to precharge the main bit line MBL to the power supply voltage VCC level. At this time, the column select signal CSN is disabled to block the connection of the main bit line MBL and the common data bus 200.

13 is an operation timing diagram of a nonvolatile ferroelectric memory in read mode according to the present invention.

First, in the read mode, the write enable signal / WE maintains the power supply voltage VCC level. The t2 and t3 sections are data sensing sections. In the t5 section, the hidden data "1" is recorded, and the data output valid section is maintained after the t5 section.

Subsequently, a plurality of multiple level data is restored in the t6 section. That is, while the sub bit line selection signal SBSW1 is at a high level, a voltage is applied to the sub bit line SBL and the main bit line MBL by the feedback decoder loop. As a result, data is restored to the memory cell.

In addition, the data level stored in the cell array block 100 may be sensed and output through the common data bus 200 during the t6 period.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

As described above, the present invention makes it possible to accurately detect the change of the reference voltage level of the cell data according to the change of temperature using the reference cell in the column direction.

In addition, the present invention implements the transfer path of the reference cell data in the same condition as the transfer path of the main cell data, so that it is possible to accurately detect the change in the reference voltage level of the cell data according to the position of the cell array block.

Claims (16)

A nonvolatile ferroelectric comprising a cell array of a multi-bit line structure including a plurality of sub bit lines selectively connected to a main bit line and converting the sensing voltage of the sub bit line into a current to induce the main bit line sensing voltage. In the memory control device, A plurality of cell array blocks including a reference generator for controlling a reference voltage level of data read from the sub cell array block including the nonvolatile ferroelectric element; A common data bus for inputting / outputting data applied from the plurality of cell array blocks; A reference buffer unit for averaging and buffering different output data of the reference generator applied through the common data bus; And And a sense amplifier array configured to sense and amplify output data of a subcell array block applied through the common data bus based on an output value applied from the reference buffer unit. The method of claim 1, wherein each of the plurality of cell array blocks A main bit line pull-up control unit which pulls up the main bit line according to a state of a main bit line pull-up control signal; A main bit line sensing rod unit controlling a sensing load of the main bit line according to a state of a main bit line control signal; A plurality of subcell array blocks each having the nonvolatile ferroelectric element; A column select array unit configured to selectively connect the main bit line and the common data bus according to a state of a column select signal; And And a pair of reference subcells for storing data of different values, and a reference generator for outputting data read from the pair of reference subcells to the reference buffer through a reference bus. Nonvolatile ferroelectric memory. The method of claim 2, wherein the reference generation unit A pair of reference main bit lines; The pair of reference subcell arrays including the nonvolatile ferroelectric elements to store data of different values and are connected in one-to-one correspondence with the pair of reference main bit lines; And And a reference column select switch for selectively connecting the pair of reference main bit lines and the reference bus according to the state of the column select signal. 4. The method of claim 3, wherein the first reference subcell array of the pair of reference subcell arrays is A first reference sub bit line coupled to the first reference main bit line; A plurality of reference cells connected to the first reference sub bit lines to store first data; A first driving element supplying a ground voltage to the first reference sub bit line upon activation of a sub bit line pull down signal; A second driving element supplying a ground voltage according to a main bit line pull-down signal; And And a third driver for supplying the output of the second driver to the first reference main bit line according to the voltage level of the first reference sub bit line. 4. The method of claim 3, wherein the second reference subcell array of the pair of reference subcell arrays A second reference sub bit line coupled to the second reference main bit line; A plurality of reference cells connected to the second reference sub bit lines to store second data; A fourth driving element configured to supply a ground voltage to the first reference sub bit line when the sub bit line pull down signal is activated; A fifth driving element configured to supply a high level voltage to the second reference sub bit line when the sub bit line selection signal is activated; A sixth driving element supplying a ground voltage according to the main bit line pull-down signal; And And a seventh driver for supplying the output of the sixth driver to the second reference main bit line according to the voltage level of the second reference sub bit line. 3. The apparatus of claim 2, wherein the reference buffer unit generates a reference input signal by averaging the data of different values applied from the pair of reference subcell arrays, and differentials a reference output signal having the same value as the reference input signal. And amplifying and outputting the amplified output to the sense amplifier array. The method of claim 6, wherein the reference buffer unit A first buffer unit for differentially amplifying the reference input signal and the reference output signal according to a first control signal activated when sensing cell data; And A second amplifier differentially amplifies the output of the first buffer unit when the first control signal is activated and outputs the differentially amplified reference output signal when the second control signal is activated after an activation time of the first control signal Nonvolatile ferroelectric memory characterized in that it comprises a buffer portion. The method of claim 7, wherein the first buffer portion A first differential amplifier for differentially amplifying the reference input signal and the reference output signal when the first control signal is activated and supplying a first output signal to the second buffer unit; And And a second differential amplifier configured to differentially amplify the reference input signal and the reference output signal to supply a second output signal to the second buffer when the first control signal is activated. A nonvolatile ferroelectric comprising a cell array of a multi-bit line structure including a plurality of sub bit lines selectively connected to a main bit line and converting the sensing voltage of the sub bit line into a current to induce the main bit line sensing voltage. In the memory control device, A plurality of cell array blocks including a reference generator for generating a plurality of multi-level reference voltages for controlling the reference voltage levels of data read in the sub-cell array block including the nonvolatile ferroelectric element; A common data bus for inputting / outputting data applied from the plurality of cell array blocks; A plurality of reference buffer units configured to generate a plurality of reference output signals by averaging a plurality of different output data of the reference generator applied through the common data bus; And And a sense amplifier array configured to sense and amplify output data of a subcell array block applied through the common data bus based on a plurality of output values applied from the plurality of reference buffer units, respectively. Ferroelectric memory. The method of claim 9, wherein each of the plurality of cell array blocks A main bit line pull-up control unit which pulls up the main bit line according to a state of a main bit line pull-up control signal; A main bit line sensing rod unit controlling a sensing load of the main bit line according to a state of a main bit line control signal; A plurality of subcell array blocks each having the nonvolatile ferroelectric element; A column select array unit configured to selectively connect the main bit line and the common data bus according to a state of a column select signal; And The reference generation includes a plurality of pairs of reference subcell arrays storing data of different values, and outputs the data of the different values read from the plurality of reference subcell array pairs through the reference bus to the reference buffer unit. Nonvolatile ferroelectric memory, characterized in that it comprises a portion. The method of claim 10, wherein the reference generation unit A plurality of reference main bitline pairs; The plurality of reference subcell array pairs including the nonvolatile ferroelectric element to apply data of different values to a pair of reference main bit lines, and to be connected in a one-to-one correspondence with a plurality of reference main bit line pairs; And And a reference column select switching unit for selectively connecting the plurality of reference main bit line pairs and the common data bus according to the state of the column select signal. The method of claim 11, wherein the first reference subcell array of the pair of reference subcell arrays A first reference sub bit line coupled to the first reference main bit line; A plurality of reference cells connected to the first reference sub bit lines to store first data; A first driving element supplying a ground voltage to the first reference sub bit line upon activation of a sub bit line pull down signal; A second driving element supplying a ground voltage according to a main bit line pull-down signal; And And a third driver for supplying the output of the second driver to the first reference main bit line according to the voltage level of the first reference sub bit line. 12. The method of claim 11, wherein the second reference subcell array of the pair of reference subcell arrays A second reference sub bit line coupled to the second reference main bit line; A plurality of reference cells connected to the second reference sub bit lines to store second data; A fourth driving element configured to supply a ground voltage to the first reference sub bit line when the sub bit line pull down signal is activated; A fifth driving element supplying a high level voltage to the second reference sub bit line when the sub bit line selection signal is activated; A sixth driving element supplying a ground voltage according to the main bit line pull-down signal; And And a seventh driver for supplying the output of the sixth driver to the second reference main bit line according to the voltage level of the second reference sub bit line. 10. The apparatus of claim 9, wherein the plurality of reference buffer units respectively generate a plurality of reference input signals by averaging data of different values applied from a pair of reference subcell array units of the plurality of reference subcell arrays. And amplifying the plurality of reference output signals having the same value as four reference input signals and outputting the plurality of reference output signals to the sense amplifier array, respectively. The method of claim 9 or 14, wherein each of the plurality of reference buffer unit A first buffer unit for differentially amplifying a reference input signal and a reference output signal according to a first control signal activated when sensing cell data; And A second amplifier differentially amplifies the output of the first buffer unit when the first control signal is activated and outputs the differentially amplified reference output signal when the second control signal is activated after an activation time of the first control signal Nonvolatile ferroelectric memory characterized in that it comprises a buffer portion. The method of claim 15, wherein the first buffer portion A first differential amplifier for differentially amplifying the reference input signal and the reference output signal when the first control signal is activated and supplying a first output signal to the second buffer unit; And And a second differential amplifier configured to differentially amplify the reference input signal and the reference output signal to supply a second output signal to the second buffer when the first control signal is activated.

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