KR20020002612A - Apparatus for generating reference voltage in ferroelectric memory device - Google Patents

Abstract

PURPOSE: A reference voltage generator of a ferroelectric memory device is provided, which can generate a reference voltage without switching in a polarization state by controlling a linear capacitor in a reference cell. CONSTITUTION: A reference cell(200) comprises a switching transistor(NT0) being connected between a negative bit line(/BL) and a storage node(SN1) and having a gate connected to a reference word line(RWL) and a linear capacitor(C2) connected between a reference plate line(RPL) and a storage node(SN1). And a reference cell(210) comprises a precharge transistor(NT2) being connected between the storage node(SN1) and a ground voltage terminal and having a gate connected to a reference precharge line(RPCG), a switching transistor(NT1) being connected between the negative bit line(/BL) and the storage node(SN2) and having a gate connected to the reference word line, and a ferroelectric capacitor(C3) being connected between the storage node(SN2) and the reference plate line and storing "low" data. And a precharge transistor(NT3) is connected between the storage node(SN2) and the ground voltage terminal and its gate is connected to the reference precharge line.

Description

Reference voltage generator for ferroelectric memory devices {APPARATUS FOR GENERATING REFERENCE VOLTAGE IN FERROELECTRIC MEMORY DEVICE}

The present invention relates to a nonvolatile ferroelectric semiconductor memory device using a ferroelectric capacitor memory cell, and more particularly, to a reference voltage generator for generating a reference voltage which becomes a reference voltage of a sense amplification operation upon 'reading' stored information.

In general, a data read operation of a ferroelectric semiconductor memory device reads information stored in a ferroelectric capacitor by sensing and converting a degree of change in charge amount induced by applying a voltage across a ferroelectric capacitor storing data.

Therefore, in order to sense and amplify the change in the charge amount induced by the sense amplifier in the read operation, a reference voltage having an intermediate level between the voltage value when reading data "1" and the voltage value when reading data "0" is determined. There is a need for a separate reference voltage generator.

1 is a circuit diagram of a reference voltage generator according to the prior art (US Pat. No. 5,424,975).

In the drawing, a conventional reference voltage generator includes a reference cell 100 in which "low" data is stored, a reference cell 110 in which "high" data is stored, and each reference in response to a reference precharge signal. Two transistors (N2, N3) for precharging the cells (100, 110) are provided to generate a reference voltage required for data read operation of the ferroelectric memory device. In this case, the reference cells 100 and 110 are composed of one ferroelectric capacitor C1 or C2 and one switching transistor N0 or N1, respectively, similarly to the ferroelectric memory cell, and are common to the sub bit line / BL. Connected.

Referring to Fig. 1, the operation of the conventional reference voltage generator will be described.

When the reference word lines RW1 and RPL1 are driven high to read the cell data stored in the reference cells 100 and 110, the reference cell 100 is driven. , Switching transistors N0 and N1 of 110 are turned on, so that charge sharing occurs between the ferroelectric capacitors C0 and C1 and the subbit line / BL. Will have a reference voltage level.

Thereafter, each data (low or high) is stored again in the ferroelectric capacitors C0 and C1 of the reference cells 100 and 110 to prepare for the next reference voltage generation.

In the conventional reference voltage generator as described above, the polarization state of the ferroelectric capacitor in the reference cell 110 in which the "high" data is stored among the two reference cells is switched from positive to negative or negative to positive, thereby increasing the number of switching. As a result, aging of the ferroelectric capacitor makes it difficult to generate a stable reference voltage.

The present invention stores the "low" data in one of the two reference cells so that the polarization state of the ferroelectric capacitor is not switched, and includes a linear capacitor in the other reference cell to adjust the linear capacitor. It is an object of the present invention to provide a reference voltage generator of a ferroelectric memory device capable of generating a stable reference voltage without switching.

1 is a circuit diagram of a reference voltage generator according to the prior art.

2 is a circuit diagram of a reference voltage generator according to an embodiment of the present invention.

3 is a configuration diagram of a ferroelectric memory device including the reference voltage generator of FIG. 2 according to an embodiment of the present invention.

4 is a signal diagram for driving the ferroelectric memory device of FIG.

5 is a characteristic curve of a ferroelectric capacitor.

* Description of the main parts of the drawing

200, 210: reference cell

C2: linear capacitor

NT0, NT1, NT2, NT3: Transistor

C3: ferroelectric capacitor

According to an aspect of the present invention, there is provided a reference voltage generator of a ferroelectric memory device, comprising: a first transistor connected between a first bit line and a first storage node and having a gate terminal connected to a reference word line; And a first reference cell having a linear capacitor connected between a reference plate line and the first storage node. A second transistor connected between the first storage node and a ground power supply terminal, and a gate terminal connected to a reference precharge line; A third transistor connected between the first bit line and the second storage node and having a gate terminal connected to the reference word line; And a second reference cell connected between the second storage node and the reference plate line and having a ferroelectric capacitor configured to store data of a first level at which polarization switching does not occur. And a fourth transistor connected between the second storage node and a ground power supply terminal, and a gate terminal connected to the reference precharge line.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

FIG. 2 is a circuit diagram of a reference voltage generator according to an exemplary embodiment of the present invention, and a switching transistor connected between a sub bit line / BL and a storage node SN1 and having a gate terminal connected to a reference word line RWL ( A reference cell 200 having a linear capacitor C2 connected between NT0) and a reference plate line RRP and a storage node SN1, a storage node SN1, and a ground power terminal. It is connected between the precharge transistor (NT2), the sub bit line (/ BL) and the storage node (SN2) connected to the reference precharge line (RPCG), and the gate terminal is connected to the reference word line (RWL). A reference cell 210 having a ferroelectric capacitor C3 connected between the switching transistor NT1 and the storage node SN2 and the reference plate line RPL and storing "low" data, and the storage node SN. 2) and a pre-charge transistor NT3 connected between the ground power supply terminal and the gate terminal connected to the reference precharge line RPCG.

First, when the reference word line RWL is "low", the reference precharge line RPCG is "high", and the reference plate line RPL is "low" in the standby state, the precharge transistor ( NT2 and NT3 are turned on so that the voltage difference across each of linear capacitor C2 and ferroelectric capacitor C3 is 0V, and ferroelectric capacitor C3 stores " low " data.

Next, when the reference precharge line RPCG is driven low, and then the reference word line RWL is driven high, and the reference plate line RPL is driven high, the switching transistors NT0 and NT1 are driven. Is turned on so that charge sharing occurs between the linear capacitor C2, the ferroelectric capacitor C2, and the sub bit line / BL, which causes the sub bit line / BL to have a reference voltage level.

3 is a configuration diagram of a ferroelectric memory device including the reference voltage generator of FIG. 2 according to an embodiment of the present invention.

The ferroelectric memory device of the present invention includes a reference voltage generator 300 in which the reference voltage generator of FIG. 2 is arrayed for each bit line, a memory cell array 310 including a ferroelectric capacitor, and stores data; And a sensing amplifier 320 for sensing and amplifying a minute voltage difference between the phosphorus BL1 to BL4 and the sub bit lines / BL1 to / BL4.

Here, the memory cell array unit 310 and the sense amplifier 320 have a general configuration, and a detailed description thereof will be omitted.

The reference voltage generator 300 is an array of the reference voltage generators of FIG. 2 for each of positive and negative bit lines, and the internal circuit of each reference voltage generator is the same as that of FIG. Detailed description of the connection relationship between the generating devices is omitted.

FIG. 4 is a signal diagram for driving the ferroelectric memory device of FIG. 3.

The operation of FIG. 3 will be described with reference to FIG. 4, wherein the ferroelectric memory device of FIG. 3 has an open bit line structure, and when the data is read from and written to a regular bit line, the sub bit line becomes a reference voltage line for sense amplification. When reading and writing data on the sub-bit line, the positive bit line becomes the reference voltage line. For convenience of explanation, the following describes the case of reading and writing data in a constant bit line.

When reading data stored in the ferroelectric capacitor FC of the memory cell, that is, the data of the ferroelectric capacitor FC is loaded on the bit line BL1 of the memory cell, and the reference voltage is loaded on the sub bit line / BL1. In operation 321, the voltage difference between the positive bit line BL1 and the sub bit line / BL1 may be sensed and amplified to read data stored in the ferroelectric capacitor FC.

To this end, first, when the reference precharge line (RPCG) is enabled to the "high" level, as in the section "A" of Figure 4, the linear capacitor and the ferroelectric of the reference voltage generator arranged in the reference voltage generator 300 The voltage difference across each of the capacitors is 0V, and "low" data is stored in the ferroelectric capacitor.

Thereafter, the reference precharge line RPCG is "low" at t1 of FIG. 4, and the word line TOPWL1 and the reference word line BOTRWL are enabled at "t" at t2, and then the plate line at t3. When (TOPPL1) and the reference plateline (TOPPL1) is enabled as "high", the data of the memory cell is loaded on the bit line (BL1) and the bit line (BL1) is ferroelectric capacitor (FC) through charge sharing According to the data stored in the V0 or V1 level, the sub-bit line / BL is the reference voltage level (VREF) through the charge sharing between the ferroelectric capacitor and the linear capacitor of the reference cell. Thereafter, the sense amplifier operates at t5 to sense and amplify the potential difference between the reference voltage VREF of the positive bit line and the sub bit line to determine whether the data of the ferroelectric memory cell is "0" or "1". The section from t6 in FIG. 4 is a section for restoring the data of the destroyed memory cell while reading the data.

As the polarization state of the ferroelectric capacitor provided in the reference cell is not switched during the read operation of the ferroelectric memory device, the aging of the ferroelectric capacitor does not occur. Qns maintains a level above V0 and below V1.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The reference voltage generator according to the present invention is configured to store "low" data in any one of two reference cells so that the polarization state of the ferroelectric capacitor is not switched, and includes a linear capacitor in the other reference cell. The adjustment of this linear capacitor has the effect of always producing a stable reference voltage without switching the polarization state.

Accordingly, further effects are expected to increase the reliability of the ferroelectric memory device having the reference voltage generator of the present invention.

Claims (2)

In the reference voltage generator of the ferroelectric memory device, A first transistor connected between the first bit line and the first storage node and having a gate terminal connected to the reference word line; And A first reference cell having a linear capacitor connected between a reference plate line and the first storage node; A second transistor connected between the first storage node and a ground power supply terminal, and a gate terminal connected to a reference precharge line; A third transistor connected between the first bit line and the second storage node and having a gate terminal connected to the reference word line; And A second reference cell connected between the second storage node and the reference plateline and having a ferroelectric capacitor storing data of a first level at which polarization switching does not occur; And A fourth transistor connected between the second storage node and a ground power supply terminal and having a gate terminal connected to the reference precharge line; Reference voltage generator comprising a. The method of claim 1, wherein the first level of data, A reference voltage generator that is low data.