KR100333697B1 - Ferroelectric random access memory - Google Patents

Abstract

The present invention is to provide a ferroelectric memory device with improved sensing margin and reliability by obtaining a reference voltage used during data sensing amplification without a dummy cell, the ferroelectric memory device of the present invention, A memory cell having a drain connected to a bit line and a word line connected to a gate, and a ferroelectric capacitor connected between the source and the plate line of the transistor; Sensing amplifying means for sensing and amplifying a voltage difference between the first bit line and a second bit line as a reference voltage line; Bit line pull-down means for pulling down the first bit line and the second bit line to a ground power supply voltage in response to a first control signal; Reference voltage generating means for generating a reference voltage corresponding to an intermediate level between data '0' and '1' using a plurality of MOS transistor threshold values; And reference voltage transfer means for transferring a reference voltage from the reference voltage generation means to the second bit line in response to a third control signal.

Description

Ferroelectric random access memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric random access memory (FeRAM), and more particularly, to a ferroelectric memory device which obtains a reference voltage used during data sensing amplification from a reference voltage generator without a dummy cell.

As is well known, capacitors using ferroelectric materials have a hysteresis curve in the relationship between the voltage across the capacitor and the amount of charged charge. FIG. 1A shows a symbol of a ferroelectric capacitor formed between terminals a and b, and FIG. 1B shows an equivalent of a ferroelectric capacitor, and FIG. 1C shows a relationship of charge amount according to voltage between both terminals a and b of a capacitor. It is. Referring to FIGS. 1A, 1B, and 1C, when there is no potential difference across the ferroelectric capacitors a and b, the amount of charge maintained by polarization exists in two states, 'a' and 'b', so that no power is supplied. It can store binary data. When the information of '1' is stored as 'A' when there is no potential difference between a and b terminals, and the information of '0' is displayed as 'I', the terminal b is read to read the stored information. When a certain voltage (V) is applied, the polarization at the 'ga' position is dragged to the 'da' state to generate the amount of charge as DELTA Q1. At this time, since the state of polarization changes beyond the voltage (Vc) that can cause switching, as shown in FIG. 1B, the nonlinear capacitance (Csw) component during switching and the linear capacitance (Cln) component when not switching are simultaneously present. . In addition, the polarization at the position of 'I' is also drawn to the state of 'D', and since no switching occurs, only the linear capacitance (Cln) exists and generates the amount of charge as ΔQ0. Due to the difference in the amount of charge caused by these two state changes, the ferroelectric capacitor is used as a storage means for the nonvolatile memory device.

2 is a circuit diagram corresponding to a core portion of a ferroelectric memory device according to the related art. In FIG. 2, a first bit line pair consisting of a right bit line bl0n and a sub bit line bl0bar, and a second bit line pair consisting of another right bit line bl1n and a sub bit line bl1bar are respectively connected. The circuits are shown.

Referring to FIG. 2, unit cells including one NMOS transistor and one ferroelectric capacitor are arrayed to form a cell array unit 130. Specifically, the NMOS transistor of the unit cell has a drain connected to the bit line and a gate connected to the word lines wl0, wl1 ... wln-2, wln-1, and the ferroelectric capacitor of the unit cell has a plate line. ) And the source terminal of the an-MOS transistor. Each bit line includes a bit line pull-down unit 110 for pulling down the bit line to the ground voltage in the standby state by the control signal pbl, and a positive bit line and a sub bit during read driving by the control signal. The sense amplifier 120 is configured to sense and amplify the voltage difference between the lines.

On the other hand, in order to read data from the cell, the data between the positive bit line and the sub bit line is sensed. In this case, when the unit cell connected to the positive bit line is selected, the sub bit line connected to the unselected cell is further selected. Since the reference voltage is received from the micelle 150, the voltage difference between the positive bit line and the sub bit line is sensed by the sense amplifier 120. At this time, the method of transferring the reference voltage to the sub bit line is implemented by driving the reference voltage transmitter 140 by the control signals dtg_even and dtg_odd.

In the dummy cell unit 150, the dummy positive bit line RBL is commonly connected to the first bit line pair bl0n and bl0bar, and the dummy sub bit line RBLB is connected to the second bit line pair bl1n and bl1bar. Are connected in common to each other, and two dummy cells DC1 and DC2 are connected between the dummy positive bit line RBL and the dummy sub bit line RBLB. In addition, the dummy positive bit line RBL and the dummy sub bit line RBLB include a transistor for pulling down the pair of dummy bit lines to the ground voltage in the standby state by the control signal prl, and the dummy by the control signal eq_rl. Transistors that equalize the bit line pairs are connected. Data "0" is always stored in the first dummy cell DC1 and data "1" is always stored in the second dummy cell DC2, so that the dummy word line rwl and the dummy plate line rpl are stored. When enabled and equalizing the dummy bit line pairs RBL and RBLB, a reference voltage corresponding to an intermediate level between '0' and '1' is transferred to the bit line.

However, as shown in FIG. 2, since the dummy cells use two dummy cells in a plurality of arrayed bit lines, the number of use of the dummy cell is increased as many as the number of memory cells are arrayed, but the number of use of the ferroelectric capacitor increases. As a result, there is a characteristic aging phenomenon in which the amount of charge charged to a capacitor gradually decreases, and thus the reference voltage induced from the dummy cell becomes unstable according to the frequency of use, which causes the sensing margin to drop and It is a big problem for reliability. 3 shows that the hysteresis curve of the ferroelectric capacitor changes with age.

The present invention has been made to solve the above problems, to provide a ferroelectric memory device with improved sensing margin and reliability by obtaining a reference voltage used in the data sensing amplification without a dummy cell, the reference voltage generator. do.

1A shows a symbol of a ferroelectric capacitor;

1B is an equivalent circuit diagram of a ferroelectric capacitor;

Figure 1c is a hysteresis curve showing the characteristics of the ferroelectric capacitor,

2 is a circuit diagram corresponding to a core portion of a ferroelectric memory device according to the prior art;

3 is a diagram illustrating a aging phenomenon, which is a characteristic of a ferroelectric capacitor;

4 is a circuit diagram corresponding to a core portion of a ferroelectric memory device according to an embodiment of the present invention;

FIG. 5 is a diagram showing timing and ferroelectric capacitors for each signal for reading data from a memory cell in FIG. 4; FIG.

6 is a circuit diagram of a reference voltage generator according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

110: bit line pull-down unit 120: detection amplifier

130: cell array unit 140: reference voltage transfer unit

250: reference voltage generator

A ferroelectric memory device of the present invention for achieving the above object comprises: a memory cell having a transistor having a drain connected to a first bit line and a word line connected to a gate, and a ferroelectric capacitor connected between a source and a plate line of the transistor; Sensing amplifying means for sensing and amplifying a voltage difference between the first bit line and a second bit line as a reference voltage line; Bit line pull-down means for pulling down the first bit line and the second bit line to a ground power supply voltage in response to a first control signal; Reference voltage generating means for generating a reference voltage corresponding to an intermediate level between data '0' and '1' using a plurality of MOS transistor threshold values; And reference voltage transfer means for transferring a reference voltage from the reference voltage generation means to the second bit line in response to a third control signal.

The present invention having such a configuration is characterized by making a reference voltage generator instead of a dummy cell to make a reference voltage necessary for sensing, and to secure the reliability of the device by preventing the life of the device generated by the dummy cell is shortened. Since it does not use dummy cells, the chip area can be significantly reduced, and the operation of equalizing the dummy bit lines to make the intermediate value between '0' and '1' can be eliminated. Can be.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4 is a circuit diagram corresponding to a core portion of a ferroelectric memory device according to an embodiment of the present invention, and is connected to a first bit line pair bl0n and bl0bar and a second bit line pair bl1n and bl1bar. The bit line pull-down unit 110, the sense amplifier 120, the cell array unit 130 and the reference voltage transfer unit 140 has the same configuration as in the prior art, the dummy cell unit (Fig. Instead of 150 of 2, the reference voltage generator 250 is replaced. The reference voltage generator 250 generates a reference voltage having an intermediate value between data '0' and '1' by using a threshold voltage value of a MOSFET.

Fig. 5 is a diagram showing the timing of each signal for reading data from a memory cell and the state of the ferroelectric capacitor. Referring to FIG. 5, an operation for reading data from the memory cell 135 in FIG. 4 will be described as an example.

As the transistors constituting the bit line pull-down unit 120 are turned on by the control signal pbl in the standby state, all the bit lines are precharged to the ground voltage. When an address signal (not shown in the figure) is input to read data stored in the memory cell 135, the control signal pbl becomes' low 'and all the bit lines, including the bit line bl0n, are in a floating state (' a in FIG. 5). ' section).

The gate of the selected cell transistor is then driven high through the word line wl0. At this time, if the plate line plate is also driven at 'high', the polarization state of the ferroelectric capacitor is 'A' (if data '1' is stored) or 'I' ('0' of data is stored in FIG. 1C). ) To the state of 'da' and induces a change in the charge amount of? Q0 or? Q1. At that time, the control signal dtg_odd is set to 'high' to transfer the reference voltage from the reference voltage generator 250 to the bit line bl0bar ('b' section in FIG. 5).

Subsequently, when the sensing amplifier 120 is activated by activating the sensing amplifier enable signal sa_en, the data '0' or '1' and the reference voltage ('0' and '1' intermediate levels) of the bit line bl0 are turned on. The detection and amplification determines whether the data of the memory cell is '0' or '1' ('c' section of FIG. 5).

Subsequently, when the plate line plate is 'low' and the word line WLO is 'low' again while the sensing amplifier 120 is enabled, the data is restored to the memory cell 135 (Fig. 5). 'd' section).

6 is a circuit diagram illustrating a reference voltage generator 250 according to an embodiment of the present invention. The reference voltage generator 250a and the reference voltage Vref for generating a reference voltage using the threshold voltage of the MOS transistor are shown in FIG. It is composed of a current mirror type driving unit 250b to have sufficient driving capability when loaded on the bit line. The reference voltage generating circuit unit 250a according to the present embodiment includes two PMOS transistors P0 and P1 diode-connected between the node A and the power supply terminal, and an NMOS transistor between the node A and the ground power supply. Since the structure is implemented as (N9), the number of transistors to be connected may vary depending on the size of the transistor.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention obtains a reference voltage necessary for data sensing of a cell through a reference voltage generator, thereby reducing the area occupied by the dummy cell since the dummy cell having the same configuration as that of the memory cell is not required. Since it is not necessary to read and equalize '0' and '1' from the above, the time can be shortened and the life of the chip due to aging of the dummy cell can be prevented.

Claims (1)

A memory cell having a transistor having a drain connected to a first bit line and a word line connected to a gate, and a ferroelectric capacitor connected between the source and the plate line of the transistor; Sensing amplifying means for sensing and amplifying a voltage difference between the first bit line and a second bit line as a reference voltage line; Bit line pull-down means for pulling down the first bit line and the second bit line to a ground power supply voltage in response to a first control signal; Reference voltage generating means for generating a reference voltage corresponding to an intermediate level between data '0' and '1' using a plurality of MOS transistor threshold values; And Reference voltage transfer means for transferring a reference voltage from said reference voltage generating means to said second bit line in response to a third control signal, The reference voltage generating means has a reference voltage generating circuit for generating a reference voltage using the threshold voltage of the MOS transistor and a sufficient driving capability when transferring the reference voltage from the reference voltage generating circuit portion to the second bit line. Current mirror type driver Ferroelectric memory device comprising a.