KR100373352B1 - memory cell in FeRAM device having resistance for compensation of voltage-down in cell storage node - Google Patents

Abstract

The present invention relates to a ferroelectric memory device, and an object of the present invention is to provide a ferroelectric memory device for compensating for a leakage current generated from a storage node of a cell including a ferroelectric capacitor to generate a voltage drop in the storage node. According to an aspect of the present invention, a memory cell of a ferroelectric memory device, comprising: a switching transistor having a gate connected to a word line and a first junction connected to a bit line; A ferroelectric capacitor connected to a plate line for supplying a voltage of substantially one half level of a power supply, and a storage electrode connected to a second junction of the switching transistor; And a resistance element connected in parallel with the ferroelectric capacitor between the second junction and the plate line and having a resistance value for providing a current corresponding to the leakage current of the ferroelectric capacitor to the storage electrode of the ferroelectric capacitor. A memory cell of a ferroelectric memory device is provided.

Description

Memory cell in FeRAM device having resistance for compensation of voltage-down in cell storage node

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a ferroelectric memory device (FeRAM) using a ferroelectric material as a dielectric of a capacitor and using the capacitor as a means for storing information.

As is well known, capacitors using ferroelectric materials have a hysteresis curve in the relationship between the voltage across the capacitor and the amount of charged charge.

FIG. 1A shows a symbol of a ferroelectric capacitor formed between terminals a and b, and FIG. 1B shows a relationship of the amount of charge according to the voltage between both terminals a and b of the capacitor.

Referring to FIGS. 1A and 1B, unlike a general linear capacitor, even when there is no potential difference across ferroelectric capacitors a and b, since a certain amount of charge is maintained in two states of “a” or “b”, the supply of power is reduced. You can store binary data even if you do not have it. The reason for the above is that the characteristics of the ferroelectric material cause polarization of the atomic arrangement of the ferroelectric material when an electric field is applied to the material and the electric field is cut off.

When the information of "1" stored when there is no potential difference between a and b terminals is set to "a" state, and the information of "0" is set to "b" state, the terminal b is read to read the stored information. When a sufficiently large negative voltage (-V) is applied, the polarization at the "high" position is dragged to the "high" state to generate an amount of charge as ΔQ1. In addition, the polarization at the "I" position is also dragged to the "multi" state to generate the amount of charge ΔQ0. Due to the difference in the charge amount caused by these two state changes, the ferroelectric capacitor is used as a storage means of the nonvolatile memory device.

Many technologies for implementing a memory device using the above characteristics of the ferroelectric capacitor have been published. FIG. 2 shows an example of the prior art, and shows a unit cell circuit diagram of a ferroelectric memory composed of one switching NMOS transistor and one ferroelectric capacitor 1T1C.

Referring to FIG. 2, the unit cell 10 includes a switching NMOS transistor 11 and a switching node in which a word line WL0 is connected and a bit line BL is connected at one end (source) to access a cell. It consists of a ferroelectric capacitor connected between the other end (drain) of the MOS transistor 11 and the plate line PL.

The ferroelectric unit cell 10 having the above-described configuration receives a signal from which a row address signal and a column address signal are decoded to the word line WL0 and the bit line BL, respectively, and is applied to the cell plate line PL. The memory device may perform a memory function with the changed charge amount in the selected ferroelectric capacitor 12 by receiving the plate signal.

As described above, in the ferroelectric memory cell, an electric field is applied across the ferroelectric capacitor in order to detect or store the amount of charge stored in the ferroelectric capacitor, and a restore operation is required to return the once read memory cell to its original state. For this reason, it is necessary to drive a plate line in order to operate and read or write ferroelectric memory cells. However, many ferroelectric capacitors connected to the plate line have a large capacitance, and the resistance of the plate line is also larger than that of the metal wires. Therefore, the RC time constant increases, causing a large delay in the signal when driving the plate line, thereby preventing high-speed operation. It becomes a factor.

3 illustrates an improved prior art ferroelectric memory device which operates a cell by fixing a plate line to 1/2 supply voltage (1/2 Vcc) in order to solve the problems of the prior art as described above. The circuit of the core portion is shown.

Referring to Fig. 3, an improved conventional ferroelectric memory device configuration and its operation (read drive) will be described.

First, as described above, the memory cell 30 includes a switching NMOS transistor 32 having one end connected to a positive bit line bl and a gate connected to a word line wl, and the NMOS. The ferroelectric capacitor 31 is connected between the other end (drain) of the transistor 32 and the plate line PL.

The precharge unit 40 controlled by the precharge signal blpcg is connected to the positive bit line bl and the sub bit line blb. The precharge unit 40 grounds the bit line in the precharge mode. It is configured to precharge to a voltage level.

As such, when the positive bit line bl and the sub bit line blb are precharged, the reference voltage is transferred to one of the positive bit line bl and the sub bit line blb. The reference voltage generator 60 is connected to bl) and the sub bit line blb through the reference voltage transfer controller 50. The reference voltage transfer control unit 50 carries a reference voltage on the sub bit line blb when the control signal even is activated and a reference voltage on the positive bit line bl when the control signal odd is activated. It consists of a switching transistor gated at odds. Here, it is assumed that the reference voltage is transferred to the sub bit line blb.

On the other hand, when the word line wl is turned on at the same time as the reference voltage is transmitted to the sub bit line blb, charge sharing occurs between the bit line bl and the data stored in the storage node SN. As a result, the positive bit line bl and the storage node SN of the cell are at the same potential.

Subsequently, when the control signal sap is activated, the potentials of the positive bit line bl and the sub bit line blb are separated by logic "high" and "low" by the sense amplifier 10, and then output buffers (not shown). Will be printed).

Subsequently, the positive bit line bl and the sub bit line blb having “high” and “low” have hysteresis characteristics as described above with reference to FIG. 2 since the plate line PL is fixed at 1/2 Vcc. In order to comply with it, i.e., to make the voltage difference across the ferroelectric capacitor 31 "0V" and return it to its original state, the positive bit line bl and the sub bit line blb in response to the control signal start and the equalizing signal eq. An equalizing unit 20 is configured to equalize to 1/2 Vcc.

After that, the word line wl is turned off and the positive and negative bit lines bl and blb are again precharged to the ground voltage to complete one cycle.

The structure formed by fixing the plate line PL as described above is referred to as NDP (Non-Driven Plate, IEEE Solid-State Circuit, Vol. 31, No. 11, Novemver 1996, pp1625-pp1633) structure, and uses the NDP structure. This eliminates the need to drive the plateline PL, which speeds up the overall operating speed of the ferroelectric memory.

However, in the conventional ferroelectric memory device as described above, as shown in FIG. 4, since a resistive component is present at the junction of the storage node SN connected to the switching nMOS transistor 32 and the ferroelectric capacitor 31, the word line ( The leakage current is generated in the standby state where wl) is turned off, and the potential of the storage node SN gradually decreases at 1/2 Vcc due to the leakage current. As a result, the potential reduction of the storage node SN generates a potential difference across the ferroelectric capacitor 31, causing loss of stored data.

Therefore, conventionally, in order to compensate for this, a refresh operation is performed in which the word line wl is frequently turned on. This refresh driving causes a large power loss.

The present invention has been made to solve the problems of the prior art as described above, to prevent a reduction in the amount of charge caused by the leakage current in the memory cell storage node of the ferroelectric memory device to eliminate the need for a refresh operation, thereby power consumption SUMMARY OF THE INVENTION An object of the present invention is to provide a memory cell of a ferroelectric memory device capable of suppressing the "

1A shows a symbol of a ferroelectric capacitor.

1B is a hysteresis curve showing the characteristics of a ferroelectric capacitor.

2 is a unit cell circuit diagram of a ferroelectric memory according to the prior art.

3 is a circuit diagram showing a core portion of a ferroelectric memory device according to the prior art.

4 illustrates the presence of junction capacitance and junction resistance in a storage node in the circuit of FIG.

5 is a circuit diagram illustrating a core portion of a ferroelectric memory device according to an embodiment of the present invention.

6 is a unit cell circuit diagram of a ferroelectric memory according to the present invention;

7 is a control signal timing diagram of FIG. 5 in accordance with the present invention;

* Brief description of symbols for the main parts of the drawings

100: sense amplifier unit 200: bit line equalization unit

300: memory cell unit 400: bit line precharge unit

500: reference voltage transfer control unit 600: reference voltage generator

According to an aspect of the present invention for achieving the above object, a memory cell of a ferroelectric memory device, comprising: a switching transistor having a gate connected to a word line and a first junction connected to a bit line; A ferroelectric capacitor connected to a plate line for supplying a voltage of substantially one half level of a power supply, and a storage electrode connected to a second junction of the switching transistor; And a resistance element connected in parallel with the ferroelectric capacitor between the second junction and the plate line and having a resistance value for providing a current corresponding to the leakage current of the ferroelectric capacitor to the storage electrode of the ferroelectric capacitor. A memory cell of a ferroelectric memory device is provided.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

5 is a circuit diagram illustrating a core portion of a memory cell according to an exemplary embodiment of the present invention, where 100 is a sense amplifier unit, 200 is a bit line equalization unit, 300 is a memory cell unit, 400 is a bit line precharge unit, and 500 Denotes a reference voltage transfer control unit, and denotes a reference voltage generator. Other components except for the memory cell unit 300 in the configuration of FIG. 5 are substantially the same as the prior art of FIG. 3.

FIG. 6 shows one of two memory cells of the memory cell unit 300 according to the present invention. The configuration is as follows. The word line wl is connected to the gate of the switching NMOS transistor 311 to control on-off, and the bit line bl is connected to one terminal (source) of the switching NMOS transistor 311. The other terminal (drain) of the switching NMOS transistor 311 is connected to the ferroelectric capacitor 301, and the other terminal of the ferroelectric capacitor 301 is connected to the plate line PL which is fixed at 1/2 Vcc and driven. And a high resistance 321 connected in parallel with the ferroelectric capacitor 301 between the plate line PL and the storage node SN.

As described above, when a high resistance is connected between the plate line PL and the storage node SN having a level of 1/2 Vcc, a minute current is supplied from the plate line PL toward the storage node SN. The amount of charge loss due to leakage current in the storage node SN generated when the line wl is turned off may be compensated for. The amount of current supplied to the storage node SN should be substantially equal to the leakage current. That is, if too much resistance is applied, the plate line PL and the storage node SN are electrically open to compensate for the voltage drop of the storage node SN. When the connection is made, the plate line PL and the storage node SN are shorted, which is not a problem when the word line wl is turned off, but when the word line wl is turned on Since the resistance is ignored, the 1/2 Vcc level of the plate line PL is loaded on the bit line BL as it is. This causes a problem in the sensing action by the sense amplifier, and outputs unwanted data. Therefore, the resistance should be connected to the appropriate value of the resistance, the resistance of the appropriate value will vary depending on the conditions, but the cycle of 300 ns (Cycle), the temperature of about 25 ℃ and the plate line level is approximately 500 at about 1.5V -Should have a resistance of 700 ㏀.

FIG. 7 is a control signal diagram for operating the core portion of the memory cell shown in FIG. 5, and the operation of the present invention will be described with reference to FIGS.

First, in the standby state, the precharge signal blpcg becomes 'high', precharges the positive and sub bit lines bl and blb to the ground level, and then sets the precharge signal blpcg to “low” to read the data stored in the cell. And the bit line precharge unit 400 is turned off, so that the positive and sub bit lines bl and blb are floated in the precharged state to 0 V. Thereafter, the first switching NMOS of the memory cell unit 300 is The word line wl0 connected to the drain terminal of the transistor 311 is "high" so that the first switching NMOS transistor 311 is turned on, and the charge stored in the ferroelectric capacitor 301 is stored in the positive bit line bl. When the positive bit line bl is changed, the reference voltage generated by the reference voltage generator 600 is loaded on the sub bit line blb at a similar time. Positive for applying the reference voltage generated in 600) The switching nMOS transistor 501 of the reference voltage transfer control unit 500 is turned on when the control signal even is applied as “high” to select the sub bit line blb among the tbl line and the sub bit line blb. Subsequently, when the sense amplifier enable signal sap is activated as "low", the signals of the positive bit line bl and the sub bit line blb are sensed and amplified by the detection amplifier unit 100 to "high" and "low". Then, the control signal start of the bit line equalizing unit 200 is applied as "high" in order to return the voltage difference across the ferroelectric capacitor 301 to "0V". At the same time, when the equalization signal eq is also applied as "high", the positive and sub bit lines bl and blb are precharged to 1/2 Vcc and equalized. After the equalization is completed, the control signal start and the equalization signal eq are turned off by applying "low", and then the word line signal (wl) is turned off by applying "low" and bit line free. Applying the charge signal blpcg to " high " ends the hysteresis curve as shown in FIG.

Thereafter, the bit line is precharged to the ground voltage again and enters the standby state. At this time, the storage node SN is compensated for the voltage drop due to the leakage current through the high resistance from the plate line PL.

Meanwhile, the present invention can be applied to not only memory cells but all cells using ferroelectric capacitors, such as reference cells of reference voltage generators. Thus, the technical idea of the present invention has been described in detail according to the preferred embodiment. It should be noted that the examples are illustrative only and not intended to be limiting. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention made as described above is stable and can perform fast operation by eliminating a separate operation such as refresh by further adding a high resistance to compensate for the loss of charge caused by the leakage current generated in the storage node of the memory cell in the standby state In addition, it is possible to reduce the loss of power and increase the area.

Claims (5)

delete In a memory cell of a ferroelectric memory device, A switching transistor having a gate connected to the word line and a first junction connected to the bit line; A ferroelectric capacitor connected to a plate line for supplying a voltage of substantially one half level of a power supply, and a storage electrode connected to a second junction of the switching transistor; And A resistance element connected in parallel with the ferroelectric capacitor between the second junction and the plate line and having a resistance value for providing a current corresponding to the leakage current of the ferroelectric capacitor to the storage electrode of the ferroelectric capacitor A memory cell of a ferroelectric memory device having a. The method of claim 2, A substantially half level of the power supply is 1.5V, and the resistance element has a resistance value of 500 to 700 kΩ. delete delete