US12095003B2 - Micro light emitting diode chip - Google Patents

Micro light emitting diode chip Download PDF

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Publication number
US12095003B2
US12095003B2 US17/489,799 US202117489799A US12095003B2 US 12095003 B2 US12095003 B2 US 12095003B2 US 202117489799 A US202117489799 A US 202117489799A US 12095003 B2 US12095003 B2 US 12095003B2
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light emitting
emitting diode
diode chip
micro light
doping region
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US20230008639A1 (en
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Hsin-Chiao Fang
Jyun-De Wu
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PlayNitride Display Co Ltd
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PlayNitride Display Co Ltd
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    • H01L33/14—
    • H01L33/025—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/816—Bodies having carrier transport control structures, e.g. highly-doped semiconductor layers or current-blocking structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/8215—Bodies characterised by crystalline imperfections, e.g. dislocations; characterised by the distribution of dopants, e.g. delta-doping
    • H01L2933/0016—
    • H01L33/0095—
    • H01L33/305—
    • H01L33/382—
    • H01L33/40—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/032—Manufacture or treatment of electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/822—Materials of the light-emitting regions
    • H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
    • H10H20/8242—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP characterised by the dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/831—Electrodes characterised by their shape
    • H10H20/8312—Electrodes characterised by their shape extending at least partially through the bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/832—Electrodes characterised by their material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Definitions

  • the disclosure relates to a chip, in particular to a micro light emitting diode chip.
  • the final process requires the electrode and the epitaxial structure to make ohmic contact, such as Be—Au alloy electrode and the epitaxial structure of the P-type-window layer to make ohmic contact.
  • the transparent substrate is usually bonded to the epitaxial structure using polymer glue, for example, the transparent substrate is bonded to the P-type window layer.
  • the temperature at which the electrode and the epitaxial structure make ohmic contact is about 500 degrees Celsius, and this temperature may cause the polymer glue to break, which in turn may cause the chip to break.
  • the disclosure provides a micro light emitting diode chip capable of making ohmic contact between an electrode and an epitaxial structure at a relatively low temperature.
  • An embodiment of the disclosure provides a micro light emitting diode chip including a first-type semiconductor layer, an active layer, a second-type semiconductor layer, a first-type electrode, and a second-type electrode.
  • the first-type semiconductor layer has a first high-concentration doping region and a first low-concentration doping region.
  • the active layer is disposed between the first-type semiconductor layer and the second-type semiconductor layer.
  • the first-type electrode is directly contacted and electrically contacted to the first high-concentration doping region.
  • the second-type electrode is electrically connected to the second-type semiconductor layer.
  • doping concentration of the first high-concentration doping region falls within a range of 5 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 .
  • a ratio of an area of an orthographic projection of the first high-concentration doping region in a direction perpendicular to the micro light emitting diode chip to an area of an orthographic projection of the micro light emitting diode chip in the direction falls within a range of 0.01 to 0.35.
  • a ratio of an area of an orthographic projection of a first contact region in a direction perpendicular to the micro light emitting diode chip to an area of an orthographic projection of the first high-concentration doping region in the direction falls within a range of 0.5 to 1.
  • the first contact region is a contact range of the first-type electrode and the first high-concentration doping region.
  • a thickness of the first high-concentration doping region falls within a range of 1 nm to 3 ⁇ m.
  • a distance between the first high-concentration doping region and the active layer falls within a range of 0.5 ⁇ m to 1.5 ⁇ m.
  • a shortest distance between the first-type electrode and an edge of the micro light emitting diode chip is greater than or equal to 1 ⁇ m.
  • a shortest distance between the first high-concentration doping region and an edge of the micro light emitting diode chip is greater than or equal to 1 ⁇ m.
  • the micro light emitting diode chip further includes a window layer.
  • the first-type semiconductor layer is disposed between the active layer and the window layer.
  • a ratio of doping concentration of the first high-concentration doping region to doping concentration of the window layer is greater than or equal to 3 and less than or equal to 1000.
  • the first-type electrode includes an upper first-type electrode.
  • the upper first-type electrode is disposed on a surface of the window layer away from the first-type semiconductor layer.
  • a first overlapping region exists between an orthographic projection of the upper first-type electrode onto the first high-concentration doping region and the first high-concentration doping region.
  • An area ratio of the first overlapping region to the first high-concentration doping region falls within a range of 0.5 to 1.5.
  • the first-type electrode includes an upper first-type electrode.
  • the upper first-type electrode is disposed on a surface of the second-type semiconductor layer away from the first-type semiconductor layer.
  • a first overlapping region exists between an orthographic projection of the upper first-type electrode onto the first high-concentration doping region and the first high-concentration doping region.
  • An area ratio of the first overlapping region to the first high-concentration doping region falls within a range of 0.5 to 1.5.
  • the second-type semiconductor layer has a second high-concentration doping region and a second low-concentration doping region.
  • the second-type electrode is directly contacted and electrically contacted to the second high-concentration doping region.
  • doping concentration of the second high-concentration doping region falls within a range of 5 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 .
  • a ratio of an area of an orthographic projection of the second high-concentration doping region along a direction perpendicular to the micro light emitting diode chip to an area of an orthographic projection of the micro light emitting diode chip in the direction falls within a range of 0.01 to 0.35.
  • a ratio of an area of an orthographic projection of a second contact region in a direction perpendicular to the micro light emitting diode chip to an area of the second high-concentration doping region falls within a range of 0.5 to 1.
  • the second contact region is a contact range of the second-type electrode and the second high-concentration doping region.
  • a thickness of the second high-concentration doping region falls within a range of 1 nm to 3 ⁇ m.
  • a distance between the second high-concentration doping region and the active layer falls within a range of 0.5 ⁇ m to 1.5 ⁇ m.
  • a shortest distance between the second-type electrode and an edge of the micro light emitting diode chip is greater than or equal to 1 ⁇ m.
  • a shortest distance between the second high-concentration doping region and an edge of the micro light emitting diode chip is greater than or equal to 1 ⁇ m.
  • the first-type semiconductor layer has a first high-concentration doping region or the second-type semiconductor layer has a second high-concentration doping region. Therefore, the first-type electrode and the first high-concentration doping region or the second-type electrode and the second high-concentration doping region may be annealed at low temperature to reach ohmic contact temperature, which further prevents polymer glue from breaking and increases the yield.
  • FIG. 1 A is a schematic three-dimensional view of a micro light emitting diode chip according to a first embodiment of the disclosure.
  • FIG. 1 B is a schematic cross-sectional view of the micro light emitting diode chip according to the first embodiment of the disclosure.
  • FIG. 2 is a schematic cross-sectional view of a micro light emitting diode chip according to a second embodiment of the disclosure.
  • FIG. 3 is a schematic cross-sectional view of a micro light emitting diode chip according to a third embodiment of the disclosure.
  • FIG. 4 is a schematic cross-sectional view of the micro light emitting diode chip according to a fourth embodiment of the disclosure.
  • FIG. 1 A is a schematic three-dimensional view of a micro light emitting diode chip according to a first embodiment of the disclosure.
  • FIG. 1 B is a schematic cross-sectional view of the micro light emitting diode chip according to the first embodiment of the disclosure.
  • an embodiment of the disclosure provides a micro light emitting diode chip 10 , which includes a first-type semiconductor layer 100 , an active layer 200 , a second-type semiconductor layer 300 , a first-type electrode 400 , and a second-type electrode 500 .
  • the first-type semiconductor layer 100 may be a P-type (or N-type) semiconductor layer
  • the second-type semiconductor layer 300 may be an N-type (or P-type) semiconductor layer.
  • the first-type semiconductor layer 100 is a P-type semiconductor layer, dopant thereof is, for example, carbon (C), magnesium (Mg), zinc (Zn), selenium (Se), or beryllium (Be).
  • the second-type semiconductor layer 300 is an N-type semiconductor layer, dopant thereof is, for example, silicon (Si) or tellurium (Te).
  • the micro light emitting diode chip 10 is, for instance, a red light microLED or an infrared light microLED chip, while the disclosure is not limited thereto.
  • a structure of the active layer 200 may be a multiple quantum well (MQW) structure, a single quantum well structure, a double heterostructure, a single heterostructure, or a combination thereof.
  • a material of the active layer 200 may be a semiconductor material of gallium phosphide system.
  • a material of the first-type electrode 400 or the second-type electrode 500 is, for example, a Be—Au alloy, but the disclosure is not limited thereto.
  • the first-type semiconductor layer 100 has a first high-concentration doping region 102 and a first low-concentration doping region 104 .
  • doping concentration of the high-concentration doping region is too low, resistance will increase; when the doping concentration of the high-concentration doping region is too high, transparency of the micro light emitting diode chip 10 will decrease.
  • the doping concentration of the first high-concentration doping region 102 falls within a range of 5 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 .
  • the doping concentration of the first high-concentration doping region 102 falls within a range of 5 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 , which may allow for better resistivity and transparency.
  • the active layer 200 is disposed between the first-type semiconductor layer 100 and the second-type semiconductor layer 300 .
  • the first-type electrode 400 is directly contacted and electrically connected to the first high-concentration doping region 102 .
  • the second-type electrode 500 is electrically connected to the second-type semiconductor layer 300 .
  • a ratio of an area of an orthographic projection of the first high-concentration doping region 102 in a direction E1 perpendicular to the micro light emitting diode chip 10 to an area of an orthographic projection of the micro light emitting diode chip 10 in the direction E1 falls within a range of 0.01 to 0.35.
  • a ratio of an area of an orthographic projection of a first contact region CR1 in the direction E1 perpendicular to the micro light emitting diode chip 10 to an area of an orthographic projection of the first high-concentration doping region 102 in the direction E1 falls within a range of 0.5 to 1.
  • the first contact region CR1 is a contact range of the first-type electrode 400 and the first high-concentration doping region 102 .
  • a thickness t1 of the first high-concentration doping region 102 falls within a range of 1 nm to 3 ⁇ m.
  • the first high-concentration doping region 102 makes a depth of current diffusion difficult to control, and an effect of current diffusion may be lost.
  • a thickness of the first-type semiconductor layer 100 is thicker than 3 ⁇ m, for example, designed to fall within a range of 4 ⁇ m to 5 ⁇ m, the thickness t1 of the first high-concentration doping region 102 is too thick, and the first high-concentration doping region 102 will affect a current path and may produce a light absorption effect.
  • a distance d3 between the first high-concentration doping region 102 and the active layer 200 falls within a range of 0.5 ⁇ m to 1.5 ⁇ m.
  • the distance d3 between the first high-concentration doping region 102 and the active layer 200 is too small, impurities will easily diffuse into the active layer 200 and affect a photoelectric effect of the micro light emitting diode chip 10 .
  • the distance d3 between the first high-concentration doping region 102 and the active layer 200 is too large, referring to FIG. 2 or FIG.
  • an etching depth of a groove H1 is too deep, resulting in poor yield of the micro light emitting diode chip 10 and poor distribution efficiency of current in the first high-concentration doping region 102 and the first semiconductor layer 100 , reducing photoelectric efficiency.
  • a shortest distance d1 between the first-type electrode 400 and an edge of the micro light emitting diode chip 10 is greater than or equal to 1 ⁇ m. Moreover, a shortest distance d2 between the first high-concentration doping region 102 and the edge of the micro light emitting diode chip 10 is greater than or equal to 1 ⁇ m. In this way, the first-type electrode 400 may be configured toward a center of the micro light emitting diode chip 10 , which may increase bonding yield and avoid a sidewall effect of carriers running to sidewalls.
  • the micro light emitting diode chip 10 further includes a window layer 600 .
  • the window layer 600 is configured as a light extraction layer.
  • a substrate of the window layer 600 may be a group III-V material, and the doping may be the same as the first-type semiconductor layer 100 .
  • the first-type semiconductor layer 100 is disposed between the active layer 200 and the window layer 600 .
  • a ratio of the doping concentration of the first high-concentration doping region 102 to doping concentration of the window layer 600 is greater than or equal to 3 and less than or equal to 1000; if the ratio is less than 3, the window layer 600 will absorb light due to its high doping concentration; if the ratio is greater than 1000, the yield of the chip is not good due to the low doping concentration of the window layer 600 .
  • the ratio of the doping concentration of the first high-concentration doping region 102 to the doping concentration of the window layer 600 is greater than or equal to 10 and less than or equal to 50.
  • the first-type electrode 400 includes an upper first-type electrode 402 .
  • the upper first-type electrode 402 is disposed on a surface of the window layer 600 away from the first-type semiconductor layer 100 .
  • a first overlapping region OR1 exists between an orthographic projection of the upper first-type electrode 402 onto the first high-concentration doping region 102 and the first high-concentration doping region 102 .
  • the first-type electrode 400 may be configured toward the center of the micro light emitting diode chip 10 to increase bonding area, which may increase the bonding yield and avoid the sidewall effect of carriers running to the sidewalls.
  • the micro light emitting diode chip 10 further has a first groove H1 and a second groove H2.
  • the first groove H1 penetrates the window layer 600 and a part of the first high-concentration doping region 102 , and the first groove H1 exposes a surface of the first high-concentration doping region 102 on a side opposite to the direction E1.
  • the first-type electrode 400 is disposed in the first groove H1 and electrically contacts the exposed surface of the first high-concentration doping region 102 .
  • the second groove H2 penetrates the window layer 600 , the first-type semiconductor layer 100 , the active layer 200 and a part of the second-type semiconductor layer 300 , and the second groove H2 exposes a surface of the second-type semiconductor layer 300 on a side opposite to the direction E1. Furthermore, the second-type electrode 500 is disposed in the second groove H2 and electrically contacts the exposed surface of the second-type semiconductor layer 300 .
  • the micro light emitting diode chip 10 further includes an insulating layer 700 .
  • the insulating layer 700 covers inner walls of the first groove H1 and the second groove H2, making the first-type electrode 400 be electrically insulated from the window layer 600 , and the second-type electrode 500 be electrically insulated from the window layer 600 , the first-type semiconductor layer 100 , and the active layer 200 .
  • the insulating layer 700 is extended and disposed on a surface of the window layer 600 on a side opposite to the direction E1.
  • the insulating layer 700 has a first opening O1 and a second opening O2 in the first groove H1 and the second groove H2, respectively, and the first-type electrode 400 and the second-type electrode 500 are electrically contacted through the first opening O1 and the second opening O2 to the first high-concentration doping region 102 and the second-type semiconductor layer 300 , respectively.
  • the first-type semiconductor layer 100 has the first high-concentration doping region 102 , and the first-type electrode 400 is electrically contacted to the first high-concentration doping region 102 . Therefore, the first-type electrode 400 and the first high-concentration doping region 102 may be annealed at low temperature to reach ohmic contact temperature (falling in a range of 400 to 500 degrees Celsius), which further prevents polymer glue from breaking and increases the yield.
  • FIG. 2 is a schematic cross-sectional view of a micro light emitting diode chip according to a second embodiment of the disclosure.
  • a micro light emitting diode chip 10 A according to this embodiment is similar to the micro light emitting diode chip 10 of FIG. 1 B , with the following major differences.
  • the micro light emitting diode chip 10 A further includes a buffer layer 800 .
  • a material of the buffer layer 800 may be a group III-V material, and the doping may be the same as the first-type semiconductor 100 .
  • the buffer layer 800 is disposed between the active layer 200 and the first-type semiconductor layer 100 .
  • the buffer layer 800 between the first high-concentration doping region 102 and the active layer 200 could avoid the impurities of the first high-concentration doping region 102 from diffusing into the active layer 200 and affecting a photoelectric effect of the micro light emitting diode chip 10 B.
  • the first-type electrode 400 includes an upper first-type electrode 402 .
  • the upper first-type electrode 402 is disposed on a surface of the second-type semiconductor layer 300 away from the first-type semiconductor layer 100 .
  • a first overlapping region OR1 exists between an orthographic projection of the upper first-type electrode 402 onto the first high-concentration doping region 102 and the first high-concentration doping region 102 .
  • An area ratio of the first overlapping region OR1 to the first high-concentration doping region 102 falls within a range of 0.5 to 1.5.
  • the micro light emitting diode chip 10 A does not have the second groove H2 of the micro light emitting diode chip 10 of FIG. 1 B .
  • the first groove H1 penetrates the second-type semiconductor layer 300 , the active layer 200 , the buffer layer 800 and a part of the first high-concentration doping region 102 , and the first groove H1 exposes a surface of the first high-concentration doping region 102 on a side opposite to the direction E2.
  • the first-type electrode 400 is disposed in the first groove H1 and electrically contacts the exposed surface of the first high-concentration doping region 102 .
  • Advantages of the micro light emitting diode chip 10 A are similar to those of the micro light emitting diode chip 10 and therefore will not be repeated in the following.
  • FIG. 3 is a schematic cross-sectional view of a micro light emitting diode chip according to a third embodiment of the disclosure.
  • a micro light emitting diode chip 10 B according to this embodiment is similar to the micro light emitting diode chip 10 A of FIG. 2 , with the following major differences.
  • the second-type semiconductor layer 300 has a second high-concentration doping region 302 and a second low-concentration doping region 304 .
  • the second-type electrode 500 is directly contacted and electrically connected to the second high-concentration doping region 302 .
  • Doping concentration of the second high-concentration doping region 302 falls within a range of 5 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 .
  • the doping concentration of the second high-concentration doping region 302 falls within a range of 5 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 .
  • a ratio of an area of an orthographic projection of the second high-concentration doping region 302 along the direction E2 to an area of an orthographic projection of the micro light emitting diode chip 10 B in the direction E2 falls within a range of 0.01 to 0.35.
  • a ratio of an area of an orthographic projection of a second contact region CR2 in the direction E2 to an area of the second high-concentration doping region 302 falls within a range of 0.5 to 1.
  • the second contact area CR2 is a contact range of the second-type electrode 500 and the second high-concentration doping region 302 .
  • the resistance R is relatively small, and high doping helps current diffusion.
  • a thickness t2 of the second high-concentration doping region 302 falls within a range of 1 nm to 3 ⁇ m.
  • the second high-concentration doping region 302 makes a depth of current diffusion difficult to control, and an effect of current diffusion may be lost.
  • a thickness of the second-type semiconductor layer 300 is thicker than 3 ⁇ m, for example, designed to fall within a range of 4 ⁇ m to 5 ⁇ m, the thickness t2 of the second high-concentration doping region 302 is too thick, and the second high-concentration doping region 302 will affect a current path and may produce a light absorption effect.
  • a distance d6 between the second high-concentration doping region 302 and the active layer 200 falls within a range of 0.5 ⁇ m to 1.5 ⁇ m.
  • the distance d6 between the second high-concentration doping region 302 and the active layer 200 is too small, impurities will easily diffuse into the active layer 200 and affect a photoelectric effect of the micro light emitting diode chip 10 B.
  • the distance d6 between the second high-concentration doping region 302 and the active layer 200 is too large, the distribution efficiency of current is poor.
  • a shortest distance d4 between the second-type electrode 500 and an edge of the micro light emitting diode chip 10 B is greater than or equal to 1 ⁇ m.
  • a shortest distance d5 between the second high-concentration doping region 302 and the edge of the micro light emitting diode chip 10 B is greater than or equal to 1 ⁇ m.
  • the second-type electrode 500 may be configured toward a center of the micro light emitting diode chip 10 B, which may increase bonding yield and avoid a sidewall effect of carriers running to sidewalls.
  • the second-type electrode 500 includes an upper second-type electrode 502 .
  • the upper second-type electrode 502 is disposed on a surface of the second-type semiconductor layer 300 away from the first-type semiconductor layer 100 .
  • a second overlapping region OR2 exists between an orthographic projection of the upper second-type electrode 502 in the direction E2 and the second high-concentration doping region 302 .
  • the second-type electrode 500 may be configured toward the center of the micro light emitting diode chip 10 B, which may increase the bonding yield and avoid the sidewall effect of carriers running to the sidewalls.
  • the micro light emitting diode chip 10 B further has a second groove H2.
  • the second groove H2 penetrates a part of the second high-concentration doping region 302 , and the second groove H2 exposes a surface of the second high-concentration doping region 302 on a side opposite to the direction E2.
  • the second-type electrode 500 is disposed in the second groove H2 and electrically contacts the exposed surface of the second high-concentration doping region 302 .
  • Advantages of the micro light emitting diode chip 10 B are similar to those of the micro light emitting diode chip 10 A or 10 and therefore will not be repeated in the following.
  • FIG. 4 is a schematic cross-sectional view of the micro light emitting diode chip according to a fourth embodiment of the disclosure.
  • a micro light emitting diode chip 10 C according to this embodiment is similar to the micro light emitting diode chip 10 A of FIG. 2 , with the following major differences.
  • the window layer 600 C is located at the light output surface to serve as a light extraction layer of the micro light emitting diode chip 10 C.
  • the first semiconductor layer 100 is disposed between the window layer 600 C and the active layer 200 .
  • the window layer 600 C serves as a layer to be bonded to a transfer substrate (not shown) before forming ohmic contact between the electrode and the epitaxial structure, so as to prevent the transfer substrate (not shown) from being in direct contact with the first semiconductor layer 100 to affect the yield.
  • the first-type semiconductor layer has a first high-concentration doping region or the second-type semiconductor layer has a second high-concentration doping region.
  • the first-type electrode is electrically connected to the first high-concentration doping region or the second-type electrode is electrically connected to the second high-concentration doping region. Therefore, the first-type electrode and the first high-concentration doping region or the second-type electrode and the second high-concentration doping region may be annealed at low temperature to reach ohmic contact temperature, which further prevents polymer glue from breaking and increases the yield.

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Abstract

A micro light emitting diode chip including a first-type semiconductor layer, an active layer, a second-type semiconductor layer, a first-type electrode, and a second-type electrode is provided. The first-type semiconductor layer has a first high-concentration doping region and a first low-concentration doping region. The active layer is disposed between the first-type semiconductor layer and the second-type semiconductor layer. The first-type electrode is directly contacted and electrically connected to the first high-concentration doping region. The second-type electrode is electrically connected to the second-type semiconductor layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwanese application serial no. 110125431, filed on Jul. 12, 2021. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
BACKGROUND Technical Field
The disclosure relates to a chip, in particular to a micro light emitting diode chip.
Description of Related Art
In the existing manufacture of the micro light emitting diode chip such as a red micro light emitting diode chip, the final process requires the electrode and the epitaxial structure to make ohmic contact, such as Be—Au alloy electrode and the epitaxial structure of the P-type-window layer to make ohmic contact. Before making the ohmic contact between the electrode and the epitaxial structure, the transparent substrate is usually bonded to the epitaxial structure using polymer glue, for example, the transparent substrate is bonded to the P-type window layer. However, the temperature at which the electrode and the epitaxial structure make ohmic contact is about 500 degrees Celsius, and this temperature may cause the polymer glue to break, which in turn may cause the chip to break.
SUMMARY
The disclosure provides a micro light emitting diode chip capable of making ohmic contact between an electrode and an epitaxial structure at a relatively low temperature.
An embodiment of the disclosure provides a micro light emitting diode chip including a first-type semiconductor layer, an active layer, a second-type semiconductor layer, a first-type electrode, and a second-type electrode. The first-type semiconductor layer has a first high-concentration doping region and a first low-concentration doping region. The active layer is disposed between the first-type semiconductor layer and the second-type semiconductor layer. The first-type electrode is directly contacted and electrically contacted to the first high-concentration doping region. The second-type electrode is electrically connected to the second-type semiconductor layer.
According to an embodiment of the disclosure, doping concentration of the first high-concentration doping region falls within a range of 5×1017 cm−3 to 1×1019 cm−3.
According to an embodiment of the disclosure, a ratio of an area of an orthographic projection of the first high-concentration doping region in a direction perpendicular to the micro light emitting diode chip to an area of an orthographic projection of the micro light emitting diode chip in the direction falls within a range of 0.01 to 0.35.
According to an embodiment of the disclosure, a ratio of an area of an orthographic projection of a first contact region in a direction perpendicular to the micro light emitting diode chip to an area of an orthographic projection of the first high-concentration doping region in the direction falls within a range of 0.5 to 1. The first contact region is a contact range of the first-type electrode and the first high-concentration doping region.
According to an embodiment of the disclosure, a thickness of the first high-concentration doping region falls within a range of 1 nm to 3 μm.
According to an embodiment of the disclosure, a distance between the first high-concentration doping region and the active layer falls within a range of 0.5 μm to 1.5 μm.
According to an embodiment of the disclosure, a shortest distance between the first-type electrode and an edge of the micro light emitting diode chip is greater than or equal to 1 μm.
According to an embodiment of the disclosure, a shortest distance between the first high-concentration doping region and an edge of the micro light emitting diode chip is greater than or equal to 1 μm.
According to an embodiment of the disclosure, the micro light emitting diode chip further includes a window layer. The first-type semiconductor layer is disposed between the active layer and the window layer.
According to an embodiment of the disclosure, a ratio of doping concentration of the first high-concentration doping region to doping concentration of the window layer is greater than or equal to 3 and less than or equal to 1000.
According to an embodiment of the disclosure, the first-type electrode includes an upper first-type electrode. The upper first-type electrode is disposed on a surface of the window layer away from the first-type semiconductor layer. In a direction of the first-type semiconductor layer perpendicular to the micro light emitting diode chip, a first overlapping region exists between an orthographic projection of the upper first-type electrode onto the first high-concentration doping region and the first high-concentration doping region. An area ratio of the first overlapping region to the first high-concentration doping region falls within a range of 0.5 to 1.5.
According to an embodiment of the disclosure, the first-type electrode includes an upper first-type electrode. The upper first-type electrode is disposed on a surface of the second-type semiconductor layer away from the first-type semiconductor layer. In a direction perpendicular to the micro light emitting diode chip, a first overlapping region exists between an orthographic projection of the upper first-type electrode onto the first high-concentration doping region and the first high-concentration doping region. An area ratio of the first overlapping region to the first high-concentration doping region falls within a range of 0.5 to 1.5.
According to an embodiment of the disclosure, the second-type semiconductor layer has a second high-concentration doping region and a second low-concentration doping region. The second-type electrode is directly contacted and electrically contacted to the second high-concentration doping region.
According to an embodiment of the disclosure, doping concentration of the second high-concentration doping region falls within a range of 5×1017 cm−3 to 1×1019 cm−3.
According to an embodiment of the disclosure, a ratio of an area of an orthographic projection of the second high-concentration doping region along a direction perpendicular to the micro light emitting diode chip to an area of an orthographic projection of the micro light emitting diode chip in the direction falls within a range of 0.01 to 0.35.
According to an embodiment of the disclosure, a ratio of an area of an orthographic projection of a second contact region in a direction perpendicular to the micro light emitting diode chip to an area of the second high-concentration doping region falls within a range of 0.5 to 1. The second contact region is a contact range of the second-type electrode and the second high-concentration doping region.
According to an embodiment of the disclosure, a thickness of the second high-concentration doping region falls within a range of 1 nm to 3 μm.
According to an embodiment of the disclosure, a distance between the second high-concentration doping region and the active layer falls within a range of 0.5 μm to 1.5 μm.
According to an embodiment of the disclosure, a shortest distance between the second-type electrode and an edge of the micro light emitting diode chip is greater than or equal to 1 μm.
According to an embodiment of the disclosure, a shortest distance between the second high-concentration doping region and an edge of the micro light emitting diode chip is greater than or equal to 1 μm.
Based on the above, in the micro light emitting diode chip according to an embodiment of the disclosure, the first-type semiconductor layer has a first high-concentration doping region or the second-type semiconductor layer has a second high-concentration doping region. Therefore, the first-type electrode and the first high-concentration doping region or the second-type electrode and the second high-concentration doping region may be annealed at low temperature to reach ohmic contact temperature, which further prevents polymer glue from breaking and increases the yield.
To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
FIG. 1A is a schematic three-dimensional view of a micro light emitting diode chip according to a first embodiment of the disclosure.
FIG. 1B is a schematic cross-sectional view of the micro light emitting diode chip according to the first embodiment of the disclosure.
FIG. 2 is a schematic cross-sectional view of a micro light emitting diode chip according to a second embodiment of the disclosure.
FIG. 3 is a schematic cross-sectional view of a micro light emitting diode chip according to a third embodiment of the disclosure.
FIG. 4 is a schematic cross-sectional view of the micro light emitting diode chip according to a fourth embodiment of the disclosure.
 DESCRIPTION OF THE EMBODIMENTS
FIG. 1A is a schematic three-dimensional view of a micro light emitting diode chip according to a first embodiment of the disclosure. FIG. 1B is a schematic cross-sectional view of the micro light emitting diode chip according to the first embodiment of the disclosure. Referring to FIG. 1A and FIG. 1B, an embodiment of the disclosure provides a micro light emitting diode chip 10, which includes a first-type semiconductor layer 100, an active layer 200, a second-type semiconductor layer 300, a first-type electrode 400, and a second-type electrode 500.
According to this embodiment, the first-type semiconductor layer 100 may be a P-type (or N-type) semiconductor layer, and the second-type semiconductor layer 300 may be an N-type (or P-type) semiconductor layer. In the present embodiment, the first-type semiconductor layer 100 is a P-type semiconductor layer, dopant thereof is, for example, carbon (C), magnesium (Mg), zinc (Zn), selenium (Se), or beryllium (Be). And the second-type semiconductor layer 300 is an N-type semiconductor layer, dopant thereof is, for example, silicon (Si) or tellurium (Te). In the embodiment, the micro light emitting diode chip 10 is, for instance, a red light microLED or an infrared light microLED chip, while the disclosure is not limited thereto.
According to this embodiment, a structure of the active layer 200 may be a multiple quantum well (MQW) structure, a single quantum well structure, a double heterostructure, a single heterostructure, or a combination thereof. A material of the active layer 200 may be a semiconductor material of gallium phosphide system.
According to this embodiment, a material of the first-type electrode 400 or the second-type electrode 500 is, for example, a Be—Au alloy, but the disclosure is not limited thereto.
According to this embodiment, the first-type semiconductor layer 100 has a first high-concentration doping region 102 and a first low-concentration doping region 104. When doping concentration of the high-concentration doping region is too low, resistance will increase; when the doping concentration of the high-concentration doping region is too high, transparency of the micro light emitting diode chip 10 will decrease. According to this embodiment, the doping concentration of the first high-concentration doping region 102 falls within a range of 5×1017 cm−3 to 1×1019 cm−3. According to a preferred embodiment, the doping concentration of the first high-concentration doping region 102 falls within a range of 5×1018 cm−3 to 1×1019 cm−3, which may allow for better resistivity and transparency.
According to this embodiment, the active layer 200 is disposed between the first-type semiconductor layer 100 and the second-type semiconductor layer 300. The first-type electrode 400 is directly contacted and electrically connected to the first high-concentration doping region 102. The second-type electrode 500 is electrically connected to the second-type semiconductor layer 300.
According to this embodiment, a ratio of an area of an orthographic projection of the first high-concentration doping region 102 in a direction E1 perpendicular to the micro light emitting diode chip 10 to an area of an orthographic projection of the micro light emitting diode chip 10 in the direction E1 falls within a range of 0.01 to 0.35.
According to this embodiment, a ratio of an area of an orthographic projection of a first contact region CR1 in the direction E1 perpendicular to the micro light emitting diode chip 10 to an area of an orthographic projection of the first high-concentration doping region 102 in the direction E1 falls within a range of 0.5 to 1. The first contact region CR1 is a contact range of the first-type electrode 400 and the first high-concentration doping region 102. According to relationship between resistance R and area A: R=ρ×1/A, when an area of the first contact region CR1 is large, the resistance R is relatively small, and high doping helps current diffusion, where p is resistivity of the material and 1 is resistance length.
According to this embodiment, a thickness t1 of the first high-concentration doping region 102 falls within a range of 1 nm to 3 μm. When the thickness t1 of the first high-concentration doping region 102 is too small, the first high-concentration doping region 102 makes a depth of current diffusion difficult to control, and an effect of current diffusion may be lost. Conversely, considering that a thickness of the first-type semiconductor layer 100 is thicker than 3 μm, for example, designed to fall within a range of 4 μm to 5 μm, the thickness t1 of the first high-concentration doping region 102 is too thick, and the first high-concentration doping region 102 will affect a current path and may produce a light absorption effect.
According to this embodiment, a distance d3 between the first high-concentration doping region 102 and the active layer 200 falls within a range of 0.5 μm to 1.5 μm. When the distance d3 between the first high-concentration doping region 102 and the active layer 200 is too small, impurities will easily diffuse into the active layer 200 and affect a photoelectric effect of the micro light emitting diode chip 10. Conversely, when the distance d3 between the first high-concentration doping region 102 and the active layer 200 is too large, referring to FIG. 2 or FIG. 3 , an etching depth of a groove H1 is too deep, resulting in poor yield of the micro light emitting diode chip 10 and poor distribution efficiency of current in the first high-concentration doping region 102 and the first semiconductor layer 100, reducing photoelectric efficiency.
According to this embodiment, a shortest distance d1 between the first-type electrode 400 and an edge of the micro light emitting diode chip 10 is greater than or equal to 1 μm. Moreover, a shortest distance d2 between the first high-concentration doping region 102 and the edge of the micro light emitting diode chip 10 is greater than or equal to 1 μm. In this way, the first-type electrode 400 may be configured toward a center of the micro light emitting diode chip 10, which may increase bonding yield and avoid a sidewall effect of carriers running to sidewalls.
According to this embodiment, the micro light emitting diode chip 10 further includes a window layer 600. The window layer 600 is configured as a light extraction layer. A substrate of the window layer 600 may be a group III-V material, and the doping may be the same as the first-type semiconductor layer 100. In addition, the first-type semiconductor layer 100 is disposed between the active layer 200 and the window layer 600.
According to this embodiment, a ratio of the doping concentration of the first high-concentration doping region 102 to doping concentration of the window layer 600 is greater than or equal to 3 and less than or equal to 1000; if the ratio is less than 3, the window layer 600 will absorb light due to its high doping concentration; if the ratio is greater than 1000, the yield of the chip is not good due to the low doping concentration of the window layer 600. According to a preferred embodiment, the ratio of the doping concentration of the first high-concentration doping region 102 to the doping concentration of the window layer 600 is greater than or equal to 10 and less than or equal to 50.
According to this embodiment, the first-type electrode 400 includes an upper first-type electrode 402. The upper first-type electrode 402 is disposed on a surface of the window layer 600 away from the first-type semiconductor layer 100. In the direction E1 of the first-type semiconductor layer 100 perpendicular to the micro light emitting diode chip 10, a first overlapping region OR1 exists between an orthographic projection of the upper first-type electrode 402 onto the first high-concentration doping region 102 and the first high-concentration doping region 102. Furthermore, when an area ratio of the first overlapping region OR 1 to the first high-concentration doping region 102 falls within a range of 0.5 to 1.5, the first-type electrode 400 may be configured toward the center of the micro light emitting diode chip 10 to increase bonding area, which may increase the bonding yield and avoid the sidewall effect of carriers running to the sidewalls.
According to this embodiment, the micro light emitting diode chip 10 further has a first groove H1 and a second groove H2. The first groove H1 penetrates the window layer 600 and a part of the first high-concentration doping region 102, and the first groove H1 exposes a surface of the first high-concentration doping region 102 on a side opposite to the direction E1. In addition, the first-type electrode 400 is disposed in the first groove H1 and electrically contacts the exposed surface of the first high-concentration doping region 102. Moreover, the second groove H2 penetrates the window layer 600, the first-type semiconductor layer 100, the active layer 200 and a part of the second-type semiconductor layer 300, and the second groove H2 exposes a surface of the second-type semiconductor layer 300 on a side opposite to the direction E1. Furthermore, the second-type electrode 500 is disposed in the second groove H2 and electrically contacts the exposed surface of the second-type semiconductor layer 300.
According to this embodiment, the micro light emitting diode chip 10 further includes an insulating layer 700. The insulating layer 700 covers inner walls of the first groove H1 and the second groove H2, making the first-type electrode 400 be electrically insulated from the window layer 600, and the second-type electrode 500 be electrically insulated from the window layer 600, the first-type semiconductor layer 100, and the active layer 200. Moreover, the insulating layer 700 is extended and disposed on a surface of the window layer 600 on a side opposite to the direction E1.
In addition, according to this embodiment, the insulating layer 700 has a first opening O1 and a second opening O2 in the first groove H1 and the second groove H2, respectively, and the first-type electrode 400 and the second-type electrode 500 are electrically contacted through the first opening O1 and the second opening O2 to the first high-concentration doping region 102 and the second-type semiconductor layer 300, respectively.
Based on the above, in the micro light emitting diode chip 10 according to an embodiment of the disclosure, the first-type semiconductor layer 100 has the first high-concentration doping region 102, and the first-type electrode 400 is electrically contacted to the first high-concentration doping region 102. Therefore, the first-type electrode 400 and the first high-concentration doping region 102 may be annealed at low temperature to reach ohmic contact temperature (falling in a range of 400 to 500 degrees Celsius), which further prevents polymer glue from breaking and increases the yield.
FIG. 2 is a schematic cross-sectional view of a micro light emitting diode chip according to a second embodiment of the disclosure. Referring to FIG. 2 , a micro light emitting diode chip 10A according to this embodiment is similar to the micro light emitting diode chip 10 of FIG. 1B, with the following major differences. According to this embodiment, the micro light emitting diode chip 10A further includes a buffer layer 800. A material of the buffer layer 800 may be a group III-V material, and the doping may be the same as the first-type semiconductor 100. The buffer layer 800 is disposed between the active layer 200 and the first-type semiconductor layer 100. The buffer layer 800 between the first high-concentration doping region 102 and the active layer 200 could avoid the impurities of the first high-concentration doping region 102 from diffusing into the active layer 200 and affecting a photoelectric effect of the micro light emitting diode chip 10B.
According to this embodiment, the first-type electrode 400 includes an upper first-type electrode 402. The upper first-type electrode 402 is disposed on a surface of the second-type semiconductor layer 300 away from the first-type semiconductor layer 100. In a direction E2 perpendicular to the micro light emitting diode chip 10A, a first overlapping region OR1 exists between an orthographic projection of the upper first-type electrode 402 onto the first high-concentration doping region 102 and the first high-concentration doping region 102. An area ratio of the first overlapping region OR1 to the first high-concentration doping region 102 falls within a range of 0.5 to 1.5.
In addition, according to this embodiment, the micro light emitting diode chip 10A does not have the second groove H2 of the micro light emitting diode chip 10 of FIG. 1B. Furthermore, the first groove H1 penetrates the second-type semiconductor layer 300, the active layer 200, the buffer layer 800 and a part of the first high-concentration doping region 102, and the first groove H1 exposes a surface of the first high-concentration doping region 102 on a side opposite to the direction E2. Moreover, the first-type electrode 400 is disposed in the first groove H1 and electrically contacts the exposed surface of the first high-concentration doping region 102. Advantages of the micro light emitting diode chip 10A are similar to those of the micro light emitting diode chip 10 and therefore will not be repeated in the following.
FIG. 3 is a schematic cross-sectional view of a micro light emitting diode chip according to a third embodiment of the disclosure. Referring to FIG. 3 , a micro light emitting diode chip 10B according to this embodiment is similar to the micro light emitting diode chip 10A of FIG. 2 , with the following major differences. According to this embodiment, the second-type semiconductor layer 300 has a second high-concentration doping region 302 and a second low-concentration doping region 304. The second-type electrode 500 is directly contacted and electrically connected to the second high-concentration doping region 302. Doping concentration of the second high-concentration doping region 302 falls within a range of 5×1017 cm−3 to 1×1019 cm−3. According to a preferred embodiment, the doping concentration of the second high-concentration doping region 302 falls within a range of 5×1018 cm−3 to 1×1019 cm−3.
According to this embodiment, a ratio of an area of an orthographic projection of the second high-concentration doping region 302 along the direction E2 to an area of an orthographic projection of the micro light emitting diode chip 10B in the direction E2 falls within a range of 0.01 to 0.35.
According to this embodiment, a ratio of an area of an orthographic projection of a second contact region CR2 in the direction E2 to an area of the second high-concentration doping region 302 falls within a range of 0.5 to 1. The second contact area CR2 is a contact range of the second-type electrode 500 and the second high-concentration doping region 302. When an area of the second contact region CR2 is large, the resistance R is relatively small, and high doping helps current diffusion.
According to this embodiment, a thickness t2 of the second high-concentration doping region 302 falls within a range of 1 nm to 3 μm. When the thickness t2 of the second high-concentration doping region 302 is too small, the second high-concentration doping region 302 makes a depth of current diffusion difficult to control, and an effect of current diffusion may be lost. Conversely, considering that a thickness of the second-type semiconductor layer 300 is thicker than 3 μm, for example, designed to fall within a range of 4 μm to 5 μm, the thickness t2 of the second high-concentration doping region 302 is too thick, and the second high-concentration doping region 302 will affect a current path and may produce a light absorption effect.
According to this embodiment, a distance d6 between the second high-concentration doping region 302 and the active layer 200 falls within a range of 0.5 μm to 1.5 μm. When the distance d6 between the second high-concentration doping region 302 and the active layer 200 is too small, impurities will easily diffuse into the active layer 200 and affect a photoelectric effect of the micro light emitting diode chip 10B. Conversely, when the distance d6 between the second high-concentration doping region 302 and the active layer 200 is too large, the distribution efficiency of current is poor.
According to this embodiment, a shortest distance d4 between the second-type electrode 500 and an edge of the micro light emitting diode chip 10B is greater than or equal to 1 μm. Moreover, a shortest distance d5 between the second high-concentration doping region 302 and the edge of the micro light emitting diode chip 10B is greater than or equal to 1 μm. In this way, the second-type electrode 500 may be configured toward a center of the micro light emitting diode chip 10B, which may increase bonding yield and avoid a sidewall effect of carriers running to sidewalls.
According to this embodiment, the second-type electrode 500 includes an upper second-type electrode 502. The upper second-type electrode 502 is disposed on a surface of the second-type semiconductor layer 300 away from the first-type semiconductor layer 100. A second overlapping region OR2 exists between an orthographic projection of the upper second-type electrode 502 in the direction E2 and the second high-concentration doping region 302. Furthermore, when an area ratio of the second overlapping region OR2 to the second high-concentration doping region 302 falls within a range of 0.5 to 1.5, the second-type electrode 500 may be configured toward the center of the micro light emitting diode chip 10B, which may increase the bonding yield and avoid the sidewall effect of carriers running to the sidewalls.
In addition, the micro light emitting diode chip 10B further has a second groove H2. The second groove H2 penetrates a part of the second high-concentration doping region 302, and the second groove H2 exposes a surface of the second high-concentration doping region 302 on a side opposite to the direction E2. Moreover, the second-type electrode 500 is disposed in the second groove H2 and electrically contacts the exposed surface of the second high-concentration doping region 302. Advantages of the micro light emitting diode chip 10B are similar to those of the micro light emitting diode chip 10A or 10 and therefore will not be repeated in the following.
FIG. 4 is a schematic cross-sectional view of the micro light emitting diode chip according to a fourth embodiment of the disclosure. Referring to FIG. 4 , a micro light emitting diode chip 10C according to this embodiment is similar to the micro light emitting diode chip 10A of FIG. 2 , with the following major differences. In the micro light emitting diode chip 10C in this embodiment, the window layer 600C is located at the light output surface to serve as a light extraction layer of the micro light emitting diode chip 10C. In this embodiment, the first semiconductor layer 100 is disposed between the window layer 600C and the active layer 200. Moreover, the window layer 600C serves as a layer to be bonded to a transfer substrate (not shown) before forming ohmic contact between the electrode and the epitaxial structure, so as to prevent the transfer substrate (not shown) from being in direct contact with the first semiconductor layer 100 to affect the yield.
In summary, in the micro light emitting diode chip according to an embodiment of the disclosure, the first-type semiconductor layer has a first high-concentration doping region or the second-type semiconductor layer has a second high-concentration doping region. The first-type electrode is electrically connected to the first high-concentration doping region or the second-type electrode is electrically connected to the second high-concentration doping region. Therefore, the first-type electrode and the first high-concentration doping region or the second-type electrode and the second high-concentration doping region may be annealed at low temperature to reach ohmic contact temperature, which further prevents polymer glue from breaking and increases the yield.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.

Claims (15)

What is claimed is:
1. A micro light emitting diode chip comprising:
a first-type semiconductor layer having a first high-concentration doping region and a first low-concentration doping region;
an active layer;
a second-type semiconductor layer, wherein the active layer is disposed between the first-type semiconductor layer and the second-type semiconductor layer;
a first-type electrode directly contacted and electrically connected to the first high-concentration doping region; and
a second-type electrode electrically connected to the second-type semiconductor layer,
wherein a ratio of an area of an orthographic projection of a first contact region in a direction perpendicular to the micro light emitting diode chip to an area of an orthographic projection of the first high-concentration doping region in the direction falls within a range of 0.5 to 1, and the first contact region is a contact range of the first-type electrode and the first high-concentration doping region.
2. The micro light emitting diode chip according to claim 1, wherein doping concentration of the first high-concentration doping region falls within a range of 5×1017 cm−3 to 1×1019 cm−3.
3. The micro light emitting diode chip according to claim 1, wherein a ratio of an area of an orthographic projection of the first high-concentration doping region in a direction perpendicular to the micro light emitting diode chip to an area of an orthographic projection of the micro light emitting diode chip in the direction falls within a range of 0.01 to 0.35.
4. The micro light emitting diode chip according to claim 1, wherein a thickness of the first high-concentration doping region falls within a range of 1 nm to 3 μm.
5. The micro light emitting diode chip according to claim 1, wherein a distance between the first high-concentration doping region and the active layer falls within a range of 0.5 μm to 1.5 μm.
6. The micro light emitting diode chip according to claim 1, wherein a shortest distance between the first high-concentration doping region and an edge of the micro light emitting diode chip is greater than or equal to 1 μm.
7. The micro light emitting diode chip according to claim 1 further comprising a window layer, wherein the first-type semiconductor layer is disposed between the active layer and the window layer.
8. The micro light emitting diode chip according to claim 7, wherein a ratio of doping concentration of the first high-concentration doping region to doping concentration of the window layer is greater than or equal to 3 and is less than or equal to 1000.
9. The micro light emitting diode chip according to claim 7, wherein the first-type electrode comprises an upper first-type electrode disposed on a surface of the window layer away from the first-type semiconductor layer,
wherein in a direction of the first-type semiconductor layer perpendicular to the micro light emitting diode chip, a first overlapping region exists between an orthographic projection of the upper first-type electrode onto the first high-concentration doping region and the first high-concentration doping region,
wherein an area ratio of the first overlapping region to the first high-concentration doping region falls within a range of 0.5 to 1.5.
10. The micro light emitting diode chip according to claim 1, wherein the first-type electrode comprises an upper first-type electrode disposed on a surface of the second-type semiconductor layer away from the first-type semiconductor layer,
wherein in a direction perpendicular to the micro light emitting diode chip, a first overlapping region exists between an orthographic projection of the upper first-type electrode onto the first high-concentration doping region and the first high-concentration doping region,
wherein an area ratio of the first overlapping region to the first high-concentration doping region falls within a range of 0.5 to 1.5.
11. The micro light emitting diode chip according to claim 1, wherein the second-type semiconductor layer has a second high-concentration doping region and a second low-concentration doping region, and the second-type electrode is directly contacted and electrically contacted to the second high-concentration doping region.
12. The micro light emitting diode chip according to claim 11, wherein doping concentration of the second high-concentration doping region falls within a range of 5×1017 cm−3 to 1×1019 cm−3.
13. The micro light emitting diode chip according to claim 11, wherein a ratio of an area of an orthographic projection of the second high-concentration doping region along a direction perpendicular to the micro light emitting diode chip to an area of an orthographic projection of the micro light emitting diode chip in the direction falls within a range of 0.01 to 0.35.
14. The micro light emitting diode chip according to claim 11, wherein a ratio of an area of an orthographic projection of a second contact region in a direction perpendicular to the micro light emitting diode chip to an area of the second high-concentration doping region falls within a range of 0.5 to 1, and the second contact region is a contact range of the second-type electrode and the second high-concentration doping region.
15. The micro light emitting diode chip according to claim 11, wherein the second-type electrode comprises an upper second-type electrode disposed on a surface of the second-type semiconductor layer away from the first-type semiconductor layer,
wherein a second overlapping region exists between an orthographic projection of the upper second-type electrode in a direction perpendicular to the micro light emitting diode chip and the second high-concentration doping region,
wherein an area ratio of the second overlapping region to the second high-concentration doping region falls within a range of 0.5 to 1.5.
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050179045A1 (en) 2004-02-13 2005-08-18 Ryu Yung H. Nitride semiconductor light emitting diode having improved ohmic contact structure and fabrication method thereof
TW200610175A (en) 2004-09-02 2006-03-16 Formosa Epitaxy Inc Low resistance n-type contact layer structure for GaN multi-quantum well light emitting diode
CN102569556A (en) 2012-01-09 2012-07-11 厦门市三安光电科技有限公司 LED with high-conductivity n-type ohmic contact and manufacturing method thereof
TWI478387B (en) 2013-10-23 2015-03-21 隆達電子股份有限公司 Light-emitting diode structure
CN104681686A (en) 2013-12-02 2015-06-03 晶元光电股份有限公司 Semiconductor light emitting element
US20180166606A1 (en) * 2016-12-09 2018-06-14 PlayNitride Inc. Light emitting diode chip
TWI632673B (en) 2017-07-11 2018-08-11 錼創科技股份有限公司 Micro light-emitting element and display device
CN108475715A (en) 2016-01-05 2018-08-31 世迈克琉明有限公司 Semiconductor light-emitting elements
CN110828557A (en) 2019-09-30 2020-02-21 西安交通大学 P-GaN ohmic contact electrode and preparation method and application thereof
US20210057611A1 (en) 2019-08-21 2021-02-25 Industrial Technology Research Institute Light-emitting device and display apparatus

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100999787B1 (en) * 2009-12-29 2010-12-08 엘지이노텍 주식회사 Light emitting device, manufacturing method and light emitting device package

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050179045A1 (en) 2004-02-13 2005-08-18 Ryu Yung H. Nitride semiconductor light emitting diode having improved ohmic contact structure and fabrication method thereof
TW200610175A (en) 2004-09-02 2006-03-16 Formosa Epitaxy Inc Low resistance n-type contact layer structure for GaN multi-quantum well light emitting diode
CN102569556A (en) 2012-01-09 2012-07-11 厦门市三安光电科技有限公司 LED with high-conductivity n-type ohmic contact and manufacturing method thereof
TWI478387B (en) 2013-10-23 2015-03-21 隆達電子股份有限公司 Light-emitting diode structure
US9006775B1 (en) * 2013-10-23 2015-04-14 Lextar Electronics Corporation Light-emitting diode
CN104681686A (en) 2013-12-02 2015-06-03 晶元光电股份有限公司 Semiconductor light emitting element
CN108475715A (en) 2016-01-05 2018-08-31 世迈克琉明有限公司 Semiconductor light-emitting elements
US11309457B2 (en) * 2016-01-05 2022-04-19 Semicon Light Co., Ltd. Semiconductor light-emitting element
TW201822380A (en) 2016-12-09 2018-06-16 英屬開曼群島商錼創科技股份有限公司 Light-emitting diode chip
US20180166606A1 (en) * 2016-12-09 2018-06-14 PlayNitride Inc. Light emitting diode chip
US10164152B2 (en) * 2016-12-09 2018-12-25 PlayNitride Inc. Light emitting diode chip
TWI632673B (en) 2017-07-11 2018-08-11 錼創科技股份有限公司 Micro light-emitting element and display device
US10490720B2 (en) * 2017-07-11 2019-11-26 PlayNitride Inc. Micro light-emitting device and display apparatus
US20210057611A1 (en) 2019-08-21 2021-02-25 Industrial Technology Research Institute Light-emitting device and display apparatus
CN110828557A (en) 2019-09-30 2020-02-21 西安交通大学 P-GaN ohmic contact electrode and preparation method and application thereof

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
"Office Action of China Counterpart Application", issued on Mar. 9, 2023, pp. 1-7.
"Office Action of China Counterpart Application", issued on Oct. 28, 2022, p. 1-p. 8.
"Office Action of Taiwan Counterpart Application", issued on Dec. 28, 2021, p. 1-p. 6.

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