JP4174581B2 - Method for manufacturing light emitting device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a light emitting deviceofIt relates to a manufacturing method.
[0002]
[Prior art]
[Patent Document 1]
  JP 2001-68731 A
[0003]
  (Al_xGa_1-x)_yIn_1-yA light emitting device in which a light emitting layer portion is formed by a mixed crystal of P (however, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1; hereinafter also referred to as AlGaInP) has a thin AlGaInP active layer and a band gap larger than that. By adopting a double hetero structure sandwiched between an n-type AlGaInP cladding layer and a p-type AlGaInP cladding layer, a high-luminance device can be realized. In recent years, In_xGa_yAl_1-xyA blue light emitting element in which a similar double hetero structure is formed using N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1; hereinafter also referred to as InGaAlN) has been put into practical use.
[0004]
  For example, taking an AlGaInP light emitting device as an example, an n-type GaAs buffer layer, an n-type AlGaInP cladding layer, an AlGaInP active layer, and a p-type AlGaInP cladding layer are formed in this order in a heterogeneous form on an n-type GaAs substrate. The light emitting layer part which laminates | stacks and makes a double hetero structure is formed. Energization of the light emitting layer portion is performed via a metal electrode formed on the element surface. Here, since the metal electrode functions as a light shield, it is formed, for example, so as to cover only the central portion of the main surface of the light emitting layer portion, and light is extracted from the surrounding electrode non-formation region.
[0005]
  In this case, reducing the area of the metal electrode as much as possible can increase the area of the light leakage region formed around the electrode, which is advantageous from the viewpoint of improving the light extraction efficiency. Conventionally, attempts have been made to increase the light extraction amount by effectively spreading the current in the element by devising the electrode shape, but in this case also the increase in the electrode area is unavoidable anyway, the light leakage area On the contrary, it falls into a dilemma where the amount of light extraction is limited by the decrease. In addition, the carrier concentration of the dopant in the clad layer, and thus the conductivity, is kept somewhat low in order to optimize the light emission recombination of carriers in the active layer, and the current tends not to spread in the in-plane direction. . This leads to concentration of current density in the electrode coating region, and a substantial light extraction amount in the light leakage region is reduced. Therefore, a method of forming a low resistivity current diffusion layer with an increased carrier concentration between the clad layer and the electrode is employed. The current diffusion layer is required to have a thickness of at least about 5 μm to 10 μm or more in order to obtain a sufficient current diffusion effect, such as metal organic vapor phase epitaxy (MOVPE method) It is formed by the method (Liquid Phase Epitaxy: LPE method).
[0006]
  On the other hand, in order to improve the light extraction efficiency, various element structures that can extract light from both surfaces of the light emitting layer portion have been proposed. In the case of an AlGaInP light emitting device, a GaAs substrate is used as a growth substrate for the light emitting layer portion. However, GaAs absorbs a large amount of light in the emission wavelength region of the AlGaInP light emitting layer portion. Therefore, Patent Document 1 discloses a method of once peeling a GaAs substrate and newly bonding a transparent conductive substrate such as GaP that is transparent in the emission wavelength region in order to extract light from both sides of the light emitting layer portion. Yes. In this publication, a transparent conductive substrate is bonded to a light emitting layer through a conductive oxide layer such as ITO (Indium Tin Oxide).
[0007]
[Problems to be solved by the invention]
  In the light-emitting element disclosed in the above publication, the light-emitting layer portion and the transparent conductive substrate are directly joined by a conductive oxide layer in contact with both of them. However, the conductive oxide layer such as ITO has a high contact resistance with the compound semiconductor forming the light emitting layer portion or the transparent conductive substrate, and the forward series resistance is high in the above direct bonding form. Therefore, there is a problem that it is impossible to drive with an appropriate operating voltage.
[0008]
  In the above publication, the conductive oxide layer is formed by applying and baking a colloidal solution containing ITO fine particles. The conductive oxide layer formed by such a method is bonded to a transparent conductive substrate. There is a problem that the force is small and peeling easily occurs.
[0009]
  The present inventionofThe problem is a light emitting device that can be manufactured at low cost despite having a thick current diffusion layer, and has low series resistance and sufficient light emission efficiency at a low voltage.ofProduction methodTheIs to provide.
[0010]
[Means for solving the problems and actions / effects]
  Of the present inventionApplicableThe light emitting element is formed by laminating a light emitting layer portion made of a compound semiconductor on one main surface of a transparent conductive semiconductor substrate via a conductive oxide layer for substrate bonding made of a conductive oxide,
  A contact layer for reducing the junction resistance of the substrate-bonding conductive oxide layer is in contact with the substrate-bonding conductive oxide layer between the light emitting layer portion and the substrate-bonding conductive oxide layer. It is arranged.
[0011]
  And the manufacturing method of the light emitting element of this invention is as follows.
  A light emitting layer portion made of a compound semiconductor is bonded to one main surface of a transparent conductive semiconductor substrate via a substrate bonding oxide layer made of a conductive oxide, and the light emitting layer portion and the substrate bonding portion are bonded together. Manufactures a light emitting device in which a contact layer for reducing the junction resistance of the conductive oxide layer for bonding the substrate is disposed between the conductive oxide layer and the conductive oxide layer for bonding the substrate. To do
  A light emitting layer portion growth step of epitaxially growing a light emitting layer portion made of a compound semiconductor on the first main surface of the substrate for light emitting layer growth;
  A contact layer forming step of forming a layer to be a contact layer on the light emitting layer portion to reduce a junction resistance of the substrate-bonding conductive oxide layer;
  A substrate-bonding conductive oxide layer forming step of forming the light-emitting layer portion and / or the substrate-bonding conductive oxide layer on the bonding surface side of the transparent conductive semiconductor substrate;
  By laminating the light emitting layer portion and the transparent conductive semiconductor substrate via the substrate-bonding conductive oxide layer, the layer to be the contact layer is in contact with the substrate-bonding conductive oxide layer. A bonding process for making a substrate bonded body arranged in
  A peeling step of peeling the substrate for light emitting layer growth from the substrate laminate,
  In the contact layer forming step, a GaAs layer to be the contact layer is formed, and an ITO layer that forms the substrate-bonding conductive oxide layer is formed so as to be in contact with the GaAs layer, followed by heat treatment, In is diffused from the ITO layer into the GaAs layer, and the contact layer is formed as a GaAs layer containing In.In addition, the average In concentration of the contact layer is 0.1 to 0.6 in terms of the atomic ratio of In to the total concentration of In and Ga, and the boundary position of the contact layer with the ITO layer In concentration in C _A And the In concentration at the boundary position on the opposite side is C _B As C _B / C _A Is 0.8 or lessIt is characterized by that.
[0012]
  The transparent conductive semiconductor substrate is made of a semiconductor that is transparent to light emitted from the light emitting layer portion. In the present specification, “transparent to the light emitted from the light emitting layer” means that the transmittance of the light emitted from the light emitting layer is 50% or more. It is opaque to the light emitted by.
[0013]
  According to the present invention, after the light emitting layer portion made of a compound semiconductor is epitaxially grown on the first main surface of the light emitting layer growth substrate, the light emitting layer portion on the main surface opposite to the light emitting layer growth substrate side, A transparent conductive semiconductor substrate is bonded through a conductive oxide layer. This transparent conductive semiconductor substrate is used as a current diffusion layer, for example. Then, the light emitting layer growth substrate is peeled from the substrate bonded body. The conductive oxide layer can be used as a substrate-bonding conductive oxide layer for ensuring good conduction with the light emitting layer portion, and also considers lattice matching between the light emitting layer portion and the transparent conductive semiconductor substrate. Since it is not necessary, it is easy to manufacture. In addition, by attaching a transparent conductive semiconductor substrate having a sufficient thickness to the light emitting layer portion in advance, the light emitting layer portion can sufficiently secure the mechanical strength necessary for peeling the light emitting layer growth substrate. In addition, since the portion to be the current diffusion layer is not grown thick by the MOVPE method or the LPE method but is formed by bonding the transparent conductive semiconductor substrate, it is difficult to increase the cost and reduce the manufacturing efficiency.
[0014]
  On the other hand, when a conductive oxide layer such as ITO is intended to be directly bonded to the compound semiconductor layer, a good ohmic junction is not necessarily formed, and the luminous efficiency may decrease due to an increase in series resistance based on contact resistance. However, the contact resistance can be lowered by arranging a contact layer for reducing the junction resistance of the substrate-bonding conductive oxide layer so as to be in contact with the substrate-bonding conductive oxide layer.
[0015]
  On the main surface on the non-bonded side of the transparent conductive semiconductor substrate, for example, a metal electrode for applying a voltage to the light emitting layer can be formed so as to cover a partial region of the main surface. . The transparent conductive semiconductor substrate functions as a light extraction layer or a current diffusion layer. In this case, after the bonding step, a metal for applying a voltage to the light emitting layer portion on the main surface on the non-bonding side of the transparent conductive semiconductor substrate (hereinafter also simply referred to as “main surface”). What is necessary is just to implement the electrode formation process which forms an electrode in the form which covers a partial area | region of this main surface.
[0016]
  The substrate-bonding conductive oxide layer has a first region consisting of a region immediately below the metal electrode and the remaining second region, and the contact layer has a formation area ratio in the second region that is higher than that of the first region. Can be increased. Note that the formation area ratio of the contact layer in each region refers to a ratio obtained by dividing the total area of the contact layers in the region by the total area of the region. According to this configuration, in the region immediately below the metal electrode (first region) where the light extraction amount is small, the contact area formation area ratio is made smaller than the remaining region (second region) where the light extraction amount is large. The contact resistance of the conductive oxide layer in the region is increased. As a result, the drive current of the light emitting element has a larger component that flows around the first region and flows into the second region, so that the light extraction efficiency can be greatly increased.
[0017]
  In addition, the main surface of the light emitting layer on the side opposite to the transparent conductive semiconductor substrate can be covered with a conductive oxide layer for electrodes that also serves as a transparent electrode. The conductive oxide layer for electrodes such as ITO, which will be described later, has a better current diffusion effect and better light transmission than a transparent conductive semiconductor substrate such as GaP, so this surface should be used as a light extraction surface. However, it is more effective in increasing the emission intensity. If the conductive oxide layer for electrodes is formed on the n-type layer side of the light emitting layer portion having a pn junction, the light extraction improvement effect becomes more remarkable.
[0018]
  In this case, a contact layer for reducing the junction resistance of the conductive oxide layer is also formed between the conductive oxide layer for electrodes and the light emitting layer so as to be in contact with the conductive oxide layer. can do. Thereby, the contact resistance of the conductive oxide layer for electrodes can be reduced. In this case, a metal electrode is formed so as to cover a part of the electrode conductive oxide layer, and a region around the metal electrode of the electrode conductive oxide layer is used as a light extraction surface.
[0019]
  The electrode conductive oxide layer can also be configured to have a first region consisting of a region immediately below the metal electrode and the remaining second region, and the contact layer is formed in the second region more than the first region. The rate can be increased. As a result, the amount of current flowing in the second region bypassing the first region is increased, and the light extraction efficiency can be greatly increased.
[0020]
  When the above-mentioned metal electrode is formed on the conductive oxide layer for substrate bonding or the conductive oxide layer for electrodes, and in the second region, the contact area formation rate is larger than the first region, the light extraction amount From the viewpoint of improving the light extraction efficiency, it is desirable that the light emission drive current does not flow as much as possible in the first region with a small amount of light. Therefore, it is desirable that the contact layer is not formed as much as possible in the first region.
[0021]
  In the second region, the configuration in which the formation area ratio of the contact layer is set larger than that in the first region may be adopted for all contact layers, or only for some contact layers, and other contacts. For example, the layer may be formed over the entire surface of the substrate-bonding conductive oxide layer. In particular, the contact layer closest to the light emitting layer portion has a particularly remarkable effect of bypassing the drive current to the second region by setting the formation area ratio larger in the second region than in the first region.
[0022]
  Further, it is desirable that at least the contact layer formation region and the non-formation region are mixed in the second region where the amount of light extracted from the light emitting layer portion is large outside the bonding interface of the conductive oxide layer. . More specifically, the contact layer formation region is preferably formed in a dispersed manner. According to this structure, even when the contact layer formed for reducing the contact resistance of the conductive oxide layer has a property of easily absorbing light from the light emitting layer portion, it is directly under the contact layer formation region. The light generated in this manner leaks from the non-formation region adjacent to the light, so that absorption by the contact layer can be suppressed. As a result, the light extraction efficiency of the entire element can be increased.
[0023]
  Next, a contact layer for reducing the junction resistance of the substrate-bonding conductive oxide layer is also formed between the transparent conductive semiconductor substrate and the substrate-bonding conductive oxide layer. It can arrange | position so that a physical layer may be touched. Thereby, the contact resistance of a conductive oxide layer can further be reduced.
[0024]
  In addition to forming the electrode conductive oxide layer, the peel-side main surface of the light-emitting layer portion is formed with a current diffusion layer made of a compound semiconductor by epitaxial growth on the light-emitting layer growth substrate in advance. There is also a method in which the light emitting layer growth substrate is peeled off while leaving the diffusion layer on the element side. In this case, since the current diffusion layer to be formed is formed at the initial stage of growth on the substrate for growing the light emitting layer, the lattice matching conditions with the substrate are inevitably strict, and there are many restrictions. For example, when a GaAs substrate is used, a compound semiconductor for a current diffusion layer that can be lattice-matched to this can be a candidate with few AlGaAs. However, AlGaAs has a relatively small band gap energy and is likely to cause a problem of light absorption (particularly, a yellow-green emission wavelength around 560 nm). Moreover, since Al is contained, the problem of high-temperature oxidation tends to occur when the subsequent light emitting layer is epitaxially grown. Furthermore, there is a difficulty in increasing the number of growth steps by expensive MOVPE method for epitaxial growth of the AlGaAs layer. However, if a method of forming a conductive oxide layer for electrodes in a subsequent process is adopted, there is no need to consider lattice matching to the substrate at all, and light absorption problems hardly occur. In addition, an inexpensive method such as sputtering, which will be described later, can be used for the layer growth, and since the growth can be performed at a relatively low temperature, there is little fear that the compound semiconductor on the light emitting layer side is oxidized.
[0025]
  On the other hand, it is a slightly more complicated process than the method for forming the conductive oxide layer for electrodes, but both main surfaces of the light emitting layer part are interposed with conductive oxide layers for substrate bonding made of conductive oxide. It is also possible to adopt a configuration in which a transparent conductive semiconductor substrate is bonded. Also with this configuration, light can be efficiently extracted from both surfaces of the light emitting layer portion. In this case, from the viewpoint of reducing the series resistance, it is desirable to form the above-described contact layer in contact with each substrate-bonding conductive oxide layer. In addition, a metal layer is formed on the peel-side main surface of the light emitting layer portion, and the light from the light emitting layer portion is reflected by the metal layer, and the reflected light is superimposed on the direct light from the light emitting layer portion. You can also take it out.
[0026]
  Specifically, the conductive oxide layer can be made of ITO. ITO is an indium oxide film doped with tin oxide, and the resistivity of the electrode layer is 5 × 10 5 by setting the content of tin oxide to 1 to 9% by mass.^-4It can be set to a sufficiently low value of Ω · cm or less. In addition to the ITO electrode layer, the ZnO electrode layer has high conductivity and can be used in the present invention. Further, tin oxide doped with antimony oxide (so-called Nesa), Cd₂SnO₄, Zn₂SnO₄ZnSnO₃MgIn₂O₄CdSb doped with yttrium oxide (Y)₂O₆, Tin oxide doped GaInO₃Can also be used as the material of the conductive oxide layer. That is, the substrate-bonding conductive oxide layer can contain any of indium, tin, and zinc. These conductive oxides have good transparency to visible light (that is, are transparent), and when used as a voltage application electrode to the light emitting layer portion, there is an advantage that light extraction is not hindered. In addition, when a device driving voltage is applied through a metal electrode such as a bonding pad formed on the conductive oxide layer, the current is spread in a plane to make the light emission uniform and increase the efficiency. .
[0027]
  These conductive oxide layers are formed by a known vapor deposition method such as chemical vapor deposition (CVD), physical vapor deposition (PVD) such as sputtering or vacuum deposition, or molecular beam epitaxial growth. It can be formed by the method (molecular beam epitaxy: MBE). For example, an ITO electrode layer or a ZnO electrode layer can be manufactured by high frequency sputtering or vacuum deposition, and a nesa film can be manufactured by a CVD method. Further, instead of these vapor phase growth methods, other methods such as a sol-gel method may be used. However, as described later, it is advantageous from the viewpoint of improving the bonding strength that the conductive oxide layer for bonding the substrate is amorphous, and in this case, sputtering can be most preferably employed.
[0028]
  The thickness of the conductive oxide layer used for the bonding may be determined mainly by considering the electric conduction in the layer thickness direction. Therefore, the conductive oxide layer should be formed thinly so as not to increase the series resistance, for example, 50 nm to 200 nm (specifically (Example: 100 nm) On the other hand, the thickness of the conductive oxide layer used for the electrode on the main back surface side of the light emitting layer portion should be a little thicker than this in consideration of current diffusion in the in-plane direction, for example, 100 nm to 500 nm (specifically (Example: 200 nm).
[0029]
  It is desirable to use a transparent conductive semiconductor substrate having a refractive index of 4 or less with respect to light from the light emitting layer. By reducing the refractive index as described above, when light is extracted through the transparent conductive semiconductor substrate, the critical angle of total reflection on the light extraction surface is reduced, and the light extraction efficiency can be improved.
[0030]
  For example, each of the light emitting layer portions (Al_xGa_1-x)_yIn_1-yOne having a double heterostructure in which a first conductivity type cladding layer, an active layer, and a second conductivity type cladding layer composed of a mixed crystal of P (where 0 ≦ x, y ≦ 1, and x + y = 1) are laminated Can be configured as In this case, the transparent conductive semiconductor substrate has a wavelength band of 550 nm or more and 650 nm or less with respect to light of a green to red emission wavelength band (550 nm or more and 650 nm or less) from the light emitting layer portion having the double hetero structure layer. When the refractive index with respect to light is 3.5 or less, the critical angle of total reflection can be increased, and the light extraction efficiency of the light emitting element can be improved. As such a transparent conductive semiconductor substrate, specifically, any of GaP, ZnO, SiC, and AlGaAs (particularly, the mixed crystal ratio of AlAs is 0.75 or more) has good conductivity. Can be suitably used.
[0031]
  Next, specifically, each contact layer described above preferably employs a compound semiconductor that does not contain Al at the bonding interface with the conductive oxide layer and that is made of a compound semiconductor having a band gap energy of less than 1.42 eV. can do. By using such a contact layer, a good ohmic contact can be obtained, and resistance increase due to Al component oxidation hardly occurs. Specifically, GaAs containing In can be used as the contact layer. The compound semiconductor composing the contact layer is made of In at the junction interface with the conductive oxide layer._xGa_1-xIf As (0 <x ≦ 1), the desired contact resistance reduction effect can be obtained.
[0032]
  In this case, in the contact layer forming step, a GaAs layer to be a contact layer is formed, and further, an ITO layer forming a conductive oxide layer for substrate bonding is formed so as to be in contact with the GaAs layer, and then heat treatment is performed. The contact layer can be formed as a GaAs layer containing In by diffusing In from the ITO layer to the GaAs layer. In this case, the obtained light-emitting element has a conductive oxide layer that is an ITO layer, and a contact layer that is In at the bonding interface with the transparent conductive oxide layer._xGa_1-xIt is assumed that As (0 <x ≦ 1), and the In concentration distribution in the thickness direction continuously decreases as the distance from the ITO layer increases in the thickness direction.
[0033]
  In this method, a GaAs layer is first formed on a light emitting layer portion or a transparent conductive semiconductor substrate on a side where a contact layer is to be formed, and an ITO layer is formed so as to be in contact with the GaAs layer. For example, when the contact layer is formed on the light emitting layer side, the light emitting layer portion is first epitaxially grown on the light emitting layer portion growth substrate by, for example, the well-known MOVPE method, and further (with another layer interposed). The GaAs layer may be epitaxially grown. Similarly, when it is desired to form a contact layer on the transparent conductive semiconductor substrate side, a GaAs layer may be epitaxially grown on the transparent conductive semiconductor substrate.
[0034]
  For the contact layer, a method of directly epitaxially growing InGaAs may be adopted. However, the use of the above method has the following advantages. That is, the GaAs layer is very easy to lattice match with, for example, a light emitting layer portion made of AlGaInP or a transparent conductive semiconductor substrate made of GaP, and is a homogeneous and continuous film compared to the case where InGaAs is directly epitaxially grown. Can be formed. Then, after forming an ITO layer on the GaAs layer, heat treatment is performed to diffuse In from the ITO layer to the GaAs layer to form a contact layer. The contact layer made of GaAs containing In obtained by heat treatment in this way does not have an excessive In content, and effectively prevents quality deterioration such as emission intensity reduction due to lattice mismatch with the light emitting layer. can do. The lattice matching between the GaAs layer and the light emitting layer portion is such that the light emitting layer portion is (Al_xGa_1-x)_yIn_1-ySince it is particularly good when it is constituted by P (where 0 ≦ x ≦ 1, 0.45 ≦ y ≦ 0.55), the mixed crystal ratio y is set in the above range, and the light emitting layer portion ( It may be desirable to form a cladding layer or an active layer.
[0035]
  The heat treatment described above causes the In concentration distribution in the thickness direction of the contact layer to continuously decrease as the distance from the ITO layer increases in the thickness direction as shown in (1) of FIG. It is desirable to incline the In concentration distribution. Such a structure is formed by diffusing In from the ITO side to the contact layer side by heat treatment.
[0036]
  Further, the In concentration distribution in the thickness direction of the contact layer is continuously decreased as the distance from the ITO layer is increased in the thickness direction, thereby producing the following advantages. That is, for example, in the case of a contact layer formed on the light emitting layer portion side made of AlGaInP or on the transparent conductive semiconductor substrate side made of GaP, the In concentration distribution becomes small on the light emitting layer portion side or the transparent conductive semiconductor substrate side, and light emission The difference in lattice constant from the layer portion or the transparent conductive semiconductor substrate can be reduced, and as a result, the lattice matching can be further improved. However, if the heat treatment temperature becomes excessively high or the heat treatment time is lengthened, the In diffusion from the ITO layer proceeds excessively, and the In concentration distribution in the contact layer as shown in (3) in FIG. 3 shows a substantially constant high value in the thickness direction, and the above effect cannot be obtained (Note that if the heat treatment temperature is excessively lowered or the heat treatment time is excessively shortened, ▲ in FIG. 2), the In concentration in the contact layer is insufficient.
[0037]
  In this case, in FIG. 3, the In concentration in the vicinity of the boundary between the contact layer and the ITO transparent electrode layer is represented by C_AAnd the In concentration near the boundary on the opposite side is C_BWhen C_B/ C_AIs preferably adjusted to 0.8 or less, and the above-described heat treatment is preferably performed so that the In concentration distribution of the form can be obtained. C_B/ C_AWhen the value exceeds 0.8, the effect of improving the lattice matching with the light emitting layer part due to the gradient of In concentration distribution cannot be obtained sufficiently. Note that the composition distribution (In or Ga concentration distribution) in the thickness direction of the contact layer is determined by secondary ion mass spectrometry (SIMS), Auger electron spectroscopy analysis while gradually etching the layer in the thickness direction. (Auger Electron spectroscopy), X-ray photoelectron spectroscopy (XPS), etc., can be measured by known surface analysis methods.
[0038]
  The In concentration in the vicinity of the boundary between the contact layer and the ITO transparent electrode layer is preferably 0.1 or more and 0.6 or less in terms of the atomic ratio of In to the total concentration of In and Ga. It is desirable to carry out such an In concentration. If the In concentration by the above definition is less than 0.1, the effect of reducing the contact resistance of the contact layer becomes insufficient, and if it exceeds 0.6, the quality of the emission intensity decreases due to lattice mismatch between the contact layer and the light emitting layer. Deterioration becomes severe. Note that the In concentration in the vicinity of the boundary between the contact layer and the ITO transparent electrode layer is, for example, the above-described desirable value (0.1 to 0.6) in the atomic ratio of In to the total concentration of In and Ga. If possible, the In concentration C in the vicinity of the boundary of the contact layer opposite to the side facing the ITO transparent electrode layer_B4, that is, as shown in FIG. 4, there may be a structure in which an InGaAs layer is formed on the ITO transparent electrode layer side of the contact layer and the opposite side portion is a GaAs layer.
[0039]
  ITO is an indium oxide film doped with tin oxide as described above, and an ITO layer is formed on the GaAs layer, and further heat-treated in an appropriate temperature range, whereby the contact layer having the above desired In concentration. Form. By this heat treatment, the electrical resistivity of the ITO layer can be further reduced. The heat treatment is desirably performed at 600 ° C. or higher and 750 ° C. or lower. When the heat treatment temperature exceeds 750 ° C., the In diffusion rate into the GaAs layer becomes too high, and the In concentration in the contact layer tends to become excessive. In addition, the In concentration is saturated, and it is difficult to obtain an In concentration distribution inclined in the thickness direction of the contact layer. In either case, the lattice matching between the contact layer and the light emitting layer is deteriorated. In addition, if the diffusion of In to the GaAs layer excessively proceeds, In in the ITO layer is depleted near the contact portion with the contact layer, and it is difficult to avoid an increase in the electrical resistance value of the electrode. Furthermore, if the heat treatment temperature becomes too high as described above, the oxygen of ITO diffuses into the GaAs layer and the oxidation is promoted, and the series resistance of the device tends to increase. In either case, the light emitting element cannot be driven with an appropriate voltage. Moreover, when the heat treatment temperature becomes extremely high, the conductivity of the ITO transparent electrode layer may be impaired. On the other hand, when the heat treatment temperature is less than 600 ° C., the diffusion rate of In to the GaAs layer becomes too small, and it takes a long time to obtain a contact layer with sufficiently reduced contact resistance. Decrease becomes severe.
[0040]
  The heat treatment time is desirably set to a short time of 5 seconds to 120 seconds. When the heat treatment time is 120 seconds or more, particularly when the heat treatment temperature is close to the upper limit value, the amount of In diffused into the GaAs layer tends to become excessive (however, if the heat treatment temperature is kept low, a heat treatment longer than this will be performed). It is also possible to employ a time (for example, up to about 300 seconds) On the other hand, if the heat treatment time is less than 5 seconds, the amount of In diffusion into the GaAs layer is insufficient, and the contact layer has a sufficiently reduced contact resistance. Is difficult to obtain.
[0041]
  In addition, a light emitting layer portion or a transparent conductive semiconductor substrate can be bonded to the main surface of the contact layer opposite to the side in contact with the conductive oxide layer through an intermediate layer. The intermediate layer is formed of a compound semiconductor having a band gap energy intermediate between the light emitting layer portion or the transparent conductive semiconductor substrate and the contact layer.
[0042]
  In the light emitting layer portion having a double hetero structure, it is necessary to increase the barrier height between the cladding layer and the active layer to a certain level or more in order to enhance the carrier confinement effect in the active layer and improve the internal quantum efficiency. As shown in the schematic band diagram of FIG. 5 (Ec indicates the energy level at the bottom of the conduction band and Ev indicates the energy level at the top of the valence band), a contact layer (for example, InGaAs) is directly bonded to such a cladding layer (for example, AlGaInP). Then, a relatively high hetero barrier may be formed between the clad layer and the contact layer due to the bending of the band due to the junction. This barrier height ΔE increases as the band edge discontinuity between the cladding layer and the contact layer increases, and tends to hinder the movement of carriers, particularly the movement of holes having a larger effective mass. For example, in the case of using a metal electrode, light cannot be extracted when the entire surface of the cladding layer is covered with the metal electrode, so that the electrode must be formed so as to be partially covered. In this case, in order to improve the light extraction efficiency, current diffusion to the outside in the in-plane direction of the electrode must be promoted in some form. For example, in the case of a metal electrode, a contact layer such as GaAs is often formed between the light emitting layer portion, but in the case of a metal electrode, a somewhat high barrier is provided between the contact layer and the light emitting layer portion. The formation is advantageous in that the current diffusion in the in-plane direction can be promoted by the effect of blocking the carriers by the barrier. However, an increase in series resistance is unavoidable due to the formation of a high barrier.
[0043]
  On the other hand, when the ITO transparent electrode layer is used, since the ITO transparent electrode layer itself has a very high current diffusion capability, it is hardly necessary to consider the effect of blocking the carriers by the barrier. In addition, the adoption of the ITO transparent electrode layer greatly increases the area of the light extraction region as compared to when the metal electrode is used. Therefore, as shown in FIG. 6, when an intermediate layer having an intermediate band gap energy between the contact layer and the cladding layer is inserted between the contact layer and the cladding layer, the contact layer, the intermediate layer, and the intermediate layer Since each of the cladding layers has a small band edge discontinuity value, the formed barrier height ΔE is also small. As a result, the series resistance is reduced, and a sufficiently high light emission intensity can be achieved with a low driving voltage.
[0044]
  The effect of adopting the intermediate layer is that, among the light emitting layer portions of the double hetero structure, the lattice matching with GaAs containing In which forms the contact layer is relatively good (Al_xGa_1-x)_yIn_1-yThis is remarkable when the light emitting layer portion is formed at P (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1). In this case, as an intermediate layer having an intermediate band gap energy between the light emitting layer portion and the contact layer, specifically, an AlGaAs layer, a GaInP layer, and an AlGaInP layer (composition adjustment so that the band gap energy is smaller than that of the cladding layer) Can be suitably employed, and can be formed, for example, as including an AlGaAs layer. In addition, other light emitting layer portions, for example, In_xGa_yAl_1-xyThe present invention can also be applied to a light emitting layer portion having a double hetero structure composed of N. In this case, as the intermediate layer, for example, a layer including an InGaAlN layer (having a composition adjusted so that the band gap energy is smaller than that of the cladding layer) can be employed.
[0045]
  The conductive oxide layer used for bonding the transparent conductive semiconductor substrate and the light emitting layer portion can be an amorphous oxide..
[0046]
  When the conductive oxide layer made of amorphous is interposed, the light emitting layer portion and the transparent conductive semiconductor substrate can be easily bonded to each other by thermal diffusion or the like. In particular, covering the bonding side main surface of the transparent conductive semiconductor substrate and the bonding side main surface of the light emitting layer part with an amorphous conductive oxide layer, respectively, and bonding these conductive oxide layers together Thus, if the transparent conductive semiconductor substrate and the light emitting layer portion are bonded together, the light emitting layer portion and the transparent conductive semiconductor substrate can be bonded easily and firmly. When forming the substrate-bonding conductive oxide layer as amorphous, it is advantageous to employ sputtering in which the substrate temperature does not increase easily.
[0047]
DETAILED DESCRIPTION OF THE INVENTION
  Embodiments of the present invention will be described below with reference to the accompanying drawings.
  FIG. 1 is a conceptual diagram showing a light emitting device 100 according to an embodiment of the present invention. In the light emitting element 100, the light emitting layer portion 24 is provided on the main back surface MP2 of the p-GaP single crystal substrate 7 which is a transparent conductive semiconductor substrate. The entire surface of the main back surface MP3 of the light emitting layer portion 24 is covered with an ITO layer 20 that is a transparent conductive oxide layer for electrodes. The p-GaP single crystal substrate 7 functions as a current diffusion layer and a light extraction layer, and a metal electrode (for example, an Au electrode) 9 for applying a light emission driving voltage to the light emitting layer portion 24 is provided at substantially the center of the main surface MP1. The main surface MP1 is formed so as to cover a part thereof. A region around the metal electrode 9 on the main surface MP <b> 1 of the p-GaP single crystal substrate 7 forms a light extraction region from the light emitting layer portion 24. Further, the main back surface MP3 of the light emitting layer portion 24 can be extracted from the entire surface through the ITO layer 20.
[0048]
  The light emitting layer portion 24 is non-doped (Al_xGa_1-x)_yIn_1-yThe active layer 5 made of a mixed crystal of P (where 0 ≦ x ≦ 0.55, 0.45 ≦ y ≦ 0.55) is formed as p-type (Al_zGa_1-z)_yIn_1-yP-type cladding layer 6 (first conductivity type cladding layer) made of P (where x <z ≦ 1) and n-type (Al_zGa_1-z)_yIn_1-yIt has a structure sandwiched by an n-type cladding layer 4 (second conductivity type cladding layer) made of P (where x <z ≦ 1), and the emission wavelength varies from green to red depending on the composition of the active layer 5 (The emission wavelength (center wavelength) is 550 nm or more and 650 nm or less). In the light emitting device 100 of FIG. 1, the p-type AlGaInP clad layer 6 is disposed on the metal electrode 9 side, and the n-type AlGaInP clad layer 4 is disposed on the ITO layer 20 side. Therefore, the conduction polarity is positive on the metal electrode 9 side. The term “non-dope” as used herein means “does not actively add a dopant”, and contains an inevitable dopant component in a normal manufacturing process (for example, 10%).¹³-10¹⁶/ Cm³Is not excluded).
[0049]
  The p-GaP single crystal substrate 7 is manufactured by slicing and polishing a p-GaP single crystal ingot containing, for example, Zn as a p-type dopant, and has a thickness of, for example, 100 μm or more and 500 μm or less. Moreover, the refractive index with respect to the light from the light emitting layer part 24 with a wavelength of 550 nm or more and 650 nm or less is about 3.35. And it is affixed with respect to main surface MP4 of the light emitting layer part 24 via the ITO layer 10 which comprises the conductive oxide layer for board | substrate coupling | bonding. The ITO layers 20 and 10 are both amorphous.
[0050]
  A contact layer 30 made of InGaAs or the like is provided on the contact side of the ITO layers 10 and 20 in contact with the light emitting layer portion 24 with the light emitting layer portion 24 or the contact side with the p-GaP single crystal substrate 7. , 20 is formed. The contact layer 30 has a thickness of 1 nm to 20 nm (desirably 5 nm to 10 nm) in order to reduce the influence of light absorption.
[0051]
  Between each contact layer 30 and the light emitting layer portion 24 or between the p-GaP single crystal substrate 7, the contact layer and the light emitting layer portion 24 (cladding layer) or the p-GaP single crystal substrate 7 are connected. An intermediate layer 31 having an intermediate band gap energy is formed. The intermediate layer 31 can be configured to include at least one of AlGaAs, GaInP, and AlGaInP, for example. In the present embodiment, each intermediate layer 31 is configured as a single AlGaAs layer.
[0052]
  In addition, for the ITO layer 10 forming the conductive oxide layer for substrate bonding, the contact layer 30 on the side close to the light emitting layer portion 24 is in the first region PA where the light extraction amount forming the region immediately below the metal electrode 9 is small. It is not formed and is selectively formed only in the second region SA with a large light extraction amount around it. Thereby, as a result of selectively increasing the series resistance in the first area PA, the bypass current density to the second area SA, that is, the periphery of the metal electrode 9 is increased, and the light extraction efficiency is increased. Such a contact layer 30 can be formed by patterning using a known photolithography technique so as not to be formed in the first region PA.
[0053]
  In this embodiment, the contact layer 30 on the p-GaP single crystal substrate 7 side of the ITO layer 10 or the contact layer 30 of the ITO layer 20 on the back side of the light emitting layer portion 24 is the entire surface of the ITO layers 10 to 20. It is formed so as to cover. However, similarly, the contact layer 30 can also be configured to be selectively formed only in the second region SA, whereby the light extraction efficiency can be further increased. Further, the intermediate layer 31 may be patterned corresponding to the contact layer 30, or the intermediate layer 31 may be formed on the entire surface of the ITO layer 10 and only the contact layer 30 may be patterned.
[0054]
  Note that the contact layer 30 on the p-GaP single crystal substrate 7 side of the ITO layer 10 has a formation region and a non-formation region mixed in the second region SA, as shown in FIGS. It can also be shaped. In this case, the ITO layer 10 is in direct contact with the light emitting layer portion 24 in the region where the contact layer 30 is not formed. The formation region of the contact layer 30 is dispersedly formed at the bonding interface of the ITO layer 10, whereby light emission in the light emitting layer portion 24 can be made more uniform, and light can be extracted more uniformly from the non-formation region of the contact layer 30. . FIG. 7A is an example in which the formation region of the contact layer 30 is formed as a dot, and FIG. 7B is an example in which the formation region of the elongated strip-shaped contact layer 30 and the non-formation region of the same shape are alternately formed. It is. Furthermore, (c) is an example in which, unlike the case of (a), the non-formation area in the form of dots is dispersedly formed with the formation area of the contact layer 30 as the background. Here, the formation region of the contact layer 30 is formed in a lattice shape. Similarly, the other contact layer 30 in FIG. 1 can be formed in a mixed form region and non-form region. Further, the intermediate layer 31 may be patterned corresponding to the contact layer 30, or only the contact layer 30 may be patterned. The patterning can be performed by a well-known photolithography technique. The above structure can be applied to the contact layer 30 in the same manner when the ITO layer 20 forming the conductive oxide layer for electrodes is provided via the contact layer 30 in the element configuration of FIG. Can be achieved.
[0055]
  Hereinafter, a method for manufacturing the light emitting device 100 of FIG. 1 will be described.
  First, as shown in Step 1 of FIG. 2, an n-type GaAs buffer layer 2 is formed on a main surface MP5 of a GaAs single crystal substrate 1 which is a semiconductor single crystal substrate forming a light emitting layer growth substrate, for example, 0.5 μm, and AlAs. The peeling layer 3 made of, for example, is epitaxially grown by 0.5 μm. Next, a GaAs layer 30 ′ and an intermediate layer 31 to be contact layers 30 later are epitaxially grown in this order. Further, as the light emitting layer portion 24, a 1 μm n-type AlGaInP cladding layer 4, a 0.6 μm AlGaInP active layer (non-doped) 5 and 1 μm p-type AlGaInP cladding layers 6 are epitaxially grown in this order. Further, a similar intermediate layer 31 and GaAs layer 30 ′ are epitaxially grown in this order on the p-type AlGaInP cladding layer 6. Note that the last intermediate layer 31 and the GaAs layer 30 'are not formed by photolithography only in a region (first region) corresponding to the metal electrode 9 (FIG. 1).
[0056]
  The intermediate layer 31 and the GaAs layer 30 'can also be basically formed by the MOVPE method or the like. In particular, for the GaAs layer 30 ′, considering the formation of the GaAs layer 30 ′ in contact with the ITO layer 10 or 20 containing In, the following process is adopted. That is, in step 1 of FIG. 2, after forming the intermediate layer 31 and then the GaAs layer 30 'on the p-type cladding layer 6 by the MOVPE method or the like, the ITO layer 10a is formed. Also in Step 3 and Step 6, after forming the intermediate layer 31 and the GaAs layer 30 'on the p-GaP single crystal substrate 7 and the n-type cladding layer 4, respectively, the ITO layers 10b and 20 are formed. Then, the ITO layers 10a and 10b are integrated by bonding to form an ITO layer 10, and in this state, heat treatment is performed at a high temperature for a short time, whereby each ITO layer 10 and 20 is transferred to the corresponding GaAs layer 30 ′. To diffuse. This will be specifically described below.
[0057]
  First, as shown in Step 2, an ITO layer 10a is formed as a transparent conductive oxide layer on the main surface MP4 of the light emitting layer portion 24 by using high frequency sputtering. On the other hand, as shown in Step 3, a similar ITO layer 10b is also formed on the main back surface MP2 of the p-GaP single crystal substrate 7 prepared separately. Then, the ITO layer 10b of the p-GaP single crystal substrate 7 is overlaid and pressed on the ITO layer 10a of the light emitting layer portion 24, and as shown in step 4, under predetermined conditions (for example, at 450 ° C. for 30 minutes). The substrate bonded body 50 is made by heat treatment. The ITO layer 10a and the ITO layer 10b are integrated to form the substrate-bonding conductive oxide layer 10.
[0058]
  Next, the process proceeds to step 5, and the substrate laminate 50 is immersed in an etching solution made of, for example, a 10% aqueous hydrofluoric acid solution, and the AlAs release layer 3 formed between the buffer layer 2 and the light emitting layer 24 is selected. By etching, the GaAs single crystal substrate 1 (which is opaque to the light from the light emitting layer 24) is peeled from the laminate 50a of the light emitting layer portion 24 and the p-GaP single crystal substrate 7 bonded thereto. To do. It should be noted that an etch stop layer made of AlInP is formed in place of the AlAs release layer 3, and a GaAs single crystal is used by using a first etching solution (for example, ammonia / hydrogen peroxide mixed solution) having selective etching properties with respect to GaAs. Etch and remove the substrate 1 together with the GaAs buffer layer 2 and then etch stop using a second etchant that has selective etching properties with respect to AlInP (for example, hydrochloric acid: hydrofluoric acid may be added to remove the Al oxide layer) A step of etching away the layer can also be employed.
[0059]
  Next, as shown in Step 6, the ITO layer 20 is formed so as to cover the intermediate layer 31 and the GaAs layer 30 ′ formed on the main back surface MP3 of the light emitting layer 24 exposed by the peeling of the GaAs single crystal substrate 1. Form. The laminated wafer thus obtained (either before or after the electrode 9 is formed) may be placed in a furnace and, for example, in a nitrogen atmosphere or an inert gas atmosphere such as Ar The heat treatment is performed at a low temperature of 600 ° C. to 750 ° C. (eg, 700 ° C.) for a short time of 5 seconds to 120 seconds (eg, 30 seconds). As a result, In diffuses from the ITO layers 10 and 20 to the GaAs layer 30 ′, and the contact layer 30 (FIG. 1 and the like) made of GaAs containing In is obtained. This heat treatment can be performed each time a GaAs layer and an ITO layer covering the GaAs layer are formed. However, as described above, the heat treatment is collectively performed after all the ITO layers are formed. This is advantageous because the process is simplified, and the sequential heat treatment does not cause a problem that the In diffusion is accumulated and excessive as much as the previously formed GaAs layer 30 ′.
[0060]
  In FIG. 3 (1), the contact layer 30 has an In concentration in the vicinity of the interface with the ITO transparent electrode layer of 0.1 or more and 0.6 or less in terms of the atomic ratio of In to the total concentration of In and Ga. Is done. Also, the In concentration decreases continuously as it moves away from the ITO layer in the thickness direction, and the In concentration near each boundary with the ITO layer is expressed as C_AAnd the In concentration near the boundary on the opposite side is C_BWhen C_B/ C_AIs adjusted to 0.8 or less.
[0061]
  The contact layer 30 is formed by first forming a GaAs layer 30 ′ having good lattice matching with the light emitting layer portion 24 made of AlGaInP and the p-GaP substrate 7, and further forming an ITO layer, and then forming the ITO layer at a relatively low temperature for a short time. By performing the heat treatment, the In content is not excessive, and is homogeneous and has good continuity. As a result, it is possible to effectively prevent quality degradation such as reduction in emission intensity due to lattice mismatch. Thereafter, the semiconductor chip is diced by a usual method, and this is fixed to a support and wire bonding of a lead wire is performed, followed by resin sealing to obtain a final light emitting element.
[0062]
  The ITO layer 20 formed last is used as an electrode on the back side, and is composed of ITO which is a conductive oxide, thereby realizing a light extraction function and a current diffusion function. In order to enhance the current spreading function, it is important to reduce the sheet resistance (or electrical specific resistance) of the ITO layer 20, and in order to enhance the light extraction function, the ITO layer 20 is formed as thick as necessary. Even in such a case, it is important to ensure sufficient light transmission. For example, when the ITO layer 20 is formed by sputtering, it is desirable to set the sputtering voltage as low as possible in order to reduce the sheet resistance. This is because when negative ions (mainly oxygen ions) contained in the sputtering plasma are incident on the ITO layer being deposited at a high speed, insulating InO is likely to be formed, but when the acceleration voltage is lowered, the InO This is because the formation of is suppressed. In order to reduce the sputtering voltage, it is necessary to increase the magnetic field strength during sputtering to a certain level (for example, 0.8 kG or more: it is desirable to set it to 2000 G or less because the voltage reduction effect is saturated). It is valid. The reduction in sheet resistance becomes significant by setting the absolute value of the cathode voltage to 350 V or less, preferably 250 V or less, for example. If the magnetic field strength is set to 1000 G or more, for example, the sputtering voltage can be easily adjusted to 250 V or less in terms of the absolute value of the cathode voltage.
[0063]
  In order to obtain a uniform ITO layer having a high light transmittance, and to easily and firmly bond the light emitting layer portion and the transparent conductive semiconductor substrate, the ITO layer is not formed with a clear crystal grain boundary. It is advantageous to have a crystalline layer. In order to obtain an amorphous ITO layer, it is necessary to form a film at a low temperature of 200 ° C. or lower in order to prevent crystallization of ITO. In this case, in order to obtain a low resistance ITO layer, it is effective to combine with the above sputtering conditions. In particular, in order to obtain a uniform and low resistivity ITO layer even at a low temperature, water vapor is introduced into the sputtering atmosphere. Is effective (eg 3 × 10^-3Pa or more 15 × 10^-3Pa or less). If the water vapor partial pressure in the sputtering atmosphere is excessively low, the resulting ITO layer is more likely to be microcrystallized and the light transmittance and sheet resistance are significantly increased. Thus, this microcrystallization can be effectively suppressed. As a result, an ITO layer having a light transmittance of 90% or more (preferably 95% or more) and a specific resistance of 1000 μΩ · cm or less (preferably 800 μΩ · cm or less) can be realized.
[0064]
  Further, it is important for the ITO layer 20 to have a uniform and large current spreading effect in order to realize uniform and high luminous efficiency. For this purpose, it is necessary to increase the smoothness of the surface of the ITO layer in addition to the configuration of the ITO layer having a uniform and low resistivity. When the smoothness of the surface is lowered, a large number of protrusions that tend to concentrate an electric field are easily formed, and a local dark place is likely to be generated due to non-uniformity of the voltage applied to the light emitting layer portion 24, or leakage current is generated. This leads to a decrease in luminous efficiency itself. In order to prevent these problems, the surface roughness of the ITO layer is specifically the value of Rmax when the evaluation area is 0.2 μm square by three-dimensional surface topography using an atomic force microscope (AFM). It is desirable to set to 10 nm or less (for example, 4 nm to 7 nm).
[0065]
  In order to smooth the surface of the ITO layer as described above, it is effective to polish the surface after forming the ITO layer. However, since mechanical polishing is expensive, it is desirable to employ chemical polishing. As a chemical polishing liquid for ITO, for example, a mixed liquid of hydrochloric acid and nitric acid or an aqueous oxalic acid solution can be employed. In this case, if the ITO layer is finely crystallized as described above, etching is likely to proceed at the grain boundaries, so that surface roughening due to grain boundary erosion or degranulation is likely to occur. Therefore, in order to obtain a homogeneous amorphous layer, introduction of water vapor into the sputtering atmosphere can be an effective method for reducing the surface roughness of the ITO layer after chemical polishing as described above.
[0066]
  For example, in order to maximize the light emission intensity of a large-area surface-emitting element (for example, one side is 300 μm), it is important to flow as much current as possible through the large-area ITO layer. Accordingly, when the present invention is applied to a surface-emitting element having a large area, it is particularly advantageous to employ an ITO layer that is smooth, has a low resistivity, and has a high light transmittance as described above. I can say that.
[0067]
  In FIG. 1, the contact layer 30 on the light emitting layer portion 24 side may be formed as having the same conductivity type as the cladding layers 6 to 4 in contact with the contact layer 30 by adding an appropriate dopant. Are formed as a thin layer as described above, these are lightly doped layers having a low dopant concentration (for example, 10¹⁷Piece / cm³Or less; or a non-doped layer (10¹³Piece / cm³-10¹⁶Piece / cm³)) Does not cause an excessive increase in series resistance, and can be employed without any problem. On the other hand, when the lightly doped layer is used, the following effects can be achieved depending on the driving voltage of the light emitting element. That is, by making the contact layer 30 a lightly doped layer, the electrical resistivity of the layer itself is increased. Therefore, the layer of the contact layer 30 with respect to the cladding layer or the ITO layers 10 and 20 having a low electrical resistivity sandwiching the contact layer 30. The electric field (that is, the voltage per unit distance) applied in the thickness direction becomes relatively high. At this time, if the contact layer 30 is formed of GaAs containing In having a relatively small band gap, an appropriate bending occurs in the band structure of the contact layer by the application of the electric field, and a better ohmic contact can be obtained. Can be formed. As shown in FIG. 3, the In concentration of the contact layer 30 is increased on the contact side with the ITO layers 10 and 20, so that the effect becomes more remarkable.
[0068]
  In addition, like the light emitting element 200 shown in FIG. 8, the main back surface MP6 of the ITO layer 20 can be covered with a metal reflective layer 21 such as Au. According to this configuration, the light emitted from the light emitting layer portion 24 to the main back surface side is reflected by the metal reflective layer 21, and the reflected light is directly emitted from the light emitting layer portion 24 to the p-GaP single crystal substrate 7 side. Therefore, the emission intensity on the side can be greatly increased. Further, like the light emitting element 300 shown in FIG. 9, the entire surface of the main surface MP1 of the p-GaP single crystal substrate 7 is covered with a metal reflective layer 21 that also serves as an electrode, and the reflected light and the light emitted by the metal reflective layer 21 are emitted. The light directly emitted from the layer part 24 to the main back surface side can be superimposed and extracted from the ITO layer 20 side.
[0069]
  Further, as shown in FIG. 10, steps 1 to 5 are performed in the same manner as in FIG. A GaP single crystal substrate 23 (n-type in this embodiment) which is a transparent conductive semiconductor substrate can also be bonded. Specifically, the ITO layer 20a is formed on the main back surface MP3 of the light emitting layer portion 24, and the ITO layer 20b is formed on the main surface MP7 of the GaP single crystal substrate 23 via the intermediate layer 31 and the GaAs layer 30 ′, respectively. As in steps 3 and 4, bonding is performed by heat treatment. After the bonding, for example, as illustrated in FIG. 11, the metal electrode layer 21 of the GaP single crystal substrate 23 can be formed to form the light emitting element 400.
[0070]
  In the light emitting element 500 shown in FIG. 12, the main surface of the light emitting layer 24 opposite to the surface facing the transparent conductive semiconductor substrate 23 is the conductive oxide layer 20 for electrodes that also serves as a transparent electrode. The metal electrode 9 is formed so as to cover a part of the electrode conductive oxide layer 20, and the region around the metal electrode 9 of the electrode conductive oxide layer 20 is optically covered. It is used as a take-out surface. The transparent conductive semiconductor substrate 23 is an n-GaP single crystal substrate 23, and the electrode conductive oxide layer 20 is an ITO layer 20. The n-GaP single crystal substrate 23 is similar to the light emitting device 100 of FIG. 1 in that the ITO layer 10 (contact layer 30 and intermediate layer 31 are formed on both sides of the ITO layer 10 from both sides). The light emitting layer portion 24 is bonded to the n-type clad layer 4 side. Further, the entire back surface of the n-GaP single crystal substrate 23 is covered with a metal electrode 21 (for example, an Au electrode) that also serves as a reflective layer. On the other hand, a contact layer 30 and an intermediate layer 31 are formed in this order from the ITO layer 20 side between the ITO layer 20 and the p-type cladding layer 6. The contact layer 30 is not formed in the first region PA that forms a region immediately below the metal electrode 16 and has a small light extraction amount, but is selectively formed only in the second region SA that has a large light extraction amount around it. The composition and thickness of the contact layer 30 and the intermediate layer 31 are the same as those of the contact layer 30 and the intermediate layer 31 formed in contact with the p-type cladding layer 6 in the light emitting device of FIG. Patterning is possible in the same manner (patterning of the intermediate layer 31 may be omitted in the same manner as the element of FIG. 1).
[0071]
  An example of the manufacturing method of the above-mentioned element is shown in FIG. 13 (the same steps as in FIG. 2 can be adopted for the parts without particular notice). Step 1 is substantially the same as Step 1 in FIG. 2 except that the p-type GaAs substrate 1 is used, and the p-type cladding layer 6, the active layer 5, and the n-type cladding layer 4 that form the light emitting layer portion 24 are formed thereon. They are formed in the reverse order of FIG. Next, in step 2, an intermediate layer 31 and a GaAs layer 30 'are formed in this order on the main surface on one side of the n-GaP single crystal substrate 23, and an ITO layer 10b is further formed. The ITO layer 10a is also formed on the GaAs layer 30 'on the n-type cladding layer 4 side of the light emitting layer portion 24. Then, the ITO layer 10b of the n-GaP single crystal substrate 23 is superposed on the ITO layer 10a of the light emitting layer portion 24 and pressed, and heat treatment is performed under a predetermined condition (for example, at 450 ° C. for 30 minutes). Matching is performed (step 3). In step 4, the GaAs substrate 1 is peeled off, and in step 5, the exposed GaAs layer 30 'is patterned by photolithography so as to remove the first region. Then, as shown in Step 6, an ITO layer 20 is formed on the patterned GaAs layer 30 ', and a short-time heat treatment for In diffusion is performed. Thereafter, electrodes 9 and 21 are formed.
[0072]
  In the embodiment described above, each layer of the light emitting layer portion 24 is formed of an AlGaInP mixed crystal. However, each layer (p-type cladding layer 6, active layer 5 and n-type cladding layer 4) is formed of an AlGaInN mixed crystal. By doing so, a wide gap type light emitting element for blue or ultraviolet light emission can be configured. The light emitting layer portion 24 is formed by the MOVPE method in the same manner as the light emitting element 100 of FIG. In this case, for example, a sapphire substrate (insulator) is used instead of the GaAs single crystal substrate as the semiconductor single crystal substrate forming the light emitting layer growth substrate for growing the light emitting layer portion 24.
[0073]
  Furthermore, although the active layer 5 is formed as a single layer in the above embodiment, it is formed by stacking a plurality of compound semiconductor layers having different band gap energies, specifically, having a quantum well structure. It can also be configured. The active layer having a quantum well structure has two layers having different band gaps by adjusting the mixed crystal ratio, that is, a well layer having a small band gap energy and a barrier layer having a large band gap energy. The layers are stacked so as to be lattice-matched so as to be generally (one atomic layer to several nm). In the above structure, since the energy of electrons (or holes) in the well layer is quantized, for example, when applied to a semiconductor laser, the oscillation wavelength can be freely adjusted by the width and depth of the energy well layer, This is effective in stabilizing the oscillation wavelength, improving the light emission efficiency, and further reducing the oscillation threshold current density. Furthermore, since the thickness of the well layer and the barrier layer is very small, the deviation of the lattice constant is allowed up to about 2 to 3%, and the oscillation wavelength region can be easily expanded. The quantum well structure may be a multiple quantum well structure having a plurality of well layers, or a single quantum well structure having only one well layer. The thickness of the barrier layer can be, for example, about 50 nm only for the layer in contact with the cladding layer, and about 6 nm for others. The well layer can be about 5 nm.
[Brief description of the drawings]
FIG. 1 is a schematic view showing a first embodiment of a light emitting device of the present invention in a laminated structure.
2 is an explanatory view showing a manufacturing process of the light-emitting element of FIG. 1. FIG.
FIG. 3 is a conceptual diagram showing an example of an In concentration distribution in a contact layer.
FIG. 4 is a conceptual diagram showing a modification of the In concentration distribution in the contact layer.
FIG. 5 is a schematic diagram showing an example of a band structure of a contact layer when an intermediate layer is not formed.
FIG. 6 is a schematic diagram showing an example of a band structure of a contact layer when an intermediate layer is formed.
7 is a schematic diagram showing various patterning forms of a contact layer of the light emitting element of FIG. 1. FIG.
FIG. 8 is a schematic view showing a second embodiment of the light emitting element of the present invention in a laminated structure.
FIG. 9 is a schematic view showing a third embodiment of the light emitting element of the present invention in a laminated structure.
10 is an explanatory view showing a first modification of the manufacturing process of FIG. 2. FIG.
FIG. 11 is a schematic view showing a fourth embodiment of the light emitting device of the present invention in a laminated structure.
FIG. 12 is a schematic view showing a fifth embodiment of the light emitting device of the present invention in a laminated structure.
13 is a process explanatory diagram illustrating an example of a method for manufacturing the light-emitting element of FIG. 12;
[Explanation of symbols]
  1 GaAs single crystal substrate (light emitting layer growth substrate)
  4 n-type cladding layer (second conductivity type cladding layer)
  5 Active layer
  6 p-type cladding layer (first conductivity type cladding layer)
  7,23 GaP single crystal substrate (transparent conductive semiconductor substrate)
  9 Metal electrode
  10 ITO layer (conductive oxide layer for substrate bonding)
  20 ITO layer (conductive oxide layer)
  24 Light emitting layer
  30 Contact layer
  30 'GaAs layer
  31 Middle layer
  100, 200, 300, 400, 500 Light emitting element

Claims (1)

A light emitting layer portion made of a compound semiconductor is bonded to one main surface of a transparent conductive semiconductor substrate via a substrate bonding oxide layer made of a conductive oxide, and the light emitting layer portion and the substrate bonding material are bonded together. Manufactures a light emitting device in which a contact layer for reducing the junction resistance of the conductive oxide layer for bonding the substrate is disposed between the conductive oxide layer and the conductive oxide layer for bonding the substrate. To do
A light emitting layer portion growth step of epitaxially growing a light emitting layer portion made of a compound semiconductor on the first main surface of the substrate for light emitting layer growth;
A contact layer forming step of forming a layer to be a contact layer on the light emitting layer portion to reduce a junction resistance of the substrate-bonding conductive oxide layer;
A substrate-bonding conductive oxide layer forming step of forming the light-emitting layer portion and / or the substrate-bonding conductive oxide layer on the bonding surface side of the transparent conductive semiconductor substrate;
By laminating the light emitting layer portion and the transparent conductive semiconductor substrate via the substrate-bonding conductive oxide layer, the layer to be the contact layer is in contact with the substrate-bonding conductive oxide layer. A bonding process for making a substrate bonded body arranged in
A peeling step of peeling the substrate for light emitting layer growth from the substrate bonded body,
In the contact layer forming step, a GaAs layer to be the contact layer is formed, and an ITO layer forming the substrate-bonding conductive oxide layer is formed so as to be in contact with the GaAs layer, and then heat-treated, While diffusing In from the ITO layer to the GaAs layer, forming the contact layer as a GaAs layer containing In ,
The average In concentration of the contact layer is 0.1 or more and 0.6 or less in terms of the atomic ratio of In to the total concentration of In and Ga, and the In of the contact layer at the boundary position with the ITO layer _A method for manufacturing a light-emitting element, characterized in that a concentration is C _A , an In concentration at a boundary position on the opposite side is C _B , and C _B / C _A is 0.8 or less .

Images