US11855587B2 - Power amplifier circuit - Google Patents

Power amplifier circuit Download PDF

Info

Publication number
US11855587B2
US11855587B2 US16/913,585 US202016913585A US11855587B2 US 11855587 B2 US11855587 B2 US 11855587B2 US 202016913585 A US202016913585 A US 202016913585A US 11855587 B2 US11855587 B2 US 11855587B2
Authority
US
United States
Prior art keywords
transistor
current
base
bias
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US16/913,585
Other languages
English (en)
Other versions
US20200412304A1 (en
Inventor
Takashi Soga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Assigned to MURATA MANUFACTURING CO., LTD. reassignment MURATA MANUFACTURING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SOGA, TAKASHI
Publication of US20200412304A1 publication Critical patent/US20200412304A1/en
Application granted granted Critical
Publication of US11855587B2 publication Critical patent/US11855587B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/302Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in bipolar transistor amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32Modifications of amplifiers to reduce non-linear distortion
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/191Tuned amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/363Transistor with multiple emitters
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/447Indexing scheme relating to amplifiers the amplifier being protected to temperature influence
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/451Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the present disclosure relates to a power amplifier circuit.
  • the power amplifier circuit includes, for example, a bipolar transistor for amplifying input signals and a bias circuit for determining an operating point for the bipolar transistor.
  • Bipolar transistors have the thermal positive-feedback characteristic in which, when the temperature of the device increases, the collector current increases; this in turn increases the temperature of the device; and the collector current further increases.
  • Japanese Unexamined Patent Application Publication No. 2018-98766 discloses a power amplifier circuit in which a resistance element (hereinafter also referred to as a ballast resistor) is inserted between the base of a bipolar transistor and a bias circuit.
  • a resistance element hereinafter also referred to as a ballast resistor
  • the present disclosure provides a power amplifier circuit that can hinder linearity deterioration due to increase in input power.
  • a power amplifier circuit includes an amplifier transistor configured to amplify an input signal, a resistance element coupled in series with the base of the amplifier transistor, a bias transistor configured to supply a bias current from the emitter or the source of the bias transistor to the base of the amplifier transistor through the resistance element, and a feedback circuit configured to change a base or gate voltage of the bias transistor to follow a change in the bias current supplied to the base of the amplifier transistor.
  • the present disclosure can provide a power amplifier circuit that can hinder linearity deterioration due to increase in input power.
  • FIG. 1 illustrates an example of a configuration of a power amplifier circuit according to a first embodiment of the present disclosure
  • FIG. 2 is a graph illustrating a relationship between output power of RF signal and bias current with respect to the power amplifier circuit according to the first embodiment of the present disclosure and a power amplifier circuit according to a comparative example;
  • FIG. 3 is a graph illustrating a relationship between output power of RF signal and bias voltage with respect to the power amplifier circuit according to the first embodiment of the present disclosure and the power amplifier circuit according to the comparative example;
  • FIG. 4 is a graph illustrating a relationship between output power of RF signal and base-emitter voltage of transistor with respect to the power amplifier circuit according to the first embodiment of the present disclosure and the power amplifier circuit according to the comparative example;
  • FIG. 5 is a graph illustrating a relationship between output power of RF signal and power gain with respect to the power amplifier circuit according to the first embodiment of the present disclosure and the power amplifier circuit according to the comparative example;
  • FIG. 6 illustrates an example of a configuration of a power amplifier circuit according to a second embodiment of the present disclosure
  • FIG. 7 illustrates an example of a configuration of a power amplifier circuit according to a third embodiment of the present disclosure
  • FIG. 8 illustrates an example of a configuration of a power amplifier circuit according to a fourth embodiment of the present disclosure.
  • FIG. 9 illustrates an example of a configuration of a power amplifier circuit according to a fifth embodiment of the present disclosure.
  • FIG. 1 illustrates an example of a configuration of a power amplifier circuit according to a first embodiment of the present disclosure.
  • a power amplifier circuit 100 according to the present embodiment is provided in, for example, a mobile communication device such as a mobile phone and used for amplifying electric power of radio frequency (RF) signals to be transmitted to base stations.
  • the power amplifier circuit 100 amplifies transmit signals of communication standards such as the second-generation (2G) mobile communication system, the third-generation (3G) mobile communication system, the fourth-generation (4G) mobile communication, the fifth-generation (5G) mobile communication system, Long-Term Evolution Frequency-Division Duplex (LTE-FDD), Long-Term Evolution Time-Division Duplex (LTE-TDD), LTE-Advanced, and LTE-Advanced Pro.
  • the frequency range of the fundamental wave of RF signals is, for example, from approximately several hundreds of MHz to several tens of GHz.
  • the communication standard and the frequency of signals amplified by the power amplifier circuit 100 are not limited to these examples.
  • the power amplifier circuit 100 includes, for example, a transistor 110 , a bias circuit 120 , a feedback circuit 130 , capacitors C 1 and C 2 , inductors L 1 and L 2 , and a resistance element R 1 .
  • the transistor 110 (an amplifier transistor) amplifies an RF signal RFin (an input signal) and outputs an RF signal RFout.
  • the transistor 110 is configured by using a bipolar transistor such as a heterojunction bipolar transistor (HBT).
  • HBT heterojunction bipolar transistor
  • a power supply voltage Vcc is supplied to the collector through the inductor L 1 ; an RF signal RFin is inputted to the base through the capacitor C 1 ; and the emitter is grounded.
  • a bias current is supplied to the base of the transistor 110 from the bias circuit 120 through the inductor L 2 and the resistance element R 1 .
  • the RF signal RFout obtained by amplifying the RF signal RFin is outputted from the collector of the transistor 110 .
  • the bias circuit 120 determines an operating point of the transistor 110 by supplying a bias current or voltage to the base of the transistor 110 .
  • the bias circuit 120 adjusts the operating point of the transistor 110 by adjusting the level of the bias current or voltage in accordance with, for example, a control current Icont supplied to an input terminal T 1 .
  • the control current Icont is a current that flows along a control path X 1 connecting a control terminal T 2 to the input terminal T 1 .
  • the control current Icont includes a reference current Iref that is supplied to the control terminal T 2 . It should be noted that in this specification terminals such as the input terminal T 1 and the control terminal T 2 are not limited to physical terminals and include particular imaginary points on the path.
  • the bias circuit 120 includes transistors 121 to 123 .
  • the transistors 121 to 123 are configured by using, for example, HBTs and formed on a single chip by a bipolar process.
  • the collector and the base are coupled to each other (hereinafter also referred to as diode connection); the control current Icont is supplied to the collector; and the emitter is coupled to the collector of the transistor 122 .
  • the transistor 122 is subjected to diode connection; the collector is coupled to the emitter of the transistor 121 ; and the emitter is grounded.
  • a voltage for example, approximately 2.6 V
  • the control current Icont is generated.
  • the transistor 123 (a bias transistor)
  • a battery voltage Vbatt is supplied to the collector; the base is coupled to the collector of the transistor 121 ; and the emitter is coupled to the base of the transistor 110 via the inductor L 2 and the resistance element R 1 .
  • the base voltage of the transistor 123 changes in accordance with the control current Icont supplied to the transistor 121 .
  • the bias circuit 120 supplies a bias current Ibias 1 corresponding to the base voltage of the transistor 123 , that is, the collector voltage of the transistor 121 , from the emitter of the transistor 123 to the base of the transistor 110 . Furthermore, the bias circuit 120 determines the operating point of the transistor 110 by supplying a bias voltage Vb from the emitter of the transistor 123 to the base of the transistor 110 .
  • the bias voltage Vb is a voltage at one end of the resistance element R 1 on the bias circuit 120 side.
  • the control current Icont will be described in detail later.
  • the RF signal RFin is inputted to one end; and the other end is coupled to the base of the transistor 110 .
  • the capacitor C 1 blocks a direct current component of RF signal and passes an alternating current component.
  • the power supply voltage Vcc is supplied to one end; and the other end is coupled to the collector of the transistor 110 .
  • the inductor L 1 hinders transmission of RF signals to a power supply circuit (not illustrated in the drawing) side.
  • the capacitor C 2 one end is coupled to the emitter of the transistor 123 and the other end is grounded.
  • the inductor L 2 is coupled in series between the emitter of the transistor 123 and the resistance element R 1 .
  • the capacitor C 2 and the inductor L 2 both have a function of filter circuit of hindering transmission of RF signals to the bias circuit 120 side.
  • the power amplifier circuit 100 may exclude at least either the capacitor C 2 or the inductor L 2 .
  • the resistance element R 1 one end is coupled to an output terminal of the bias circuit 120 , that is, the emitter of the transistor 123 , via the inductor L 2 ; and the other end is coupled to the base of the transistor 110 .
  • the resistance element R 1 is a ballast resistor coupled in series with the base of the transistor 110 . This means that the transistor 110 has the thermal positive-feedback characteristic in which, when the temperature of the device increases, the collector current increases; this in turn increases the temperature of the device; and the collector current further increases.
  • Providing a ballast resistor for the base of the transistor 110 causes voltage drop determined as the product of the resistance of the ballast resistor and the base current of the transistor 110 . As the base current of the transistor 110 increases, voltage drop across the ballast resistor increases and the bias voltage of the transistor 110 thus decreases, and as a result, increase in the collector current is hindered.
  • the average value of the bias current Ibias 1 supplied from the bias circuit 120 by following the alternating voltage waveform of RF signal, which is the average base current of the transistor 110 increases.
  • the average base current increases, voltage drop across the resistance element R 1 excessively increases, and consequently, the base voltage of the transistor 110 falls more than is needed.
  • a base-emitter voltage Vbe of the transistor 110 decreases and power gain accordingly decreases, and as a result, linearity may deteriorate.
  • the power amplifier circuit 100 includes the feedback circuit 130 .
  • the feedback circuit 130 a specific configuration and operations of the feedback circuit 130 are described.
  • the feedback circuit 130 subjects the control current Icont to positive feedback in accordance with changes of the average value of the bias current Ibias 1 supplied to the base of the transistor 110 , such that the base voltage of the transistor 123 is caused to follow the changes in the bias current Ibias 1 .
  • the feedback circuit 130 includes a detection circuit 140 , a current mirror circuit 150 , an offset circuit 160 , and a filter circuit 170 .
  • the detection circuit 140 detects changes of the average value of the bias current Ibias 1 flowing into the base of the transistor 110 and outputs a current Ia that changes along with the changes of the average value of the bias current Ibias 1 .
  • the detection circuit 140 includes a transistor 141 and a resistance element R 2 .
  • the transistor 141 (a replica transistor) is configured by using, for example, an HBT.
  • the battery voltage Vbatt is supplied to the collector through a transistor 151 described below; the base is coupled to the emitter of the transistor 123 via the resistance element R 2 and the inductor L 2 ; and the emitter is grounded.
  • the resistance element R 2 one end is coupled to the emitter of the transistor 123 via the inductor L 2 and the other end is coupled to the base of the transistor 141 .
  • the resistance element R 2 is a ballast resistor coupled in series with the base of the transistor 141 .
  • a bias current Ibias 2 (a first current), which is proportional to the bias current Ibias 1 supplied to the base of the transistor 110 , is supplied to the base of the transistor 141 .
  • the current Ia (a second current), which is determined by multiplying the bias current Ibias 2 by hfe, flows in the collector of the transistor 141 .
  • the transistor 141 mimics the amplification behavior of the transistor 110 and outputs the current Ia obtained by copying the bias current Ibias 1 of the transistor 110 .
  • the transistor 141 may be identical to or different from the transistor 110 with respect to size.
  • the transistor 110 , the capacitor C 1 , the resistance element R 1 , the transistor 141 , and the resistance element R 2 may be formed as a single cell 200 (indicated by the dashed line in FIG. 1 ). While FIG. 1 illustrates one cell 200 , the power amplifier circuit 100 may include a plurality of cells having the same configuration as that of the cell 200 .
  • the current mirror circuit 150 generates a current Ib (a third current) proportional to the current Ia outputted from the detection circuit 140 and supplies the current Ib to the control path X 1 .
  • the current mirror circuit 150 includes a pair of transistors 151 and 152 .
  • the transistors 151 and 152 in pair are configured by using, for example, P-channel metal-oxide-semiconductor field-effect transistors (MOSFETs).
  • the battery voltage Vbatt is supplied to the source; the gate is coupled to the drain; and the drain is coupled to the collector of the transistor 141 of the detection circuit 140 .
  • the battery voltage Vbatt is supplied to the source; the gate is coupled to the gate of the transistor 151 ; and the drain is coupled to the control path X 1 .
  • the transistor 152 is smaller in size than the transistor 151 . This means that the current Ib flowing in the transistor 152 is less than the current Ia flowing in the transistor 151 .
  • the proportion of the transistor 152 and the transistor 151 in size is not particularly specified; for example, when the gain of the transistor 141 is hfe, the current Ib flowing in the transistor 152 can be substantially a current obtained by dividing the current Ia flowing in the transistor 151 by hfe. In this case, the current Ib flowing in the transistor 152 is almost equal in amount to the bias current Ibias 2 supplied to the base of the transistor 141 .
  • the current mirror circuit 150 supplies the current Ib proportional to the bias current Ibias 1 of the transistor 110 to the control path X 1 to add the current Ib to the reference current Iref.
  • the offset circuit 160 ejects a predetermined current Ic (a fourth current) from the current Ib added to the control path X 1 by the current mirror circuit 150 .
  • the offset circuit 160 includes, for example, a current source 161 .
  • One end of the current source 161 is coupled to the control path X 1 and the other end is grounded.
  • the current Ic supplied by the current source 161 may be substantially equal in amount to the current Ib outputted by the current mirror circuit 150 .
  • the filter circuit 170 is provided between the control terminal T 2 and the input terminal T 1 of the bias circuit 120 .
  • the filter circuit 170 has the frequency characteristic of attenuating at least a signal of a frequency component (for example, approximately several hundreds of MHz to several tens of GHz) of a fundamental wave of RF signal and a signal of a frequency component (for example, approximately several MHz to several tens of MHz) of a modulated wave of RF signal.
  • the filter circuit 170 may be, for example, a low-pass filter circuit that attenuates at least a signal of a frequency equal to or greater than the frequency of a modulated wave.
  • the filter circuit 170 in the present embodiment is an L-type low-pass filter circuit including a resistance element R 3 coupled in series with the control path X 1 and a capacitor C 3 having one end coupled to the control path X 1 and the other end grounded.
  • the configuration of the low-pass filter circuit is not limited to this example and may be, for example, T-type or a combination of T-type and L-type filter circuits.
  • an RF signal may be inputted to the base of the transistor 141 through the resistance elements R 1 and R 2 .
  • the alternating current component included in the bias current Ibias 2 is also included in the current Ib supplied to the control path X 1 by the current mirror circuit 150 .
  • the filter circuit 170 has a function of attenuating the alternating current component included in the current Ib before the alternating current component is supplied to the bias circuit 120 .
  • the detection circuit 140 detects the increase in the bias current Ibias 1 and outputs the current Ia proportional to the bias current Ibias 1 .
  • the current mirror circuit 150 adds the current Ib proportional to and less than the current Ia to the reference current Iref.
  • the control current Icont increases, the current flowing between the collector and the emitter of the transistor 121 increases, and thus, the collector voltage of the transistor 121 rises. Accordingly, the base voltage of the transistor 123 rises; the emitter voltage in turn rises; and the bias voltage Vb of the transistor 110 increases. As a result, decrease in the base voltage of the transistor 110 due to increase in the output power of RF signal is suppressed and linearity is thus improved.
  • FIGS. 2 to 5 are graphs illustrating simulation results of various values obtained in the power amplifier circuit 100 in FIG. 1 and a power amplifier circuit according to the comparative example.
  • solid lines indicate results of the power amplifier circuit 100
  • dashed lines indicate results of the power amplifier circuit according to the comparative example.
  • the comparative example has a configuration formed by excluding the feedback circuit 130 from the power amplifier circuit 100 illustrated in FIG. 1 .
  • FIG. 2 is a graph illustrating a relationship between the output power of RF signal and the bias current Ibias 1 of the transistor 110 .
  • the vertical axis indicates the bias current Ibias 1 (A) of the transistor 110 and the horizontal axis indicates the output power (dBm) of RF signal.
  • FIG. 3 is a graph illustrating a relationship between the output power of RF signal and the bias voltage Vb of the transistor 110 .
  • the vertical axis indicates the bias voltage Vb (V) of the transistor 110 and the horizontal axis indicates the output power (dBm) of RF signal.
  • FIG. 4 is a graph illustrating a relationship between the output power of RF signal and the base-emitter voltage Vbe of the transistor 110 .
  • the vertical axis indicates the base-emitter voltage Vbe (V) of the transistor 110 and the horizontal axis indicates the output power (dBm) of RF signal.
  • the bias voltage Vb of the transistor 110 decreases along with increase in the output power.
  • voltage drop across the ballast resistor also increases along with the increase in output power.
  • the base-emitter voltage Vbe of the transistor 110 significantly decreases along with increase in the output power.
  • FIG. 5 is a graph illustrating a relationship between the output power of RF signal and the power gain of the transistor 110 .
  • the vertical axis indicates the power gain (dB) of the transistor 110 and the horizontal axis indicates the output power (dBm) of RF signal.
  • the power amplifier circuit 100 (solid line) according to the present embodiment, since decrease in the base-emitter voltage of the transistor 110 is suppressed as described above, the power gain starts falling at a higher level of output power in comparison to the comparative example (dashed line). According to this graph, it is understood that linearity of the power amplifier circuit 100 is improved as compared to the comparative example.
  • the power amplifier circuit 100 includes HBTs and MOSFETs and may be fabricated by employing, for example, a bipolar field-effect transistor (BiFET) or bipolar complementary metal-oxide-semiconductor (BiCMOS) process.
  • BiFET is a manufacturing process of forming a bipolar transistor and a FET together as a single chip.
  • BiCMOS is a manufacturing process of forming a bipolar transistor and a CMOS together as a single chip.
  • a reference voltage that is a constant voltage may be supplied to the control terminal T 2 .
  • an element such as a resistance element may be provided between the control terminal T 2 and the input terminal T 1 and a current corresponding to the reference voltage may be supplied to the collector of the transistor 121 .
  • the configuration in which the power of RF signal is amplified in one stage is presented.
  • This configuration may be applied to a power amplifier circuit in which electric power is amplified in two or more stages.
  • this configuration may be used as, for example, an amplifier in the last stage. Because the power of RF signal in the last stage is relatively high in comparison to amplifiers of other stages, providing the feedback circuit 130 in the last stage is highly effective. In this case, the amplifiers of other stages may not necessarily include the feedback circuit 130 .
  • FIG. 6 illustrates an example of a configuration of a power amplifier circuit according to a second embodiment of the present disclosure.
  • the second and subsequent embodiments descriptions about specifics common to the first embodiment are not repeated and only different points are explained.
  • almost identical effects and advantages achieved by almost identical configurations are not mentioned in every embodiment.
  • a power amplifier circuit 100 A according to the second embodiment includes a feedback circuit 130 A instead of the feedback circuit 130 as compared to the power amplifier circuit 100 according to the first embodiment described above.
  • the feedback circuit 130 A further includes an inductor L 3 and also includes a current mirror circuit 150 A instead of the current mirror circuit 150 .
  • the inductor L 3 is coupled in series between the emitter of the transistor 123 of the bias circuit 120 and the base of the transistor 141 of the detection circuit 140 . This means that the inductor L 3 is coupled in series with the resistance element R 2 .
  • the inductor L 3 suppresses transmission of the RF signal RFin, which is supplied to the transistor 110 , to the base of the transistor 141 through the resistance element R 1 .
  • the filter circuit 170 is provided not on the control path X 1 but between the gate of the transistor 151 and the gate of the transistor 152 in the current mirror circuit 150 A.
  • the position at which the filter circuit 170 is provided is not limited to a position on the control path X 1 , but the filter circuit 170 may be provided at any point on a path starting from an output terminal, which is the collector, of the transistor 141 and leading to the base of the transistor 123 of the bias circuit 120 via the current mirror circuit 150 A and the control path X 1 .
  • FIG. 7 illustrates an example of a configuration of a power amplifier circuit according to a third embodiment of the present disclosure.
  • a power amplifier circuit 100 B according to the third embodiment includes a bias circuit 120 A instead of the bias circuit 120 and also includes a feedback circuit 130 B instead of the feedback circuit 130 as compared to the power amplifier circuit 100 according to the first embodiment described above.
  • the bias circuit 120 A includes transistors 124 and 125 instead of the transistors 121 and 123 .
  • the transistors 124 and 125 are configured by using, for example, N-channel MOSFETs.
  • the drain and the gate are coupled to each other and the source is coupled to the collector of the transistor 122 .
  • the battery voltage Vbatt is supplied to the drain; the gate is coupled to the drain of the transistor 124 ; the source is coupled to the base of the transistor 110 via the inductor L 2 and the resistance element R 1 and also coupled to the base of the transistor 141 via the inductor L 2 and the resistance element R 2 .
  • the bias currents Ibias 1 and Ibias 2 corresponding to the control current Icont are supplied from the source of the transistor 125 respectively to the base of the transistor 110 and the base of the transistor 141 .
  • MOSFET can operate at a lower threshold voltage as compared to HBT.
  • the bias circuit 120 A can operate at lower voltage as compared to the bias circuit 120 , and thus, power consumption of the battery can be reduced.
  • the bias circuit 120 A may be fabricated by employing a BiFET process, or the transistor 122 may also be configured by using a MOSFET.
  • the feedback circuit 130 B includes a current mirror circuit 150 B instead of the current mirror circuit 150 .
  • the current mirror circuit 150 B further includes the transistors 153 and 154 .
  • the transistors 153 and 154 are configured by using, for example, P-channel MOSFETs.
  • the source is coupled to the drain of the transistor 151 ; the gate is coupled to the drain; and the drain is coupled to the collector of the transistor 141 .
  • the transistor 154 (a fourth transistor), the source is coupled to the drain of the transistor 152 ; the gate is coupled to the gate of the transistor 153 ; and the drain is coupled to the control path X 1 .
  • the transistors 153 and 154 are cascoded (i.e. cascode-connected) respectively with the transistors 151 and 152 .
  • the difference in current due to the difference in source-drain voltage between the transistors 151 and 152 is reduced.
  • the source voltage of the transistor 151 and the source voltage of the transistor 152 are equal to each other.
  • the drain voltage of the transistor 151 and the drain voltage of the transistor 152 are constant due to the gate-source voltage of the transistor 153 of a lower stage and the gate-source voltage of the transistor 154 of a lower stage.
  • the source-drain voltage of the transistor 151 and the source-drain voltage of the transistor 152 are equal to each other, and as a result, the current flowing in the transistor 151 is mirrored in the transistor 152 with improved precision.
  • the current mirror circuit 150 B may be configured by cascoding.
  • the transistors 151 to 154 included in the current mirror circuit 150 B and the transistors 124 and 125 included in the bias circuit 120 A may be formed by employing the same process.
  • FIG. 8 illustrates an example of a configuration of a power amplifier circuit according to a fourth embodiment of the present disclosure.
  • a power amplifier circuit 100 C according to the fourth embodiment includes a feedback circuit 130 C instead of the feedback circuit 130 B as compared to the power amplifier circuit 100 B according to the third embodiment described above.
  • the feedback circuit 130 C includes a current mirror circuit 150 C instead of the current mirror circuit 150 B.
  • the current mirror circuit 150 C differs from the current mirror circuit 150 B in the connection configuration of the transistors 153 and 154 .
  • the source is coupled to the drain of the transistor 151 ; the gate is coupled to the gate of the transistor 154 and a control voltage VG is supplied to the gate of the transistor 153 ; and the drain is coupled to the collector of the transistor 141 .
  • the transistor 154 the fourth transistor
  • the source is coupled to the drain of the transistor 152 ; the gate is coupled to the gate of the transistor 153 and the control voltage VG is supplied to the gate of the transistor 154 ; and the drain is coupled to the control path X 1 .
  • the current mirror circuit 150 C can achieve the same effect as that of the current mirror circuit 150 B.
  • the filter circuit 170 may be provided between the gate of the transistor 151 and the gate of the transistor 152 or between the gate of the transistor 153 and the gate of the transistor 154 .
  • FIG. 9 illustrates an example of a configuration of a power amplifier circuit according to a fifth embodiment of the present disclosure.
  • a power amplifier circuit 100 D according to the fifth embodiment includes a bias circuit 120 B instead of the bias circuit 120 as compared to the power amplifier circuit 100 according to the first embodiment described above.
  • the bias circuit 120 B further includes a transistor 126 , resistance elements R 4 and R 5 , and a capacitor C 4 .
  • the transistor 126 is configured by using, for example, an HBT.
  • the collector is coupled to the emitter of the transistor 123 via the resistance element R 5 ; the base is coupled to the base of the transistor 122 ; and the emitter is grounded.
  • the resistance element R 4 is coupled in series between the collector and the base of the transistor 126 .
  • the resistance element R 5 is coupled in series between the emitter of the transistor 123 and the collector of the transistor 126 .
  • the capacitor C 4 one end is coupled to the base of the transistor 126 and the other end is grounded. An effect of the bias circuit 120 B is described below.
  • the bias current Ibias 1 supplied from the emitter of the transistor 123 to the base of the transistor 110 increases, as a result, the voltage at the emitter of the transistor 123 is led to rise.
  • the base voltage of the transistor 126 also increases with the function of the resistance element R 4 and the transistor 126 is accordingly activated. As a result, current flows in the transistor 126 and excessive increase in the emitter voltage of the transistor 123 is avoided.
  • the resistance element R 4 and the capacitor C 4 function as a low-pass filter circuit having the frequency characteristic of attenuating the frequency component of the fundamental wave of the RF signal RFin inputted to the transistor 110 and passing the frequency component of the modulated wave. Specifically, when the frequency component of the fundamental wave of the RF signal RFin is transmitted to the collector of the transistor 126 , the resistance element R 4 and the capacitor C 4 function as a filter circuit that attenuates the radio frequency component, and thus, changes in the base voltage of the transistor 126 is prevented. Accordingly, the bias circuit 120 B can supply a stable bias signal to the transistor 110 .
  • the base voltage of the transistor 122 also rises with the function of the resistance element R 4 .
  • increased current flows in the transistor 122 and the voltage at the collector of the transistor 121 decreases.
  • the base voltage of the transistor 123 coupled to the collector of the transistor 121 falls and the current flowing in the transistor 123 decreases. Also by such negative feedback, excessive increase in the emitter voltage of the transistor 123 is avoided.
  • the power amplifier circuit 100 D can stably supply the bias voltage Vb of the transistor 110 due to negative feedback that suppresses excessive increase in the emitter voltage of the transistor 123 .
  • the bias circuit 120 B may not necessarily include the resistance element R 5 . Moreover, for example, similarly to the bias circuit 120 A illustrated in FIG. 7 , the bias circuit 120 B may include the transistors 124 and 125 configured by using MOSFETs.
  • the power amplifier circuits 100 , and 100 A to 100 D include the amplifier transistor configured to amplify an input signal, the resistance element coupled in series with the base of the amplifier transistor, the bias transistor configured to supply a bias current from the emitter or the source of the bias transistor to the base of the amplifier transistor through the resistance element, and the feedback circuit configured to change a base or gate voltage of the bias transistor to follow a change in the bias current supplied to the base of the amplifier transistor.
  • the output power of the input signal increases and the average bias current of the amplifier transistor increases, the base or gate voltage of the bias transistor rises, and as a result, the bias voltage supplied to the base of the amplifier transistor rises. Accordingly, it is possible to hinder linearity deterioration due to increase in output power of input signal.
  • the feedback circuit includes the control path to which a reference current or a reference voltage is supplied, the replica transistor configured to amplify the first current proportional to the bias current and output the second current from an output terminal of the replica transistor, the current mirror circuit configured to generate the third current proportional to and less than the second current and supply the third current to the control path, and the filter circuit provided on a path starting from the output terminal of the replica transistor and leading to the base or the gate of the bias transistor via the current mirror circuit and the control path and configured to attenuate a signal of the frequency component of the fundamental wave of the input signal and a signal of the frequency component of the modulated wave of the input signal.
  • the base or gate voltage of the bias transistor is controlled in accordance with the current flowing in the control path.
  • the reference current or the reference voltage, and the third current proportional to the bias current of the amplifier transistor are supplied to the control path, and as a result, it is possible to control the base or gate voltage of the bias transistor to follow the bias current of the amplifier transistor.
  • the power amplifier circuits 100 , and 100 A to 100 D include the filter circuit, it is possible to attenuate the radio frequency component included in the third current outputted by the current mirror circuit.
  • the feedback circuit further includes the offset circuit configured to eject the predetermined fourth current from the control path.
  • the predetermined fourth current ejected by the offset circuit is substantially equal in amount to the third current that is supplied from the current mirror circuit to the control path in the state in which the input signal is not transmitted to the amplifier transistor.
  • the current mirror circuit includes the first transistor and the second transistor coupled to each other at their base or gate.
  • the filter circuit is provided between the base or the gate of the first transistor and the base or the gate of the second transistor. With this configuration, it is possible to decrease the capacitance value of the capacitor included in the filter circuit.
  • the current mirror circuit further includes the first transistor and the second transistor coupled to each other at their base or gate and the third transistor and the fourth transistor cascoded respectively with the first transistor and the second transistor.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)
US16/913,585 2019-06-27 2020-06-26 Power amplifier circuit Active 2040-10-22 US11855587B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019-119379 2019-06-27
JP2019119379A JP2021005818A (ja) 2019-06-27 2019-06-27 電力増幅回路

Publications (2)

Publication Number Publication Date
US20200412304A1 US20200412304A1 (en) 2020-12-31
US11855587B2 true US11855587B2 (en) 2023-12-26

Family

ID=73887485

Family Applications (1)

Application Number Title Priority Date Filing Date
US16/913,585 Active 2040-10-22 US11855587B2 (en) 2019-06-27 2020-06-26 Power amplifier circuit

Country Status (3)

Country Link
US (1) US11855587B2 (ja)
JP (1) JP2021005818A (ja)
CN (1) CN112152570B (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112753164B (zh) * 2018-10-17 2024-03-08 株式会社村田制作所 功率放大电路
CN116260400A (zh) * 2022-12-31 2023-06-13 广州慧智微电子股份有限公司 偏置电路、功率放大器及电子设备

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030146790A1 (en) * 2001-06-06 2003-08-07 Arell Thomas W. Multi-mode amplifier bias circuit
US7400202B2 (en) * 2005-11-08 2008-07-15 Mitsubishi Electric Corporation Bias circuit for power amplifier operated by a low external reference voltage
US7522001B2 (en) * 2007-08-23 2009-04-21 Mitsubishi Electric Corporation Power amplifier
CN206775475U (zh) 2016-07-01 2017-12-19 株式会社村田制作所 偏置电路
US20180167035A1 (en) 2016-12-09 2018-06-14 Murata Manufacturing Co., Ltd Bias circuit
JP2018098766A (ja) 2016-12-09 2018-06-21 株式会社村田製作所 バイアス回路
US10931239B2 (en) * 2018-08-17 2021-02-23 Richwave Technology Corp. Amplification circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009017494A (ja) * 2007-07-09 2009-01-22 Renesas Technology Corp バイアス回路、電力増幅回路、受信機、送信機及び送受信機
JP2018033028A (ja) * 2016-08-25 2018-03-01 株式会社村田製作所 電力増幅回路

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030146790A1 (en) * 2001-06-06 2003-08-07 Arell Thomas W. Multi-mode amplifier bias circuit
US7400202B2 (en) * 2005-11-08 2008-07-15 Mitsubishi Electric Corporation Bias circuit for power amplifier operated by a low external reference voltage
US7522001B2 (en) * 2007-08-23 2009-04-21 Mitsubishi Electric Corporation Power amplifier
CN206775475U (zh) 2016-07-01 2017-12-19 株式会社村田制作所 偏置电路
US20180006608A1 (en) 2016-07-01 2018-01-04 Murata Manufacturing Co., Ltd. Bias circuit
US20180167035A1 (en) 2016-12-09 2018-06-14 Murata Manufacturing Co., Ltd Bias circuit
JP2018098766A (ja) 2016-12-09 2018-06-21 株式会社村田製作所 バイアス回路
US10931239B2 (en) * 2018-08-17 2021-02-23 Richwave Technology Corp. Amplification circuit

Also Published As

Publication number Publication date
US20200412304A1 (en) 2020-12-31
CN112152570A (zh) 2020-12-29
CN112152570B (zh) 2024-05-28
JP2021005818A (ja) 2021-01-14

Similar Documents

Publication Publication Date Title
US11569786B2 (en) Power amplifier circuit
US9461594B2 (en) Power amplifier module
US10491168B2 (en) Power amplification circuit
US10256778B2 (en) Power amplifier module
US10355653B2 (en) Power amplifier circuit
US10476454B2 (en) Power amplifier module
US11387796B2 (en) Power amplifier circuit
US20180006608A1 (en) Bias circuit
US11290060B2 (en) Bias circuit
US10910999B2 (en) Bias circuit
US11855587B2 (en) Power amplifier circuit
US11444582B2 (en) Power amplifier circuit
US20210305951A1 (en) Power amplifier circuit
CN214380828U (zh) 功率放大系统
CN112214061B (zh) 偏置电路
US11705874B2 (en) Power amplifier circuit
US20220263477A1 (en) Power amplifier circuit
KR102029558B1 (ko) 광대역 선형화가 개선된 파워 증폭 장치

Legal Events

Date Code Title Description
AS Assignment

Owner name: MURATA MANUFACTURING CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SOGA, TAKASHI;REEL/FRAME:053058/0047

Effective date: 20200624

FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STCV Information on status: appeal procedure

Free format text: NOTICE OF APPEAL FILED

STCV Information on status: appeal procedure

Free format text: APPEAL BRIEF (OR SUPPLEMENTAL BRIEF) ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

FEPP Fee payment procedure

Free format text: PETITION RELATED TO MAINTENANCE FEES GRANTED (ORIGINAL EVENT CODE: PTGR); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

Free format text: AWAITING TC RESP., ISSUE FEE NOT PAID

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE