US11816049B2 - Interrupt request signal conversion system and method, and computing device - Google Patents

Interrupt request signal conversion system and method, and computing device Download PDF

Info

Publication number
US11816049B2
US11816049B2 US17/575,543 US202217575543A US11816049B2 US 11816049 B2 US11816049 B2 US 11816049B2 US 202217575543 A US202217575543 A US 202217575543A US 11816049 B2 US11816049 B2 US 11816049B2
Authority
US
United States
Prior art keywords
interrupt request
request signal
interrupt
peripheral
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US17/575,543
Other languages
English (en)
Other versions
US20220229794A1 (en
Inventor
Lizheng FAN
Cai Chen
Fudong Liu
Xiaofan Zhao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Phytium Technology Co Ltd
Original Assignee
Phytium Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phytium Technology Co Ltd filed Critical Phytium Technology Co Ltd
Assigned to PHYTIUM TECHNOLOGY CO., LTD. reassignment PHYTIUM TECHNOLOGY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, Cai, FAN, Lizheng, LIU, FUDONG, ZHAO, Xiaofan
Publication of US20220229794A1 publication Critical patent/US20220229794A1/en
Application granted granted Critical
Publication of US11816049B2 publication Critical patent/US11816049B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/24—Interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/24—Interrupt
    • G06F2213/2406—Generation of an interrupt or a group of interrupts after a fixed or calculated time elapses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the technical field of interrupt technology and, more specifically, to an interrupt request signal conversion system and method, and a computing device.
  • Computer interruption refers to that: when an abnormal situation or special request that occurs in the system while the computer is executing a program, the computer temporarily interrupts the program currently being executed and handles the abnormal situation or special request, and returns to the original interruption point to continue to execute the program after the abnormal situation or special request is handled.
  • peripheral devices e.g., PO devices
  • the central processing unit CPU
  • the CPU will continue to execute the current program until the peripheral devices are ready and sends an interrupt request to the CPU, at which time the CPU temporarily interrupts the current program and switches to the peripheral device service program.
  • an interrupt request signal conversion system including an interrupt request signal converter configured to generate one or more converted interrupt request signals based on one or more signals received from one or more peripheral devices, and a signal output terminal configured to send the one or more converted interrupt request signals to an interface module of a processor during operation.
  • Each of the one or more converted interrupt request signals includes a plurality of interrupt identification bits each used to identify, based on a first level and a second level different from the first level, whether a signal received from a corresponding one of the one or more peripheral devices within a predetermined time range includes a peripheral interrupt request signal.
  • a computing device including a processor and an interrupt request signal conversion system.
  • the processor includes an interface module and an interrupt controller.
  • the interrupt request signal conversion system includes an interrupt request signal converter configured to generate one or more converted interrupt request signals based on one or more signals received from one or more peripheral devices, and a signal output terminal configured to send the one or more converted interrupt request signals to the interface module of the processor during operation.
  • Each of the one or more converted interrupt request signals includes a plurality of interrupt identification bits each used to identify, based on a first level and a second level different from the first level, whether a signal received from a corresponding one of the one or more peripheral devices within a predetermined time range includes a peripheral interrupt request signal.
  • the interface module includes an interface controller configured to report an interrupt request of the peripheral device requesting interrupt to the interrupt controller based on the one or more converted interrupt request signals.
  • an interrupt request signal conversion method including generating one or more converted interrupt request signals based on one or more signals received from one or more peripheral devices, and sending the one or more converted interrupt request signals to an interface module of a processor during operation.
  • Each of the converted interrupt request signals includes a plurality of interrupt identification bits, each of the one or more converted interrupt request signals including a plurality of interrupt identification bits each used to identify, based on a first level and a second level different from the first level, whether a signal received from a corresponding one of the one or more peripheral devices within a predetermined time range includes a peripheral interrupt request signal.
  • FIG. 1 is a schematic block diagram of an interface module of a processor.
  • FIG. 2 A and FIG. 2 B are schematic diagrams showing interrupt request signals that are identifiable by an interface controller shown in FIG. 1 .
  • FIG. 2 C is a schematic diagram showing an interrupt request signal that is not identifiable by the interface controller shown in FIG. 1 .
  • FIG. 3 is a schematic block diagram of an interrupt request signal conversion system according to an embodiment of the present disclosure.
  • FIG. 4 A and FIG. 4 B are schematic block diagrams showing a first example and a second example of the interrupt request signal conversion system shown in FIG. 3 .
  • FIG. 5 A and FIG. 5 B are schematic diagrams showing an application example of the interrupt request signal conversion system shown in FIG. 3 .
  • FIG. 6 A and FIG. 6 B are schematic diagrams showing converted interrupt request signals generated by interrupt request signal converters shown in FIG. 4 A and FIG. 4 B , respectively.
  • FIG. 7 is a schematic block diagram showing a first implementation of the first example of the interrupt request signal conversion system shown in FIG. 4 A .
  • FIG. 8 is a schematic block diagram of a sub-converter of an interrupt request signal converter shown in FIG. 7 .
  • FIG. 9 is a schematic diagram showing an interrupt reference level signal, a peripheral interrupt request signal, a first intermediate signal, and the converted interrupt request signal involved in the interrupt request signal conversion system shown in FIG. 7 .
  • FIG. 10 is a schematic block diagram showing a second implementation of the first example of the interrupt request signal conversion system shown in FIG. 4 A .
  • FIG. 11 is a schematic diagram showing the interrupt reference level signal, the peripheral interrupt request signal, and the converted interrupt request signal involved in the interrupt request signal conversion system shown in FIG. 10 .
  • FIG. 12 is a schematic block diagram showing a second example of the interrupt request signal conversion system shown in FIG. 4 A .
  • FIG. 13 and FIG. 14 are first and second schematic diagrams showing the interrupt reference level signal, the peripheral interrupt request signal, and the converted interrupt request signal involved in the interrupt request signal conversion system shown in FIG. 12 , respectively.
  • FIG. 15 is a schematic block diagram showing an example of the interrupt request signal conversion system shown in FIG. 4 B .
  • FIG. 16 to FIG. 18 are first to third schematic diagrams of the peripheral interrupt request signal and the converted interrupt request signal involved in the interrupt request signal conversion system shown in FIG. 15 .
  • FIG. 19 is a schematic block diagram of a computing device according to an embodiment of the present disclosure.
  • FIG. 20 is a flowchart of an interrupt request signal conversion method according to an embodiment of the present disclosure.
  • a processor may include an interface module and an interrupt controller.
  • the interface module may be configured to receive a peripheral interrupt request signal sent by a peripheral device, and report the interrupt request of the peripheral device to the interrupt controller based on the received peripheral interrupt request signal.
  • the interrupt request signal sent by some peripheral devices may not match the interface module of the processor, which makes the processor unable to respond to the interrupt request sent by some peripheral devices, and therefore restricts the types of peripheral devices suitable for the interface module. An example is provided below in conjunction with FIG. 1 and FIGS. 2 A- 2 C .
  • FIG. 1 is a schematic block diagram of an interface module 500 of a processor. As shown in FIG. 1 , the interface module 500 includes an interface controller 510 , a first interface 531 , a second interface 532 , and a third interface 533 .
  • the first interface 531 of the interface module 500 is coupled to a plurality of peripheral devices (De_ 1 -De_n) via a first bus B 1
  • the second interface 532 of the interface module 500 is coupled to a processor core via a second bus B 2
  • the processor core may be configured to access a target peripheral device that requests access via the second interface 532 , the interface controller 510 , and the first interface 531 based on an address occupied by the target peripheral device.
  • the third interface 533 of the interface module 500 may be configured to receive a peripheral interrupt request signal sent by a peripheral device.
  • the peripheral interrupt request signal DeIRQ[n:1] received by the third interface 533 may include a peripheral interrupt request signal DeIRQ[ 1 ] sent by a first peripheral device De_ 1 , a peripheral interrupt request signal DeIRQ[ 2 ] sent by a second peripheral device De_ 2 , . . . , and a peripheral interrupt request signal DeIRQ[n] sent by the nth peripheral device De_n.
  • the interface controller 510 includes an interrupter 511 .
  • the interrupter 511 may be configured to receive a peripheral interrupt request signal via the third interface 533 .
  • the interrupter 511 may be configured to determine the peripheral device requesting an interrupt based on the received peripheral interrupt request signal, and report the interrupt request of the peripheral device requesting the interrupt to the interrupt controller of the processor via the second bus B 2 .
  • the peripheral interrupt request signal that can be identified by the interface controller 510 may satisfy predetermined requirements, which will be described below in conjunction with FIG. 2 A and FIG. 2 B .
  • FIG. 2 A and FIG. 2 B show the peripheral interrupt request signal DeIRQ[ 1 ] sent by the first peripheral device De_ 1 and the peripheral interrupt request signal DeIRQ[ 2 ] sent by the second peripheral device De_ 2 shown in FIG. 1 , respectively.
  • FIG. 2 A and FIG. 2 B also show a clock signal CLK of the interface module 500 .
  • the interface controller 510 may identify the peripheral interrupt request signals shown in FIG. 2 A and FIG. 2 B .
  • the peripheral interrupt request signal DeIRQ[ 1 ] and the peripheral interrupt request signal DeIRQ[ 2 ] each include a start frame STA_F, an end frame STO_F, and a data frame D_F between the start frame STA_F and the end frame STO_F.
  • the data frame D_F includes a plurality of interrupt identification bits (e.g., the interrupt identification bit MS 1 to the interrupt identification bit MSn, which are later denoted as MS 1 -MSn, FIG. 2 A and FIG. 2 B only show the first three interrupt identification bits).
  • the plurality of interrupt identification bits MS 1 -MSn may respectively correspond to the plurality of peripheral devices coupled to the first bus B 1 (e.g., peripheral devices De_ 1 to peripheral device De_n).
  • the j-th interrupt identification bit MSj of the plurality of interrupt identification bits MS 1 -MSn may use a first level to identify the j-th peripheral device De_j corresponding to the j-th interrupt identification bit MSj has sent by an interrupt request within a predetermined time range.
  • the j-th interrupt identification bit may use a second level different from the first level to identify that the j-th peripheral device De_j has not sent the interrupt request within the predetermined time range, where j may be a positive integer less than or equal to the number of interrupt identification bits MS 1 -MSn.
  • the first level e.g., a low level
  • a second level e.g., a high level
  • the interrupter 511 may determine the serial number of the interrupt identification bit of the first level in the peripheral interrupt request signal and the peripheral device that requests the interrupt identified by the interrupt identification bit of the first level based on the number of clock cycles between the interrupt identification bit of the first level and the start frame STA_F, and report the interrupt request of the peripheral device requesting the interrupt to the interrupt controller of the processor via the second bus B 2 after receiving the end frame STO_F of the peripheral interrupt request signal.
  • FIG. 2 C is a schematic diagram showing an interrupt request signal DEIRQ 2 that is not identified by the interface controller 510 shown in FIG. 1 .
  • the peripheral interrupt request signal DeIRQ 2 in FIG. 2 C may use the first level to indicate that the peripheral device that sent the peripheral interrupt request signal requests an interrupt.
  • the level of the signal output by the peripheral device may be the second level.
  • the interface controller 510 shown in FIG. 1 cannot determine which device sent the peripheral interrupt request signal DeIRQ 2 in FIG. 2 C
  • the interface controller 510 shown in FIG. 1 cannot report the interrupt request of the peripheral device that sent the peripheral interrupt request signal in FIG. 2 C to the interrupt controller of the processor.
  • the types of the peripheral device applicable to the interface module 500 shown in FIG. 1 are limited.
  • the interface controller 510 may have a slower processing speed for the peripheral interrupt request signals sent by the plurality of peripheral devices (e.g., peripheral device De_ 1 to peripheral device De_n). This is because the peripheral interrupt request signals occupy a large number of clock cycles, and the interface controller 510 needs to report the interrupt requests related to the peripheral interrupt request signals after the clock cycles occupied by the peripheral interrupt request signals end.
  • the present disclosure provides an interrupt request signal conversion system and method, and a computing device.
  • the interrupt request signal conversion system may include an interrupt request signal converter and a signal output terminal.
  • the interrupt request signal converter may be configured to generate at least one converted interrupt request signal (e.g., a serial interrupt request signal) based on a signal received from at least one peripheral device.
  • the signal output terminal may be configured to provide at least one converted interrupt request signal to the interface module of the processor during operation.
  • Each converted interrupt request signal may include a plurality of interrupt identification bits. Each interrupt identification bit of the plurality of interrupt identification bits may determine whether the signal received from the peripheral device corresponding to each interrupt identification bit includes a peripheral interrupt request signal within a predetermined time range.
  • the interrupt request signal conversion system may be coupled to an interface module of the processor, and generate at least one converted interrupt request signal that can be identified by the interface module based on a signal received from at least one peripheral device.
  • the types of peripheral devices suitable for the interface module of the processor can be expanded.
  • the interrupt request signal conversion system may convert an interrupt message that does not meet the requirements of the interface module of the processor into an interrupt message that meets the requirements of the interface module of the processor, thereby expanding the types of peripheral devices suitable for the interface module of the processor.
  • the interrupt request signal conversion system may combine interrupt messages of different peripheral devices by forming a converted interrupt request signal with a plurality of interrupt identification bits (i.e., the interrupt identification bits of the first level). In this way, the processing speed of the interrupt request of the peripheral device of the interface module of the processor that receives the converted interrupt request signal can be increased. For example, by combining interrupt messages of different peripheral devices, the upper limit of the number of interrupt messages sent by the peripheral device that can be carried by the interface module per unit time can also be increased.
  • the interrupt request signal conversion system may include a plurality of interrupt request signal input terminals, and the types of peripheral interrupt request signals received by the plurality of interrupt request signal input terminals may be more than one. Therefore, the interrupt request signal conversion system can send the peripheral interrupt request signal to the interface module of the processor after combining the interrupt requests of different types of peripheral devices that send different types of peripheral interrupt request signals into the same converted interrupt request signal. In this way, the usability of the interface module of the processor can be improved while increasing the processing speed of the interface module to the interrupt request of the peripheral device.
  • the interrupt request signal conversion system may be implemented as hardware such as a complex programmable logic device (CPLD) and a filed programmable gate array (FPGA).
  • CPLD complex programmable logic device
  • FPGA filed programmable gate array
  • FIG. 3 is a schematic block diagram of an interrupt request signal conversion system 10 according to an embodiment of the present disclosure.
  • FIG. 4 A and FIG. 4 B are a first example (e.g., an example of operating in a continuous mode) and a second example (e.g., an example of operating in a non-continuous mode or a static mode) of the interrupt request signal conversion system 10 shown in FIG. 3 .
  • FIG. 4 A and FIG. 4 B also show the peripheral devices (e.g., De_ 1 to De_n), the interface module 500 of the processor, and a clock generator 500 coupled to the interrupt request signal conversion system 10 .
  • the peripheral devices e.g., De_ 1 to De_n
  • the interrupt request signal conversion system 10 includes an interrupt request signal converter 100 and a signal output terminal OT.
  • the interrupt request signal converter 100 may be configured to generate at least one converted interrupt request signal SerIRQ based on a signal received from at least one peripheral device.
  • the signal output terminal OT may be configured to send at least one converted interrupt request signal SerIRQ to the interface module 500 of the processor during operation.
  • At least one interrupt request signal input terminal I_s is configured to receive a signal sent by at least one peripheral device during operation, and send the received signal to the interrupt request signal converter 100 .
  • the interrupt request signal conversion system 10 and the interface module 500 of the processor may support a plurality of peripheral devices (e.g., peripheral device De_ 1 to peripheral device De_n).
  • the interrupt request signal conversion system 10 may also include a plurality of interrupt request signal input terminals (e.g., I_s[ 1 ]-I_s[n]), and the plurality of interrupt request signal input terminals (e.g., I_s[ 1 ]-I_s[n]) may be configured to be respectively coupled to a plurality of (e.g., n) plurality of peripheral devices (e.g., peripheral device De_ 1 to peripheral device De_n).
  • the number of interrupt request signal input terminal I_s included in the interrupt request signal conversion system 10 may be equal to the number of processors coupled to the interrupt request signal conversion system 10 and the number of peripheral devices (e.g., n) that the interrupt request signal conversion system 10 can support.
  • the n peripheral devices may be selected from a mouse, a keyboard, a serial port, or other applicable peripheral devices.
  • the interrupt request signal conversion system 10 may also include a clock signal input terminal I_c.
  • the clock signal input terminal I_c may be configured to receive the clock signal CLK and send the clock CLK to the interrupt request signal converter 100 .
  • the clock signal CLK may include a plurality of clock cycles.
  • the clock signal input terminal I_c is configured to be coupled to the clock generator 550 .
  • the clock frequency of the interface module 500 may be 33 MHz.
  • FIG. 5 A and FIG. 5 B are schematic diagrams showing an application example of the interrupt request signal conversion system 10 shown in FIG. 3 .
  • FIG. 5 A and FIG. 5 B are schematic diagrams showing the processor and the components included in the interface module 500 of the processor.
  • the interface module 500 of the processor includes an interface controller 510 , a first interface 531 , a second interface 532 , and a third interface 533 .
  • the first interface 531 is coupled to a plurality of peripheral devices (De_ 1 -De_n) via the first bus B 1
  • the second interface 532 is coupled to the processor core with the second bus B 2 .
  • the processor core may access the target peripheral device via the second interface 532 , the interface controller 510 , and the first interface 531 based on the address occupied by the target peripheral device that is requesting access.
  • the third interface 533 may be coupled to the output terminal of the interrupt request signal conversion system 10 to receive the converted interrupt request signal SerIRQ from the interrupt request signal conversion system 10 .
  • the interface controller 510 includes an interrupter 511 .
  • the interrupter 511 may be configured to receive the converted interrupt request signal SerIRQ via the third interface 533 , and determine the peripheral device requesting the interrupt based on the converted interrupt request signal SerIRQ.
  • the interrupt request of the peripheral device requesting the interrupt may be reported to the interrupt controller of the processor via the second bus B 2 .
  • FIG. 6 A and FIG. 6 B are schematic diagrams showing the converted interrupt request signals SerIRQ generated by the interrupt request signal converter 100 shown in FIG. 4 A and FIG. 4 B , respectively.
  • FIG. 6 A and FIG. 6 B also show the clock signal CLK received by the interrupt request signal conversion system 10 .
  • each converted interrupt request signal SerIRQ includes a plurality of interrupt identification bits MS 1 -MSn.
  • Each interrupt identification bit may be used to determine whether the signal received from the peripheral device corresponding to each interrupt identification bit includes a peripheral interrupt request signal within a predetermined time range based on the first level and the second level that is different from the first level.
  • FIG. 6 A and FIG. 6 B only show the first to the third interrupt identification bits MS 1 -MS 3 of the plurality of interrupt identification bits MS 1 -MSn of the converted interrupt request signal SerIRQ.
  • the predetermined time range will be described later in conjunction with specific examples, which will be omitted here.
  • the first level (e.g., a low level) may be lower than a second level (e.g., a high level).
  • a low level and a high level are used to respectively represent the first level and the second level, but the embodiments of the present disclosure are not limited thereto, and a high level and a low level may also be used to represent the first level and the second level, respectively.
  • the plurality of interrupt identification bits MS 1 -MSn may respectively correspond to a plurality of peripheral devices (e.g., peripheral device De_ 1 -peripheral device De_n) that can be coupled to the interface module 500 and the interrupt request signal conversion system 10 .
  • the plurality of interrupt identification bits MS 1 -MSn may correspond to the plurality of peripheral devices that can be coupled to the interface module 500 and the interrupt request signal conversion system 10 in a one-to-one correspondence.
  • the j-th interrupt identification bit MSj of the plurality of interrupt identification bits MS 1 -MSn may use a first level to identify the j-th peripheral device De_j corresponding to the j-th interrupt identification bit MSj has sent by an interrupt request within a predetermined time range.
  • the signal received from the peripheral device corresponding to the j-th interrupt identification bit MSj within the predetermined time range may include the peripheral interrupt request signal.
  • the j-th interrupt identification bit MSj may use the second level to identify that the j-th peripheral device De_j did not send an interrupt request within the predetermined time range.
  • the signal received from the peripheral device corresponding to the j-th interrupt identification bit MSj may not include the peripheral interrupt request signal.
  • j may be a positive integer that is less than or equal to the number of the plurality of interrupt identification bits MS 1 -MSn.
  • the interrupt identification bit that is the first level may also be referred to as the interrupt request identifier.
  • the plurality of interrupt identification bits MS 1 -MSn may correspond to a plurality of interrupt request signal input terminals I_s[ 1 ]-I_s[n].
  • Each interrupt identification bit may use the first level and the second level to respectively identify that the signal received by the peripheral device coupled to the interrupt request signal input terminal I_s corresponding to each interrupt identification bit includes and not include the peripheral interrupt request signal in the predetermined time range.
  • the interrupt request signal converter 100 may be further configured to, in response to the signals received from the plurality of peripheral devices (e.g., peripheral device De_ 1 -peripheral device De_n) including N peripheral interrupt request signals, cause at least one converted interrupt request signal SerIRQ to include N interrupt request identifiers (SQ 1 , SQ 2 , . . . , SQN) respectively corresponding to N peripheral interrupt request signals.
  • N interrupt request identifiers (SQ 1 , SQ 2 , . . . , SQN) may be N interrupt identification bits of the first level, and N may be a positive integer.
  • the number of interrupt request identifiers included in the at least one converted interrupt request signal SerIRQ may be greater than 1, such that fewer interrupt request signals SerIRQ can be used to transmit the interrupt requests sent by the plurality of peripheral devices (e.g., peripheral device De_ 1 -peripheral device De_n).
  • the processing speed of the interface module of the processor receiving the converted interrupt request signal SerIRQ to the interrupt request of the peripheral device can be increased, and the upper limit of the number of interrupt request signals sent by the peripheral device that the interface module can process per unit time can also be increased.
  • the N interrupt request identifiers SQ 1 , SQ 2 , . . .
  • SQN SQN
  • N may be greater than 1, thereby further increasing the processing speed of the interface module of the processor receiving the converted interrupt request signal SerIRQ to the interrupt request of the peripheral device, and the upper limit of the number of interrupt request signals sent by the peripheral device that the interface module can process in a time unit.
  • the signals received from the plurality of peripheral devices may include two peripheral interrupt request signals.
  • the converted interrupt request signal SerIRQ includes two interrupt request identifiers respectively corresponding to the two peripheral interrupt request signals.
  • the levels of the first and second interrupt identification bits MS 1 and MS 2 of the converted interrupt request signal SerIRQ shown in FIG. 6 A and FIG. 6 B are the first level, and the level of the third interrupt identification bit MS 3 is the second level.
  • the converted interrupt request signal SerIRQ output by the output terminal OT of the interrupt request signal conversion system 10 shown in FIG. 4 B includes a start frame STA_F 2 (e.g., a start identification frame), a data frame D_F, and an end frame STO_F 2 (e.g., an end identification frame).
  • the start frame STA_F 2 is positioned before the end frame STO_F 2
  • the data frame D_F is positioned between the start frame STA_F 2 and the end frame STO_F 2 .
  • the data frame D_F includes the plurality of interrupt identification bits MS 1 -MSn described above.
  • the interface controller 510 of the interface module 500 of the processor may determine the interrupt requesting peripheral device identified by the interrupt identification bit (the interrupt identification bit of the first level) based on the number of clock cycles between the interrupt identification bit (the interrupt identification bit of the first level) in each converted interrupt request signal SerIRQ and the start frame STA_F 2 .
  • the level corresponding to the start frame STA_F 2 and the end frame STO_F 2 is the first level.
  • the level of the converted interrupt request signal SerIRQ other than the start frame STA_F 2 , the end frame STO_F 2 , and the interrupt request identifier corresponds to the second level.
  • the start frame STA_F 2 occupies the corresponding x_start clock cycles, and the end frame STO_F 2 occupies a corresponding x_stop clock cycles.
  • Each interrupt identification bit occupies a corresponding clock cycle, and the data frame D_F occupies a corresponding x_data clock cycle.
  • Each converted interrupt request signal SerIRQ occupies a corresponding x_IRQ clock cycle.
  • the number of clock cycles x_data occupied by each data frame D_F, the number of clock cycles between the clock cycle occupied by the interrupt identification bit corresponding to each peripheral device and the start frame STA_F 2 may be set based on the relevant protocol of the target interface module of the interrupt request signal conversion system 10 that can be coupled to the interrupt request signal conversion system 10 and the interface module 500 .
  • the interval between two adjacent first interrupt identifiers may be x_num clock cycles.
  • the number of clock cycles between the interrupt identification bit corresponding to the t-th peripheral device and the start frame STA_F 2 may be equal to t*3 ⁇ 1.
  • n may also be equal to 10, 29, 30 or other suitable numbers.
  • x_start may also be 8 or other suitable numbers
  • x_stop may also be 2 or other suitable numbers
  • x_num may also be 4 or other suitable numbers.
  • the interrupt request signal converter 100 also includes an interrupt reference level signal input terminal I_B.
  • the interrupt request signal converter 100 may be further configured to receive at least one interrupt reference level signal respectively corresponding to at least one converted interrupt request signal SerIRQ from the interface module 500 d via the interrupt reference level signal input terminal I_B, and using the at least one interrupt reference level signal Ser_BASE start frame STA_F and end frame STO_F 2 to determine the start time and end time of the at least one converted interrupt request signal SerIRQ.
  • FIG. 6 A also shows a schematic diagram of the interrupt reference level signal Ser_BASE received by the interrupt request signal conversion system 10 shown in FIG. 4 A .
  • the interrupt reference level signal Ser_BASE includes a start frame STA_F, an end frame STO_F, and a blank frame B_F positioned between the start frame STA_F and the end frame STO_F.
  • the level corresponding to the blank frame B_F may be the second level.
  • the interrupt reference level signal Ser_BASE may also include an interval frame I_F (see FIG. 9 ) positioned after the end frame STO_F, and the level of the interval frame I_F may be the second level.
  • the start time of each converted interrupt request signal SerIRQ is the end time of the start frame STA_F of the corresponding interrupt reference level signal Ser_BASE (that is, the start time of the blank frame B_F).
  • the converted interrupt request signal may be generated after detecting the start frame STA_F of the corresponding interrupt reference level signal Ser_BASE.
  • the end time of each converted interrupt request signal SerIRQ is the start time of the end frame STO_F of the corresponding interrupt reference level signal Ser_BASE (that is, the end time of the blank frame B_F).
  • the number of clock cycles occupied by the blank frame B_F of the interrupt reference level signal Ser_BASE is equal to the number of clock cycles occupied by the converted interrupt request signal SerIRQ.
  • the interrupt request signal of the converted interrupt request signal SerIRQ does not include the start frame and the end frame.
  • the interface controller 510 of the interface module 500 of the processor may determine the start time and end time of the converted interrupt request signal SerIRQ based on the start frame STA_F and the end frame STO_F of the interrupt reference level signal Ser_BASE sent by the interface module 500 .
  • the peripheral device that requests the interrupt identified by the interrupt identification bit of the first level may be determined based on the number of clock cycles between the interrupt identification bit of the first level in the converted interrupt request signal SerIRQ and the start frame STA_F of the interrupt reference level signal Ser_BASE.
  • the characteristics of the converted interrupt request signal SerIRQ shown in FIG. 6 A may be the same as or similar to the characteristics of the data frame D_F of the converted interrupt request signal SerIRQ shown in FIG. 6 B .
  • the characteristics of the start frame STA_F and the end frame STO_F of the interrupt reference level signal Ser_BASE shown in FIG. 6 A may be the same as or similar to the characteristic of the start frame STA_F 2 and the end frame STO_F 2 of the converted interrupt request signal SerIRQ shown in FIG. 6 B . Therefore, for more information about the converted interrupt request signal SerIRQ and the interrupt reference level signal Ser_BASE shown in FIG. 6 A , reference can be made to the description of the data frame D_F of the converted interrupt request signal SerIRQ shown in FIG. 6 B , which will not be repeated here.
  • the interrupt request signal converter 100 may be configured to detect the peripheral interrupt request signal (that is, to detect whether the signal received from the interrupt request signal input terminal includes the peripheral interrupt request signal).
  • the specific method for the interrupt request signal converter 100 to detect the peripheral interrupt request signal may be set based on the peripheral interrupt request signal sent by the target peripheral device of the interrupt request signal conversion system.
  • the peripheral interrupt request signal sent by the target peripheral device may be a signal that uses a single low level to represent the interrupt request, and the peripheral interrupt request signal sent by the target peripheral device may be detected by detecting the leading edge (e.g., the falling edge) of the peripheral interrupt request signal.
  • the target peripheral device By detecting the leading edge of the peripheral interrupt request signal to determine whether the target peripheral device sends the peripheral interrupt request signal, a more timely response to the interrupt request sent by the peripheral device may be achieved.
  • the single low level sent by the target peripheral device may be sampled multiple times to improve the accuracy of the detection result.
  • leading edge e.g., the falling edge
  • the leading edge of the received (e.g., detected) peripheral interrupt request signal may also be used as a sign of the received (e.g., detected) peripheral interrupt request signal.
  • the detection result of the peripheral interrupt request signal may be saved in a register. For example, if a falling edge is detected, the corresponding data bit in the register (e.g., a first data bit) may be set from 1 to 0. If a falling edge is detected, the corresponding data bit in the register (e.g., a second data bit) may be set from 0 to 1.
  • the peripheral interrupt request signal may be recorded when the interrupt request signal converter 100 includes the current conversion process. Further, when the interrupt request signal converter 100 is idle, the recorded peripheral interrupt request signal may be converted.
  • the counter of the interrupt request signal converter 100 may also keep counting during the process of generating a single converted interrupt request signal, and realize the related functions of the interrupt request signal converter 100 .
  • FIG. 4 A The first example of the interrupt request signal conversion system 10 shown in FIG. 4 A will be described below in conjunction with FIGS. 7 - 9 .
  • the interrupt request signal converter 100 may be configured to receive N peripheral interrupt request signals from a plurality of interrupt request signal input terminals within the clock cycle occupied by the same interrupt reference level signal Ser_BASE, and generate a single converted interrupt request signal SerIRQ (that is, the converted interrupt request signal SerIRQ corresponding to the first interrupt reference level signal Ser_BASE) within the clock cycle occupied by the blank frame B_F of the first interrupt reference level signal Ser_BASE received after the N peripheral interrupt request signals are received based on the N peripheral interrupt request signals.
  • N may be a positive integer.
  • the single converted interrupt request signal SerIRQ (that is, the converted interrupt request signal SerIRQ corresponding to the first interrupt reference level signal Ser_BASE) described above may include N interrupt request identifiers (e.g., SQ 1 , SQ 2 , . . . , SQN).
  • N interrupt request identifiers e.g., SQ 1 , SQ 2 , . . . , SQN.
  • N may be greater than 1.
  • the interrupt request signal conversion system 10 may increase the processing speed of the interrupt request of the peripheral device for the interface module of the processor receiving the converted interrupt request signal SerIRQ, and increase the upper limit of the number of interrupt request signals sent by the peripheral devices that the interface module can process in a unit time.
  • the predetermined time range may refer to the clock cycle occupied by the same interrupt reference level signal Ser_BASE (that is, the interrupt request signal SerIRQ before the previous conversion of the interrupt reference level signal Ser_BASE that overlaps the generated converted interrupt request signal SerIRQ in time).
  • the interrupt request signal converter 100 may be configured to receive N peripheral interrupt request signals from a plurality of interrupt request signal input terminals within the clock cycle occupied by the same interrupt reference level signal Ser_BASE; generate a plurality of first intermediate signals Inter[ 1 ]-Inter[n] within the clock cycle occupied by the blank frame B_F of the first interrupt reference level signal Ser_BASE received after the N peripheral interrupt request signals are received based on the N peripheral interrupt request signals; and perform a logical AND operation on the plurality of first intermediate signals Inter[ 1 ]-Inter[n] to generate a converted interrupt request signal SerIRQ (that is, a converted interrupt request signal SerIRQ that overlaps with the first interrupt reference level signal Ser_BASE in time) corresponding to the first interrupt reference level signal Ser_BASE.
  • a converted interrupt request signal SerIRQ that is, a converted interrupt request signal SerIRQ that overlaps with the first interrupt reference level signal Ser_BASE in time
  • the first intermediate signal output by each sub-converter may include a second interrupt identification bit (e.g., M 2 [ 1 ]-M 2 [ n ]) corresponding to the input terminal of the interrupt request signal coupled to the sub-converter.
  • the plurality of second interrupt identification bits included in the plurality of first intermediate signals Inter[ 1 ]-Inter[n] may not overlap in time, that is, they may occupy different clock cycles.
  • the signals received by the plurality of interrupt request signal input terminals I_s[ 1 ]-I_s[n] may include N peripheral interrupt request signals, and a single interrupt request signal SerIRQ (the converted interrupt request signal SerIRQ corresponding to the first interrupt reference level signal Ser_BASE) may include N interrupt request identifiers (SQ 1 , SQ 2 , . . . , SQN).
  • FIG. 7 is a schematic diagram showing the first implementation of the first example of the interrupt request signal conversion system 10 shown in FIG. 4 A .
  • the interrupt request signal converter 100 includes a plurality of sub-converters (e.g., sub-converter 110 [ 1 ]-sub-converter 110 [ n ]) and a logical AND operator.
  • FIG. 8 is a schematic diagram of the j-th sub-converter 110 [ j ] of the interrupt request signal converter 100 shown in FIG. 7 , where j may be a positive integer less than or equal to the number of the plurality of sub-converters (or the number of the plurality of interrupt identification bits).
  • FIG. 9 is a schematic diagram showing the interrupt reference level signal Ser_BASE, the peripheral interrupt request signal, the first intermediate signals Inter[ 1 ]-Inter[n], and the converted interrupt request signal SerIRQ involved in the interrupt request signal conversion system 10 shown in FIG. 7 .
  • each of the plurality of sub-converters includes a first input terminal In 1 , a second input terminal In 2 , a third input terminal In 3 , and a fourth input terminal In 4 .
  • the first input terminals In 1 of the plurality of sub-converters are configured to be respectively coupled to the plurality of interrupt request signal input terminals I_s[ 1 ]-I_s[n].
  • the first input terminals In 1 of the plurality of sub-converters correspond to, and are respectively coupled to, the plurality of interrupt request signal input terminals I_s[ 1 ]-I_s[n] in a one-to-one correspondence.
  • the interrupt request signal converter 100 may be configured to receive N (e.g., two) peripheral interrupt request signals from the plurality of interrupt request signal input terminals I_s[ 1 ]-I_s[n] in the clock cycle occupied by the same interrupt reference level signal Ser_BASE (e.g., the first interrupt reference level signal Ser_BASE in FIG. 9 ). That is, within the clock cycle occupied by the same interrupt reference level signal Ser_BASE, the signals received from the plurality of interrupt request signal input terminals I_s[ 1 ]-I_s[n] may include N peripheral interrupt request signals. As shown in FIG.
  • the signals received from the interrupt request signal input terminals I_s[ 1 ] and I_s[j] include the peripheral interrupt request signals DeIRQ[ 1 ] and DeIRQ[j], respectively. Further, the signals received from the plurality of interrupt request signal input terminals I_s[ 1 ]-I_s[n] other than the input terminals I_s[ 1 ] and I_s[j] do not include the peripheral interrupt request signal (that is, the corresponding levels are all second level).
  • the second input terminals In 2 of the plurality of sub-converters are configured to be coupled to the interrupt reference level signal input terminal I_B to receive the same interrupt reference level signal Ser_BASE.
  • the third input terminals In 3 of the plurality of sub-converters are configured to be coupled to the clock signal input terminal I_C to receive the same clock signal CLK.
  • the fourth input terminals In 4 of the plurality of sub-converters are configured to receive a reset signal RST to perform a reset operation on the sub-converters when required.
  • the plurality of sub-converters (e.g., sub-converter 110 W-sub-converter 110 [ n ]) are configured to respectively generate a plurality of first intermediate signals Inter[ 1 ]-Inter[n].
  • the level of the first intermediate signal Inter[ 1 ] output by the output terminal OUT[ 1 ] of the sub-converter 110 [ 1 ] coupled to the interrupt request signal input terminal I_s[ 1 ] and the level of the second interrupt identification bit of the first intermediate signal Inter[j] output by the output terminal OUT[j] of the sub-converter 110 [ j ] coupled to the interrupt request signal input terminal I_s[j] are the first level.
  • the level of the second interrupt identification bit of the first intermediate signal Inter[OTR] output by the output terminal OUT[OTR] of the plurality of sub-converters other than the sub-converters 1110 [ 1 ] and 110 [ j ] is the second level.
  • the logical AND operator is configured to generate a conversion corresponding to the first interrupt reference level signal Ser_BASE by performing a logical AND operation on a plurality of first intermediate signals Inter[ 1 ]-Inter[n].
  • the interrupt request identifiers formed by the plurality of (more than 1) peripheral interrupt requests triggered by the plurality of peripheral devices e.g., the interrupt request identifier SQ 1 triggered by the first peripheral interrupt request signal DeIRQ[ 1 ] and the interrupt request identifier SQk triggered by the k-th peripheral interrupt request signal DeIRQ[j]
  • the interrupt request identifier SQ 1 triggered by the first peripheral interrupt request signal DeIRQ[ 1 ] and the interrupt request identifier SQk triggered by the k-th peripheral interrupt request signal DeIRQ[j] within the clock cycle occupied by the same interrupt reference level signal Ser_Base can be combined into the same converted interrupt request signal SerIRQ.
  • the processing speed of the interface module of the processor receiving the converted interrupt request signal SerIRQ to the interrupt request of the peripheral device can be increased, and the upper limit of the number of interrupt request signals sent by the peripheral device that the interface module can process per unit time can also be increased.
  • the logical AND operator reference can be made to related technologies, which will not be provided here.
  • each of the plurality of sub-converter may be configured to detect whether the signal received by the first input terminal of the sub-converter (e.g., a signal received within a clock cycle occupied by a single interrupt reference level signal Ser_BASE) includes a peripheral interrupt request signal, and set the level of the second identification bit of the first intermediate signal (the first intermediate signal that overlaps with the first interrupt reference level signal after the single interrupt reference level signal described above) output by the sub-converter to the first level when the peripheral interrupt request signal is included in the received signal.
  • the types of peripheral interrupt request signals detected by the plurality of sub-converters may be the same or not completely the same.
  • the interrupt request signal converter 100 includes a plurality of sub-converters, the method for detecting the peripheral interrupt request signal adopted by each sub-converter can be matched with the peripheral interrupt request signal received by the interrupt request signal input terminal coupled to the sub-converter. In this way, the interrupt request signal conversion system 10 can be compatible with multiple types of peripheral devices, and allow the interrupt request signal converter 100 to combine the interrupt requests of different types of peripheral devices into the interrupt request signal conversion system of a single converted interrupt request signal.
  • the j-th sub-converter 110 [ j ] of the plurality of sub-converters is configured to generate the j-th first intermediate signal Inter[j] in the plurality of first intermediate signals Inter[ 1 ]-Inter[n] from the signal received by the j-th interrupt request signal input terminal I_s[j] in the plurality of interrupt request signal input terminal I_s[ 1 ]-I_s[n].
  • the plurality of sub-converters are configured to generate a plurality of first intermediate signals Inter[ 1 ]-Inter[n] in the clock cycle occupied by the blank frame B_F of the first interrupt reference level signal Ser_BASE received after receiving N peripheral interrupt request signals based on the N peripheral interrupt request signals.
  • the number of clock cycles occupied by the plurality of first intermediate signals Inter[ 1 ]-Inter[n] is equal to the number of clock cycles occupied by the blank frame B_F of the corresponding interrupt reference level signal Ser_BASE.
  • the start time of the plurality of first intermediate signals Inter[ 1 ]-Inter[n] is the start time (that is, the end time of the start frame STA_F) of the blank frame B_F of the corresponding interrupt reference level signal Ser_BASE.
  • the end time of the plurality of first intermediate signals Inter[ 1 ]-Inter[n] is the end time (that is, the start time of the end frame STO_F) of the blank frame B_F of the corresponding interrupt reference level signal Ser_BASE.
  • each of the first intermediate signal may include a second interrupt identification bit corresponding to the input terminal of the interrupt request signal coupled to the sub-converter that outputs each first intermediate signal.
  • the first intermediate signal Inter[ 1 ] output by the output terminal OUT[ 1 ] of the first sub-converter has a second interrupt identification bit M 2 [ 1 ]; . . .
  • the first intermediate signal Inter[j] output by the output terminal OUT[j] of the j-th sub-converter 110 [ j ] has a second interrupt identification bit M 2 [ j ]; . . .
  • the first intermediate signal Inter[n] output by the output terminal OUT[n] of the n-th sub-converter has a second interrupt identification bit M 2 [ n ] (not shown in the accompanying drawings).
  • the converted interrupt request signal SerIRQ corresponding to the first interrupt reference level signal Ser_BASE may include N (e.g., two) interrupt request identifiers (e.g., interrupt request identifier SQ 1 and interrupt request identifier SQk).
  • the j-th sub-converter 110 [ j ] may be configured to, in response to the signal received from the j-th interrupt request signal input terminal I_s[j] being the k-th peripheral interrupt request signal of the N peripheral interrupt request signals, causing the second interrupt identification bit M 2 [ j ] of the j-th first intermediate signal Inter[j] generated in the clock cycle occupied by the blank frame B_F of the first interrupt reference level signal Ser_BASE received after the k-th peripheral interrupt request signal DeIRQ[j] to be the first level, where k may be a positive integer less than or equal to N.
  • each of the plurality of sub-converters may also include a counter (e.g., a corresponding one of the counters 111 [ 1 ]- 111 [ n ]).
  • the j-th sub-converter 110 [ j ] of the plurality of sub-converters may be configured to cause the counter 111 [ j ] included in the j-th sub-converter 110 [ j ] to start counting in response to receiving the k-th peripheral interrupt request signal DeIRQ[j] in the N peripheral interrupt request signals from the j-th first intermediate signal I_s[j] in the plurality of interrupt request signal input terminals, and detecting the start time STA_F of the first interrupt reference level signal Ser_BASE; and, set the second interrupt identification bit of the first intermediate signal output by the j-th sub-converter 110 [ j ] to the first level when the value of the counter 111 [ j ] in the j-th sub-converter 110 [ j ] is equal to a device identification value that matches the peripheral device that sent the k-th peripheral interrupt request signal De
  • the second interrupt identification bit set to the first level included in the plurality of first intermediate signals may be used as the interrupt request identifier of the converted interrupt request signal through a logical AND operation.
  • the first intermediate signal output by the j-th sub-converter 110 [ j ] may include the second interrupt identification bit of the first level, which may be used as the interrupt request identifier SQk of the converted interrupt request signal through a logical AND operation.
  • the device identification value matching the j-th peripheral device may be equal to j*(x_num+1)+x_start, such as j*3+x_start.
  • the device identification value in other examples provided in the embodiments of the present disclosure can have the same or similar definition, which will not be repeated here.
  • FIG. 10 is a schematic diagram showing a second implementation of the first example of the interrupt request signal conversion system 10 shown in FIG. 4 A .
  • the interrupt request signal converter 100 includes a single counter 111 .
  • FIG. 11 is a schematic diagram showing the interrupt reference level signal Ser_BASE, the peripheral interrupt request signal, and the converted interrupt request signal SerIRQ involved in the interrupt request signal conversion system 10 shown in FIG. 10 .
  • the interrupt request signal converter 100 may be further configured to, in the clock cycle corresponding to the same interrupt reference level signal Ser_BASE, receive and record N peripheral interrupt request signals from a plurality of interrupt request signal input terminals I_s[i]-I_s[n]; detect the start time STA_F of the first interrupt reference level signal Ser_BASE received after the N peripheral interrupt request signals are received in response to receiving N peripheral interrupt request signals; cause the counter 111 to start counting in response to detecting the start frame STA_F of the first interrupt reference level signal Ser_BASE, and set the level of the corresponding part (e.g., the part where the interrupt identification bit corresponding to the N device identification values is positioned) of the interrupt request signal to the first level to form N interrupt request identifiers (e.g., SQ 1 , SQ 2 .
  • N interrupt request identifiers e.g., SQ 1 , SQ 2 .
  • the value of the counter 111 e.g., the value of the counter 111 in a single counting cycle
  • the device identification value e.g., N device identification values
  • the peripheral interrupt request signal DeIRQP (e.g., the leading edge of the peripheral interrupt request signal DeIRQP, from the P-th interrupt request signal input terminal I_s[P], where P may be a positive integer less than or equal to N) that triggers the counter 111 to start counting has been received, and the peripheral interrupt request signal DeIRQP triggers the interrupt request signal converter 100 to form an interrupt request identifier SQP in the clock cycle occupied by the blank frame B_F of the first interrupt reference level signal Ser_BASE after the interrupt reference level signal Ser_BASE corresponding to the peripheral interrupt request signal DeIRQP.
  • the interrupt request signal converter 100 may be configured to generate N interrupt request identifiers corresponding to N peripheral interrupt request signals within the clock cycle occupied by the blank frame B_F of the first interrupt reference level signal Ser_BASE received after receiving the N peripheral interrupt request signals.
  • FIG. 10 shows that the interrupt request signal conversion system 10 shown in FIG. 4 A can also increase the processing speed of the interrupt request of the peripheral device of the interface module of the processor receiving the converted interrupt request signal SerIRQ.
  • the interrupt request signal conversion system 10 shown in FIG. 10 has the same or similar functions to the interrupt request signal conversion system 10 shown in FIG. 7 . Therefore, for the functional details of the interrupt request signal conversion system 10 shown in FIG. 10 , reference can be made to the related description of the interrupt request signal conversion system 10 shown in FIG. 7 , which will not be repeated here.
  • FIG. 4 A The second example of the interrupt request signal conversion system 10 shown in FIG. 4 A will be described below in conjunction with FIGS. 12 - 14 .
  • FIG. 12 is a schematic diagram of the second example of the interrupt request signal conversion system 10 shown in FIG. 4 A .
  • the interrupt request signal converter 100 includes a counter 111 .
  • the interrupt request signal converter 100 shown in FIG. 12 may enable the interrupt request of the peripheral device to be sent to the interface module of the processor faster.
  • the predetermined time range may refer to the clock cycle occupied by the portion between the two interrupt identification bits corresponding to the k-th peripheral interrupt request signal that form two adjacent converted interrupt request signals SerIRQs.
  • the predetermined time range may refer to the time range between the formation of the two interrupt identification bits between after the previous interrupt identification bit and the next interrupt identification bit.
  • the interrupt request signal converter 100 may be configured to form the converted interrupt request signal SerIRQ corresponding to the k-th peripheral interrupt request signal DeIRQ[j] in the clock cycle occupied by the blank frame B_F of the currently received interrupt reference level signal Ser_BASE (that is, the interrupt reference level signal received when the k-th peripheral interrupt request signal DeIRQ[j] is received) in response to the counter 111 being in the counting state and the k-th device identification value being not missed when the k-th peripheral interrupt request signal DeIRQ[j] is received.
  • an interrupt request identifier corresponding to the k-th peripheral interrupt request signal DeIRQ[j] may be formed.
  • the converted interrupt request signal SerIRQ corresponding to the k-th peripheral interrupt request signal DeIRQ[j] may refer to the converted interrupt request signal SerIRQ including the interrupt request identifier triggered by the k-th peripheral interrupt request signal DeIRQ[j].
  • the converted interrupt request signal SerIRQ corresponding to the k-th peripheral interrupt request signal DeIRQ[j] in other embodiments has the same or similar definition, which will not be repeated herein.
  • FIG. 13 is a first schematic diagram showing the interrupt reference level signal Ser_BASE, the peripheral interrupt request signal, and the converted interrupt request signal SerIRQ involved in the interrupt request signal conversion system 10 shown in FIG. 12 .
  • the interrupt request signal converter 100 forms a converted interrupt request signal SerIRQ (that is, SerIRQ[ 1 ]) corresponding to the first peripheral interrupt request signal in the clock cycle occupied by the blank frame B_F of the currently received interrupt reference level signal Ser_BASE.
  • SerIRQ that is, SerIRQ[ 1 ]
  • an interrupt request identifier SQ 1 corresponding to the first peripheral interrupt request signal SerIRQ[ 1 ] may be formed.
  • the peripheral interrupt request signal DeIRQP (e.g., the leading edge of the peripheral interrupt request signal DeIRQP) triggers the interrupt request signal converter 100 to form the interrupt request identifier SQP in the clock cycle occupied by the blank frame B_F of the first interrupt reference level signal Ser_BASE (e.g., the interrupt reference level signal overlapping with the peripheral interrupt request signal DeIRQP) after the interrupt reference level signal Ser_BASE corresponding to the peripheral interrupt request signal DeIRQP.
  • the number of the peripheral interrupt request signal may be used to indicate the position of the interrupt identification bit corresponding to the peripheral interrupt request signal.
  • the first peripheral interrupt request signal may be used to trigger the peripheral interrupt request signal that forms the interrupt request identifier at the first interrupt identification bit.
  • the interrupt request signal converter 100 may be configured to form a converted interrupt request signal SerIRQ corresponding to the k-th peripheral interrupt request signal DeIRQ[j] in the clock cycle occupied by the blank frame B_F of the first interrupt reference level signal Ser_BASE received after receiving the k-th peripheral interrupt request signal DeIRQP in response to k-th peripheral interrupt request signal DeIRQ[j] the counter 111 being in the counting state but missing the k-th device identification value that matches the peripheral device that sent the k-th peripheral interrupt request signal DeIRQ[j] when the k-th peripheral interrupt request signal DeIRQ[j] is received.
  • the counter 111 may be placed in a recounting state after detecting the start frame STA_F of the first interrupt reference level signal Ser_BASE, and the interrupt request identifier corresponding to the k-th peripheral interrupt request signal DeIRQ[j] may be formed when the recounted value of the counter 111 is equal to the k-th device identification value.
  • the counter 111 may be reset.
  • the interrupt request signal converter 100 may be configured to form the converted interrupt request signal SerIRQ[ 2 ] corresponding to the k-th peripheral interrupt request signal DeIRQ[j] in the clock cycle occupied by the blank frame B_F of the first interrupt reference level signal Ser_BASE received after receiving the k-th peripheral interrupt request signal DeIRQP.
  • the interrupt request signal converter 100 may form an interrupt request identifier SQk corresponding to the k-th peripheral interrupt request signal when the recounted value of the counter 111 is equal to the k-th device identification value.
  • the counter 111 missing the k-th device identification value may be that the value of the counter 111 has passed the k-th device identification value in the current counting cycle of the counter 111 .
  • the current value of the counter 111 passing the k-th device identification value may be that the current value of the counter 111 is already greater than the k-th device identification value
  • the current value of the counter 111 passing the k-th device identification value may be that the current value of the counter 111 is already less than the k-th device identification value.
  • the counter 111 missing the k-th device identification value has the same or similar definition, which will not be repeated herein.
  • a converted interrupt request signal SerIRQ corresponding to the k-th peripheral interrupt request signal may be generated in the clock cycle occupied by the blank frame B_F of the first interrupt reference level signal Ser_BASE received after the k-th peripheral interrupt request signal is received.
  • the counter 111 may be placed in a counting state, and when the value of the counter 111 is equal to the k-th device identification value, an interrupt request identifier corresponding to the k-th peripheral interrupt request signal may be formed.
  • FIG. 14 is a second schematic diagram showing the interrupt reference level signal Ser_BASE, the peripheral interrupt request signal, and the converted interrupt request signal SerIRQ involved in the interrupt request signal conversion system 10 shown in FIG. 12 .
  • a converted interrupt request signal SerIRQ corresponding to the first peripheral interrupt request signal may be generated in the clock cycle occupied by the blank frame B_F of the first interrupt reference level signal Ser_BASE (that is, the second interrupt reference level signal Ser_BASE in FIG. 14 ) after receiving the first peripheral interrupt request signal DeIRQ[ 1 ].
  • the counter 111 starts counting and the value of the counter 111 is equal to the k-th device identification value, an interrupt request identifier corresponding to the k-th peripheral interrupt request signal may be formed.
  • FIG. 15 is a schematic diagram showing an example of the interrupt request signal conversion system 10 shown in FIG. 4 B .
  • the interrupt request signal converter 100 includes a counter 111 .
  • FIG. 16 is a first schematic diagram showing the peripheral interrupt request signal and the converted interrupt request signal SerIRQ involved in the interrupt request signal conversion system 10 shown in FIG. 15 .
  • the interrupt request signal converter 100 may be further configured to cause the counter 111 to start counting in response to receiving the k-th peripheral interrupt request signal DeIRQ[j] of the N peripheral interrupt request signals (the k-th peripheral interrupt request signal received from the j-th interrupt request signal input terminal), the counter 111 being reset and not being in the counting state.
  • the interrupt request signal converter 100 may be further configured to form the start frame STA_F of the converted interrupt request signal SerIRQ corresponding to the k-th peripheral interrupt request signal in response to the value of the counter 111 being between a reset value of the counter 111 and a first value.
  • the value of the counter 111 being between the reset value and the first value to form the start frame STA_F may be that when the value of the counter 111 is equal to either one of the first value (e.g., 1) and the first value (e.g., 4) after the reset value (e.g., 0), the corresponding part of the converted interrupt request signal may be set to the first level.
  • the interrupt request signal converter 100 may be further configured to form an interrupt request identifier of the converted interrupt request signal SerIRQ corresponding to the k-th peripheral interrupt request signal in response to the value of the counter 111 being equal to the k-th device identification value.
  • the k-th device identification value may match the peripheral device that sent the k-th peripheral interrupt request signal.
  • the interrupt request signal converter 100 may be further configured to form the end frame STO_F of the converted interrupt request signal SerIRQ corresponding to the k-th peripheral interrupt request signal in response to the value of the counter 111 being between a second value and a third value.
  • the reset value of the counter 111 , the first value, the device identification value, the second value, and the third value may all be non-negative integers and change monotonously.
  • the reset value of the counter 111 , the first value, the device identification value, the second value, and the third value may increase sequentially, i.e., the device identification value is larger than the first value, the second value is larger than the device identification value, and the third value is larger than the second value.
  • the length of time occupied by the start frame STA_F, the data frame D_F, and the end frame STO_F of the converted interrupt request signal SerIRQ may be equal to the predetermined values, such as x_start, x_data, and x_stop, by setting the reset value, the first value, the device identification value, the second value, and the third value of the counter 111 .
  • the device identification value matching the t-th peripheral device may equal to t*(x_num+1)+x_start, such as t*3+x_start, where t may be a positive integer less than or equal to n.
  • the reset value of the counter 111 , the first value, the second value, and the third value may be set based on the relevant protocol of the interface module of the processor. For example, for the interface module shown in FIG. 5 A , the reset value of the counter 111 , the first value, the second value, and the third value may be set to 0, 4, 57, and 59, respectively.
  • FIG. 17 is a second schematic diagram showing the peripheral interrupt request signal and the converted interrupt request signal SerIRQ involved in the interrupt request signal conversion system 10 shown in FIG. 15 .
  • the interrupt request signal converter 100 may be configured to reset the counter 111 and start recounting in response to receiving the k-th peripheral interrupt request signal DeIRQ[j], the counter 111 is in the counting state, and after the value of the counter 111 reaches a preset boundary value (e.g., the upper limit, e.g., the third value), where the second value, the third value, and the preset boundary value may change monotonously; and form the start frame STA_F, the interrupt request identifier, and the end frame STO_F of the converted interrupt request signal SerIRQ corresponding to the k-th peripheral interrupt request signal DeIRQ[j] in response to the recounting value of the counter 111 being selected between the reset value of the counter 111 and the first value, the k-th device identification value, and between the second value and the third value.
  • a preset boundary value e.g., the upper limit, e.g., the third value
  • the peripheral interrupt request signal DeIRQP (triggered to form an interrupt request identifier SQP) that triggers the counter 111 to start counting has been received. That is, when the k-th peripheral interrupt request signal DeIRQ[j] is received, the counter 111 is in the counting state. As shown in FIG. 17 , although the counter 111 does not miss the k-th device identification value, the interrupt request signal converter 100 can form a converted interrupt request signal corresponding to the k-th peripheral interrupt request signal DeIRQ[j] after the counter 111 starts recounting.
  • the interrupt request signal converter 100 may form the start frame STA_F of the converted interrupt request signal SerIRQ corresponding to the k-th peripheral interrupt request signal DeIRQ[j] after the recounted value of the counter 111 is between the reset value of the counter 111 and the first value; form an interrupt request identifier SQk of the converted interrupt request signal SerIRQ corresponding to the k-th peripheral interrupt request signal DeIRQ[j] when the recounted value of the counter 111 is equal to the k-th device identification value; and form the end frame STO_F of the converted interrupt request signal SerIRQ corresponding to the k-th peripheral interrupt request signal DeIRQ[j] when the recounted value of the counter 111 is between the second value and the third value.
  • the peripheral interrupt request signals (e.g., the plurality of peripheral interrupt request signals) received in the current counting cycle of the counter 111 may all be recorded. Then in the next counting cycle of the counter 111 , corresponding middle request identifiers (e.g., a plurality of middle request identifiers) and the interrupt request signal including these middle request identifiers may be formed based on the peripheral interrupt request signals recorded in the current counting cycle.
  • middle request identifiers e.g., a plurality of middle request identifiers
  • the interrupt request signal including these middle request identifiers may be formed based on the peripheral interrupt request signals recorded in the current counting cycle.
  • the predetermined time range may refer to the clock cycle occupied by the current counting cycle of the counter 111 (that is, the counting cycle before the counting cycle forming the converted interrupt request signal SerIRQ).
  • FIG. 18 is a third schematic diagram showing the peripheral interrupt request signal and the converted interrupt request signal SerIRQ involved in the interrupt request signal conversion system 10 shown in FIG. 15 .
  • the interrupt request signal converter 100 may be further configured to form an interrupt request identifier SQk corresponding to the converted interrupt request signal SerIRQ of the k-th peripheral interrupt request signal DeIRQ[j] in response to receiving the k-th peripheral interrupt request signal DeIRQ[j], the counter 111 is in the counting state and the k-th device identification value is not missed, and when the value of the counter 111 is equal to the k-th device identification value.
  • the peripheral interrupt request signal DeIRQP (triggered to form an interrupt request identifier SQP) that triggers the counter 111 to start counting has been received. That is, when the first peripheral interrupt request signal DeIRQ[ 1 ] is received, the counter 111 is in the counting state. As shown in FIG. 17 , since the counter 111 does not miss the first device identification value, when the value of the counter 111 is equal to the first device identification value, the interrupt request signal converter 100 can form an interrupt request identifier SQ 1 of the converted interrupt request signal SerIRQ corresponding to the first peripheral interrupt request signal DeIRQ[ 1 ].
  • the start frame STA_F, the interrupt request identifier, and the end frame STO_F of the converted interrupt request signal SerIRQ corresponding to the k-th peripheral interrupt request signal DeIRQ[j] can be formed when the recounted value of the counter 111 is selected from between the reset value of the counter 111 and the first value, the k-th device identification value, and between the second value and the third value in response to receiving the k-th peripheral interrupt request signal DeIRQ[j], and the counter 111 is in the counting state and missed the k-th device identification value.
  • the interrupt request signal converter 100 can form the start frame STA_F, the interrupt request identifier, and the end frame STO_F of the converted interrupt request signal SerIRQ corresponding to the k-th peripheral interrupt request signal DeIRQ[j] when the recounted value is selected from between the reset value of the counter 111 and the first value, the k-th device identification value, and between the second value and the third value.
  • the interrupt request signal converter 100 provided in FIG. 18 may include an interface module of a processor that can enable the interrupt request of a peripheral device to be sent more quickly.
  • the predetermined time range may refer to the time range from the time when the current counting cycle (that is, the counting cycle before the counting cycle of the converted interrupt request signal SerIRQ is formed) value of the counter 111 is the k-th device identification value to the time when the recounted value of the counter 111 is the k-th device identification value.
  • FIG. 19 is a schematic diagram of a computing device according to an embodiment of the present disclosure.
  • the computing device includes a processor and the interrupt request signal conversion system 10 provided by any embodiment of the present disclosure.
  • the processor includes an interface module 500 and interrupt controller.
  • the interface module 500 includes an interface controller 510 , and the interface controller 510 may be configured to report an interrupt request of a peripheral device requesting an interrupt to the interrupt controller based on at least one converted interrupt request signal SerIRQ.
  • the computing device may expand the types of applicable peripheral devices.
  • the interface module 500 may be configured to send at least one interrupt reference level signal Ser_BASE to the interrupt request signal conversion system 10 .
  • Each interrupt reference level signal Ser_BASE may include a start frame STA_F and an end frame STO_F.
  • the interface controller 510 may be further configured to use the end of the start frame STA_F of the interrupt reference level signal Ser_BASE corresponding to each converted interrupt request signal SerIRQ as the start time of each converted interrupt request signal SerIRQ, and determine the peripheral device that requests the interrupt identified by the interrupt identification bit of the first level based on the number of clock cycles between the converted interrupt request signal SerIRQ and the start time (that is, the end time of the start frame STA_F of the interrupt reference level signal Ser_Base) in at least one converted interrupt request signal SerIRQ that is the first level interrupt identification bit.
  • the interface module 500 may be configured to report the interrupt requests of all peripheral devices that request the interrupts identified by each converted interrupt request signal SerIRQ after the end frame STO_F is sent to the interrupt request signal conversion system 10 .
  • each converted interrupt request signal SerIRQ may include a start frame STA_F 2 and an end frame STO_F 2 (see FIG. 6 B ).
  • the interface controller 510 may be further configured to determine the peripheral device that requests the interrupt identified by the interrupt identification bit of the first level based on the number of clock cycles between the interrupt identification bit of the first level in each converted interrupt request signal SerIRQ and the start frame STA_F 2 .
  • the interface controller 510 may be further configured to report the interrupt request of the peripheral device requesting interrupt related to the interrupt request signal SerIRQ after receiving the end frame STO_F 2 of the interrupt request signal SerIRQ.
  • the interface module 500 of the processor may be implemented as the interface module 500 shown in FIG. 5 A .
  • the interface controller 510 of the interface module 500 also includes an interrupt clear/suspend module 512 .
  • the interrupt clear/suspend module 512 includes a mask register 512 a for the interrupt mode, and the mask register 512 a includes an interrupt mask identification bit.
  • the interrupt clear/suspend module 512 may be configured to suspend or clear the interrupt request reported by the interrupter 511 based on the value of the interrupt mask identification bit. For example, when the value of the interrupt mask identification bit is a first value (e.g., 1), the interrupt clear/suspend module 512 may mask (clear) the interrupt request reported by the interrupter 511 . In this way, the interrupt request received from the peripheral device can be masked (cleared) and cannot be reported to the processor core. In another example, when the value of the interrupt mask identification bit is different from the first value (e.g., 0), the interrupt clear/suspend module 512 may suspend the interrupt request reported by the interrupter 511 . In this way, the interrupt request received from the peripheral device can be reported to the processor core.
  • a first value e.g. 1
  • the interrupt clear/suspend module 512 may mask (clear) the interrupt request reported by the interrupter 511 . In this way, the interrupt request received from the peripheral device can be masked
  • the interface module 500 when the interrupt mode of the interface module 500 also includes a direct memory access (DMA) interrupt mode, the interface module 500 may also include a second interrupter, and the mask register 512 a may also include a second interrupt mask identification bit.
  • the interrupt clear/suspend module 512 may be configured to suspend or clear the interrupt request reported by the second interrupter based on the value of the second interrupt mask identification bit.
  • the interrupt mask identification bit may be located higher than the second interrupt mask identification bit.
  • the mask register 512 a is not limited to being set in the interrupt clear/suspend module 512 , but may also be set in the interrupter 511 or the third interface 533 .
  • the interrupter 511 or the third interface 533 may determine whether to mask (clear) the interrupt request received from the peripheral device based on the value of the interrupt mask identification bit, such that interrupt request cannot be reported to the processor core.
  • the third interface 533 may perform a logical AND operation (e.g., or logical operation) on at least part of the interrupt request signal SerIRQ and the value of the interrupt mask identification bit, and send the result of the logical operation to the interrupter 511 .
  • the value of the interrupt mask identification bit is the first value (e.g., 1)
  • the level of at least part of the interrupt identification bit may be set to the second level, and at least part of the interrupt identification bit can be masked (cleared).
  • the value of the interrupt mask identification bit is the second value (e.g., 0)
  • the interrupt request signal SerIRQ may remain unchanged.
  • FIG. 20 is a flowchart of an interrupt request signal conversion method according to an embodiment of the present disclosure. The method will be described in detail below.
  • each converted interrupt request signal may include a plurality of interrupt identification bits.
  • Each interrupt identification bit may be used to identify whether the signal received from the peripheral device corresponding to each interrupt identification bit includes a peripheral interrupt request signal within a predetermined time range based on a first level and a second level that may be different from the first level.
  • the interrupt request signal conversion method can expand the types of peripheral devices suitable for the interface module of the processor that receives the converted interrupt request signal obtained based on the interrupt request signal conversion method.
  • the interrupt request signal conversion method can expand the types of peripheral devices suitable for the interface module of the processor that receives the converted interrupt request signal obtained based on the interrupt request signal conversion method.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
US17/575,543 2021-01-15 2022-01-13 Interrupt request signal conversion system and method, and computing device Active 2042-02-11 US11816049B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110053411.7 2021-01-15
CN202110053411.7A CN112711549B (zh) 2021-01-15 2021-01-15 中断请求信号转换系统和方法、计算装置

Publications (2)

Publication Number Publication Date
US20220229794A1 US20220229794A1 (en) 2022-07-21
US11816049B2 true US11816049B2 (en) 2023-11-14

Family

ID=75549115

Family Applications (1)

Application Number Title Priority Date Filing Date
US17/575,543 Active 2042-02-11 US11816049B2 (en) 2021-01-15 2022-01-13 Interrupt request signal conversion system and method, and computing device

Country Status (3)

Country Link
US (1) US11816049B2 (zh)
EP (1) EP4060507A3 (zh)
CN (1) CN112711549B (zh)

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619703A (en) * 1995-06-06 1997-04-08 Cirrus Logic, Inc. Apparatus and method for supporting multiple interrupt protocols with unequal number of interrupt request signals
US5752043A (en) * 1995-06-27 1998-05-12 Kabushiki Kaisha Toshiba Interrupt control system provided in a computer
US5848278A (en) * 1995-09-29 1998-12-08 Kabushiki Kaisha Toshiba Serial interrrupt control system in a system in which a plurality of interrupt requesters are connected to a serial bus
US5940402A (en) * 1997-06-06 1999-08-17 Timeplex, Inc. Method and apparatus for TDM interrupt transmissions between multiple devices and a processor
US6115780A (en) * 1997-10-20 2000-09-05 Nec Corporation Interrupt steering circuit for PCI bus
CN1283286A (zh) 1997-12-23 2001-02-07 英特尔公司 将地址与数据线上的中断请求信号转换成中断消息信号的机制
US20030212844A1 (en) * 2002-05-10 2003-11-13 Wang Jennifer C. Method, apparatus, and system for generating serial interrupt requests (IRQ) with power savings
CN102768648A (zh) 2011-05-02 2012-11-07 快捷半导体(苏州)有限公司 低延迟中断收集器、具有该收集器的系统和相关方法
CN103077137A (zh) 2011-10-25 2013-05-01 北京大豪科技股份有限公司 中断控制方法及中断控制单元
US20130185469A1 (en) * 2010-10-22 2013-07-18 Mitsubishi Electric Corporation Interrupt signal accepting apparatus and computer apparatus
CN107544838A (zh) 2016-06-24 2018-01-05 中兴通讯股份有限公司 一种中断处理方法及装置
CN108369564A (zh) 2015-12-10 2018-08-03 高通股份有限公司 来自外围设备的中断的数字聚合

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619703A (en) * 1995-06-06 1997-04-08 Cirrus Logic, Inc. Apparatus and method for supporting multiple interrupt protocols with unequal number of interrupt request signals
US5752043A (en) * 1995-06-27 1998-05-12 Kabushiki Kaisha Toshiba Interrupt control system provided in a computer
US5848278A (en) * 1995-09-29 1998-12-08 Kabushiki Kaisha Toshiba Serial interrrupt control system in a system in which a plurality of interrupt requesters are connected to a serial bus
US5940402A (en) * 1997-06-06 1999-08-17 Timeplex, Inc. Method and apparatus for TDM interrupt transmissions between multiple devices and a processor
US6115780A (en) * 1997-10-20 2000-09-05 Nec Corporation Interrupt steering circuit for PCI bus
CN1283286A (zh) 1997-12-23 2001-02-07 英特尔公司 将地址与数据线上的中断请求信号转换成中断消息信号的机制
US20030212844A1 (en) * 2002-05-10 2003-11-13 Wang Jennifer C. Method, apparatus, and system for generating serial interrupt requests (IRQ) with power savings
US20130185469A1 (en) * 2010-10-22 2013-07-18 Mitsubishi Electric Corporation Interrupt signal accepting apparatus and computer apparatus
CN102768648A (zh) 2011-05-02 2012-11-07 快捷半导体(苏州)有限公司 低延迟中断收集器、具有该收集器的系统和相关方法
US20120284442A1 (en) * 2011-05-02 2012-11-08 Card Robert A Low latency interrupt collector
CN103077137A (zh) 2011-10-25 2013-05-01 北京大豪科技股份有限公司 中断控制方法及中断控制单元
CN108369564A (zh) 2015-12-10 2018-08-03 高通股份有限公司 来自外围设备的中断的数字聚合
CN107544838A (zh) 2016-06-24 2018-01-05 中兴通讯股份有限公司 一种中断处理方法及装置

Also Published As

Publication number Publication date
CN112711549A (zh) 2021-04-27
US20220229794A1 (en) 2022-07-21
EP4060507A2 (en) 2022-09-21
EP4060507A3 (en) 2022-09-28
CN112711549B (zh) 2023-08-01

Similar Documents

Publication Publication Date Title
US6078970A (en) System for determining adapter interrupt status where interrupt is sent to host after operating status stored in register is shadowed to host memory
EP4080373A1 (en) Interrupt request signal conversion system and method, and computing device
US10409744B1 (en) Low-latency wake-up in a peripheral device
US7124232B2 (en) Bus connection circuit and bus connection system having plural request queues, a bus interface portion outputting request signals, an arbiter performing arbitration of plural requests and a bus interface portion outputting a request signal indicating allocation of pre-fetch buffers corresponding to arbitrated requests
CN114817110B (zh) 一种数据传输方法及装置
US20170329730A1 (en) Method and unit for handling interrupts in a system
CN109933549B (zh) 一种适用于risc-v处理器的中断控制器
US8244947B2 (en) Methods and apparatus for resource sharing in a programmable interrupt controller
US5881294A (en) System for transforming PCI level interrupts
US11816049B2 (en) Interrupt request signal conversion system and method, and computing device
CN105487989A (zh) 一种降低响应延时提高系统效率的中断控制器及控制方法
CN116360853B (zh) 寄存器映射方法、装置、设备及介质
CN102591817A (zh) 一种多总线桥控制器及其实现方法
CN110750472A (zh) 一种int中断转msi中断的转换方法、装置及存储介质
CN106844025B (zh) 一种异步中断处理方法及中断控制器
WO2019120294A1 (en) Data-processing apparatus, data transmission method, and computing system thereof
WO2019169582A1 (zh) 处理中断的方法和装置
US6734984B2 (en) System having an arithmetic-logic circuit for determining the maximum or minimum of a plurality of codes
WO2018106392A1 (en) Technologies for multi-core wireless network data transmission
US9146776B1 (en) Systems and methods for controlling flow of message signaled interrupts
CN116136790A (zh) 任务处理方法和装置
US9229791B1 (en) System and method for high speed multiple buffer allocation
CN112130982A (zh) 中断控制装置、方法及系统
CN111722916A (zh) 一种通过映射表处理msi-x中断的方法
US10002087B1 (en) Communication between an external processor and FPGA controller

Legal Events

Date Code Title Description
AS Assignment

Owner name: PHYTIUM TECHNOLOGY CO., LTD., CHINA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FAN, LIZHENG;CHEN, CAI;LIU, FUDONG;AND OTHERS;REEL/FRAME:058653/0011

Effective date: 20220107

FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE