US11543986B2 - Electronic system including host, memory controller and memory device and method of operating the same - Google Patents

Electronic system including host, memory controller and memory device and method of operating the same Download PDF

Info

Publication number
US11543986B2
US11543986B2 US17/304,076 US202117304076A US11543986B2 US 11543986 B2 US11543986 B2 US 11543986B2 US 202117304076 A US202117304076 A US 202117304076A US 11543986 B2 US11543986 B2 US 11543986B2
Authority
US
United States
Prior art keywords
memory
block addresses
logical block
segments
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US17/304,076
Other languages
English (en)
Other versions
US20220171532A1 (en
Inventor
Hye Mi KANG
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
SK Hynix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SK Hynix Inc filed Critical SK Hynix Inc
Assigned to SK Hynix Inc. reassignment SK Hynix Inc. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KANG, HYE MI
Publication of US20220171532A1 publication Critical patent/US20220171532A1/en
Application granted granted Critical
Publication of US11543986B2 publication Critical patent/US11543986B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0253—Garbage collection, i.e. reclamation of unreferenced memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7205—Cleaning, compaction, garbage collection, erase control

Definitions

  • Various embodiments described in the present disclosure generally relate to an electronic device, and more particularly, to an electronic system and a method of operating the electronic system.
  • a storage device is a device that stores data under the control of a host device, such as a computer, a smartphone, or a smartpad.
  • a host device such as a computer, a smartphone, or a smartpad.
  • the storage device include a device such as a hard disk drive (HDD) which may store data in a magnetic disk, and a device such as a solid state drive (SSD) or a memory card which may store data in a semiconductor memory, particularly, a nonvolatile memory, according to the device in which the data is stored.
  • HDD hard disk drive
  • SSD solid state drive
  • memory card which may store data in a semiconductor memory, particularly, a nonvolatile memory, according to the device in which the data is stored.
  • the storage device may include a memory device in which data is stored and a memory controller which controls the storage of data in the memory device.
  • memory devices may be classified into volatile memory and nonvolatile memory.
  • Representative examples of the nonvolatile memory include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase-change random access memory (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and a ferroelectric RAM (FRAM).
  • Various embodiments described in the present disclosure are directed to an electronic system that translates randomly written logical block addresses into addresses corresponding to consecutive data, and a method of operating the electronic system.
  • an electronic system may include a file system is configured to assign logical block addresses corresponding to consecutive pieces of data to sets of segments in a plurality of zones.
  • the electronic system may also include a memory device including a plurality of memory blocks, and a memory controller configured to map the logical block addresses to physical block addresses corresponding to consecutive pages in the plurality of memory blocks to program the consecutive pieces of data to the consecutive pages in the plurality of memory blocks.
  • the file system may be configured to assign new logical block addresses corresponding to consecutive pieces of a data file to invalid segments in the plurality of zones. Each of the invalid segments may have been assigned a logical block address that is mapped to a physical block address associated with invalid data.
  • the method may include assigning logical block addresses corresponding to consecutive pieces of data to sets of segments in a plurality of zones; generating mapping relationships between the logical block addresses and physical block addresses corresponding to consecutive pages in the plurality of memory blocks; programming, based on the mapping relationships, the consecutive pieces of data to the consecutive pages in the plurality of memory blocks; updating the mapping relationships, the updated mapping relationships indicating one or more physical block addresses associated with invalid data; and assigning new logical block addresses corresponding to consecutive pieces of a data file to invalid segments, where each of the invalid segments has been assigned a logical block address mapped to a physical block address of the one or more physical block addresses associated with invalid data.
  • FIG. 1 is a block diagram of an example of a storage device.
  • FIG. 2 is a block diagram illustrating the structure of an example of a memory device of the storage device of FIG. 1 .
  • FIG. 3 is a diagram illustrating an example of a memory cell array of the memory device of FIG. 2 .
  • FIG. 4 is a simplified diagram illustrating an example of outputting and updating map data between a host and a storage device.
  • FIG. 5 is a diagram illustrating zones of an example of a file system and programmed memory blocks.
  • FIG. 6 is a diagram illustrating examples of invalidated pages when map update occurs.
  • FIG. 7 is a diagram illustrating an example of updating respective zones of a file system depending on map update.
  • FIG. 8 is a diagram illustrating an example in which logical block addresses are overwritten to invalidated segments.
  • FIG. 9 is a diagram illustrating an example of programming data after logical block addresses are overwritten.
  • FIG. 10 is a diagram illustrating an example of a process in which garbage collection is performed in a file system.
  • FIG. 11 is a diagram illustrating mapping relationships that are changed after garbage collection has been performed on a file system.
  • FIG. 12 is a flowchart illustrating an example of the operation of an electronic system according to an embodiment.
  • FIG. 13 is a flowchart illustrating an example of the operation of an electronic system according to an embodiment.
  • FIG. 14 is a block diagram illustrating an example of a memory controller of the storage device of FIG. 1 .
  • FIG. 15 illustrates an example of a memory card system in which a storage device according to an embodiment may be used.
  • FIG. 16 is a block diagram of an example of a solid state drive (SSD) system in which a storage device according to an embodiment may be used.
  • SSD solid state drive
  • FIG. 17 is a block diagram illustrating an example of a user system in which a storage device according to an embodiment may be used.
  • FIG. 1 is a block diagram of an example of a storage device.
  • a storage device 50 may include one or more memory devices 100 and a memory controller 200 .
  • the storage device 50 may be a device that stores data under the control of a host 300 , such as a mobile phone, a smartphone, an MP3 player, a laptop computer, a desktop computer, a game console, a television (TV), a tablet PC, or an in-vehicle infotainment system.
  • a host 300 such as a mobile phone, a smartphone, an MP3 player, a laptop computer, a desktop computer, a game console, a television (TV), a tablet PC, or an in-vehicle infotainment system.
  • the storage device 50 may include any one of various types of storage devices, depending on a host interface that is a scheme for communication with the host 300 .
  • the storage device 50 may be implemented as any one of various types of storage devices, such as a solid state disk (SSD), a multimedia card such as an MMC, an embedded MMC (eMMC), a reduced size MMC (RS-MMC), or a micro-MMC, a secure digital card such as an SD, a mini-SD, or a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card-type storage device, a peripheral component interconnection (PCI)-card type storage device, a PCI express (PCI-E) card-type storage device, a compact flash (CF) card, a smart media card, a memory stick, and the like.
  • SSD solid state disk
  • MMC multimedia card
  • eMMC embedded MMC
  • RS-MMC reduced
  • the storage device 50 may be manufactured in any one of various types of package forms.
  • the storage device 50 may be manufactured in any one of various types of package forms, such as package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer-level fabricated package (WFP), wafer-level stack package (WSP), and the like.
  • POP package on package
  • SIP system in package
  • SOC system on chip
  • MCP multi-chip package
  • COB chip on board
  • WFP wafer-level fabricated package
  • WSP wafer-level stack package
  • the memory device 100 may store data.
  • the memory device 100 may operate in response to the control of the memory controller 200 .
  • the memory device 100 may include a memory cell array including a plurality of memory cells that can store data.
  • the memory cell array may include a plurality of memory blocks.
  • Each memory block may include a plurality of memory cells, which may constitute a plurality of pages.
  • a page may be a unit by which data is stored in the memory device 100 or by which data stored in the memory device 100 is read.
  • a memory block may be a unit by which data is erased.
  • the memory device 100 may take many alternative forms, such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate fourth generation (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory device, a resistive RAM (RRAM), a phase-change RAM (PRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FRAM), or a spin transfer torque RAM (STT-RAM).
  • DDR SDRAM double data rate synchronous dynamic random access memory
  • LPDDR4 SDRAM low power double data rate fourth generation SDRAM
  • GDDR SDRAM graphics double data rate SDRAM
  • LPDDR SDRAM low power DDR SDRAM
  • RDRAM Rambus dynamic random access memory
  • NAND flash memory a NAND flash memory
  • vertical NAND flash memory a vertical NAND
  • the memory device 100 may be implemented in a two-dimensional (2D) array structure or a three-dimensional (3D) array structure.
  • 2D two-dimensional
  • 3D three-dimensional
  • the present disclosure is not limited to the 3D array structure.
  • the present disclosure may also be applied not only to a flash memory device in which a charge storage layer is formed of a conductive floating gate (FG), but also to a charge trap flash (CTF) memory device in which a charge storage layer is formed of an insulating layer.
  • FG conductive floating gate
  • CTF charge trap flash
  • the memory device 100 may operate in a single-level cell (SLC) manner in which one data bit is stored in one memory cell.
  • the memory device 100 may operate in a manner in which at least two data bits are stored in one memory cell.
  • the memory device 100 may operate in a multi-level cell (MLC) manner in which two data bits are stored in one memory cell, a triple-level cell (TLC) manner in which three data bits are stored in one memory cell, a quadruple-level cell (QLC) manner in which four data bits are stored in one memory cell, or the like.
  • MLC multi-level cell
  • TLC triple-level cell
  • QLC quadruple-level cell
  • the memory device 100 may receive a command and an address from the memory controller 200 , and may access an area of the memory cell array selected by the address. That is, the memory device 100 may perform an operation corresponding to the command on the area selected by the address. For example, the memory device 100 may perform a write operation (i.e., program operation), a read operation, or an erase operation in response to the received command.
  • a program command is received
  • the memory device 100 may program data to the area selected based on the address.
  • a read command is received, the memory device 100 may read data from the area selected based on the address.
  • an erase command is received, the memory device 100 may erase data stored in the area selected based on the address.
  • the memory controller 200 may control the overall operation of the storage device 50 .
  • the memory controller 200 may run firmware.
  • the memory controller 200 may run firmware, such as a Flash Translation Layer (FTL), for controlling communication between the host 300 and the memory device 100 .
  • FTL Flash Translation Layer
  • the memory controller 200 may include firmware (not illustrated) that may receive data and a logical block address (LBA) from the host 300 , and may translate the logical block address (LBA) into a physical block address (PBA) indicating the address of memory cells which are included in the memory device 100 and in which data is to be stored. Further, the memory controller 200 may store a logical-physical address mapping table, which indicates mapping relationships between logical block addresses (LBA) and physical block addresses (PBA), in a buffer memory.
  • firmware not illustrated
  • LBA logical block address
  • PBA physical block address
  • the memory controller 200 may control the memory device 100 so that a program operation, a read operation, or an erase operation can be performed in response to a request received from the host 300 .
  • the memory controller 200 may convert the program request into a program command, and may provide the program command, a physical block address (PBA), and data to the memory device 100 .
  • PBA physical block address
  • the memory controller 200 may convert the read request into a read command, select a physical block address corresponding to the logical block address, and thereafter provide the read command and the physical block address (PBA) to the memory device 100 .
  • the memory controller 200 may convert the erase request into an erase command, select a physical block address corresponding to the logical block address, and thereafter provide the erase command and the physical block address (PBA) to the memory device 100 .
  • PBA physical block address
  • the memory controller 200 may autonomously generate a program command, an address, and data without receiving a request from the host 300 , and may transmit them to the memory device 100 .
  • the memory controller 200 may provide commands, addresses, and data to the memory device 100 so as to perform background operations, such as a program operation for wear leveling to equalize memory space usage, and a program operation for garbage collection that clears outdated data from memory.
  • the memory controller 200 may include a flash translation layer 210 .
  • the flash translation layer 210 may translate a logical block address (LBA) corresponding to a request received from the host 300 into a physical block address (PBA), and may output the physical block address (PBA) to the memory device 100 .
  • LBA logical block address
  • PBA physical block address
  • the flash translation layer 210 may translate a logical block address (LBA) corresponding to a program request into a physical block address (PBA), translate a logical block address (LBA) corresponding to a read request into a physical block address (PBA), or translate a logical block address (LBA) corresponding to an erase request into a physical block address (PBA).
  • the flash translation layer 210 may output the translated physical block address (PBA) to the memory device 100 , and the memory device 100 may perform an operation on a page or a memory block corresponding to the physical block address (PBA).
  • the memory controller 200 may receive consecutive logical block addresses from a file system 310 , and may translate the received logical block addresses into consecutive physical block addresses. When the consecutive physical block addresses are output to the memory device 100 , the memory device 100 may perform consecutive operations corresponding to the consecutive physical block addresses.
  • the storage device 50 may include a buffer memory (not illustrated).
  • the memory controller 200 may control data exchange between the host 300 and the buffer memory (not illustrated).
  • the memory controller 200 may temporarily store system data for controlling the memory device 100 in the buffer memory.
  • the memory controller 200 may temporarily store data from the host 300 in the buffer memory, and may then transmit the data temporarily stored in the buffer memory to the memory device 100 .
  • the buffer memory may be used as a working memory or a cache memory for the memory controller 200 .
  • the buffer memory may store codes or commands to be executed by the memory controller 200 .
  • the buffer memory may store data to be processed by the memory controller 200 .
  • the buffer memory may be implemented as a DRAM, such as a double data rate SDRAM (DDR SDRAM), a double data rate fourth generation (DDR4) SDRAM, a low power double data rate fourth generation (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR) SDRAM, or a Rambus DRAM (RDRAM), or may be implemented as a static RAM (SRAM).
  • DDR SDRAM double data rate SDRAM
  • DDR4 SDRAM double data rate fourth generation SDRAM
  • LPDDR4 SDRAM low power double data rate fourth generation SDRAM
  • GDDR SDRAM graphics double data rate SDRAM
  • LPDDR SDRAM low power DDR SDRAM
  • RDRAM Rambus DRAM
  • SRAM static RAM
  • the buffer memory may be outside the storage device 50 and may be coupled to the storage device 50 .
  • volatile memory devices coupled to the storage device 50 may function as the buffer memory.
  • the memory controller 200 may control at least two memory devices. In this case, the memory controller 200 may control the memory devices according to an interleaving scheme to improve operating performance.
  • the host 300 may communicate with the storage device 50 using at least one of various communication methods, such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed Interchip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnection (PCI), PCI express (PCIe), Nonvolatile Memory express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMedia Card (MMC), embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM) communication methods.
  • USB Universal Serial Bus
  • SATA Serial AT Attachment
  • SAS Serial Attached SCSI
  • HSIC High Speed Interchip
  • SCSI Small Computer System Interface
  • PCI Peripheral Component Interconnection
  • PCIe PCI express
  • NVMe Nonvolatile Memory express
  • UFS Universal Flash Storage
  • SD Secure Digital
  • MMC MultiMedia Card
  • eMMC embedded MMC
  • the host 300 may include the file system 310 .
  • the file system 310 may include a plurality of zones for improving the consecutive write performance of the storage device 50 .
  • the plurality of zones may be implemented using nonvolatile memory devices or volatile memory devices.
  • each of the plurality of zones may include segments.
  • a segment to which a logical block address is assigned may be a valid segment
  • a segment to which a logical block address is not assigned may be a free segment.
  • a valid segment may be invalidated, and thus may become an invalid segment (also referred to as invalidated segment).
  • garbage collection may be performed, or alternatively, data may be overwritten to invalid segments, thus enabling the invalid segments to be reused.
  • Consecutive logical block addresses may be assigned to the plurality of zones. For example, logical block addresses corresponding to consecutive write requests may be sequentially assigned to free segments among the segments included in the plurality of zones. That is, in an embodiment, when a bad block, a failed page, or an invalid page is not included in the memory device 100 , the performance of the storage device 50 controlled by the file system 310 may be improved.
  • random writing rather than consecutive (continuous) writing may be performed. For example, a large amount of overwriting may occur in a plurality of zones of the file system 310 , and random writing may be performed on the memory device 100 . When random writing is performed, the performance of the storage device 50 may be deteriorated.
  • the present disclosure proposes a method of improving the performance of the storage device 50 when random writing may be performed due to the absence of a free segment in the file system 310 .
  • FIG. 2 is a block diagram illustrating the structure of an example of a memory device of the storage device of FIG. 1 .
  • the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .
  • the memory cell array 110 includes a plurality of memory blocks BLK 1 to BLKz.
  • the plurality of memory blocks BLK 1 to BLKz are coupled to a row decoder 121 through row lines RL.
  • the row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line.
  • Each of the memory blocks BLK 1 to BLKz may be coupled to a page buffer group 123 through bit lines BL 1 to BLn.
  • Each of the memory blocks BLK 1 to BLKz may include a plurality of memory cells.
  • the plurality of memory cells may be nonvolatile memory cells.
  • Memory cells coupled to the same word line may be defined as a single page. Therefore, a single memory block may include a plurality of pages.
  • Each of the memory cells included in the memory cell array 110 may be implemented as a single-level cell (SLC) capable of storing one data bit, a multi-level cell (MLC) capable of storing two data bits, a triple-level cell (TLC) capable of storing three data bits, a quadruple-level cell (QLC) capable of storing four data bits, and the like.
  • SLC single-level cell
  • MLC multi-level cell
  • TLC triple-level cell
  • QLC quadruple-level cell
  • the peripheral circuit 120 may perform a program operation, a read operation, or an erase operation on a selected area of the memory cell array 110 under the control of the control logic 130 .
  • the peripheral circuit 120 may drive the memory cell array 110 .
  • the peripheral circuit 120 may apply various operating voltages to the row lines RL and the bit lines BL 1 to BLn or discharge the applied voltages under the control of the control logic 130 .
  • the peripheral circuit 120 may include the row decoder 121 , a voltage generator 122 , the page buffer group 123 , a column decoder 124 , an input/output circuit 125 , and a sensing circuit 126 .
  • the row decoder 121 is coupled to the memory cell array 110 through the row lines RL.
  • the row lines RL may include the at least one source select line, the plurality of word lines, and the at least one drain select line.
  • the word lines may include normal word lines and dummy word lines.
  • the row lines RL may further include a pipe select line.
  • the row decoder 121 may decode a row address RADD received from the control logic 130 .
  • the row decoder 121 selects at least one of the memory blocks BLK 1 to BLKz according to the decoded address. Further, the row decoder 121 may select at least one word line WL of the selected memory block so that voltages generated by the voltage generator 122 are applied to the at least one word line WL according to the decoded address.
  • the row decoder 121 may apply a program voltage to a selected word line and apply a program pass voltage having a level lower than that of the program voltage to unselected word lines.
  • the row decoder 121 may apply a verify voltage to a selected word line and apply a verify pass voltage higher than the verify voltage to unselected word lines.
  • the row decoder 121 may apply a read voltage to a selected word line and apply a read pass voltage higher than the read voltage to unselected word lines.
  • the erase operation of the memory device 100 is performed on a memory block basis.
  • the row decoder 121 may select one memory block according to the decoded address.
  • the row decoder 121 may apply a ground voltage to word lines coupled to the selected memory block.
  • the voltage generator 122 may be operated under the control of the control logic 130 .
  • the voltage generator 122 may generate a plurality of voltages using, for example, an external supply voltage provided to the memory device 100 . More specifically, the voltage generator 122 may generate various operating voltages Vop that are used for program, read, and erase operations in response to an operation signal OPSIG. For example, the voltage generator 122 may generate a program voltage, a verify voltage, a pass voltages, a read voltage, an erase voltage, etc. under the control of the control logic 130 .
  • the voltage generator 122 may generate an internal supply voltage by regulating the external supply voltage.
  • the internal supply voltage generated by the voltage generator 122 is used as an operating voltage for the memory device 100 .
  • the voltage generator 122 may generate a plurality of voltages using the external supply voltage or the internal supply voltage.
  • the voltage generator 122 may include a plurality of pumping capacitors for receiving the internal supply voltage and may generate a plurality of voltages by selectively enabling the plurality of pumping capacitors under the control of the control logic 130 .
  • the generated voltages may be supplied to the memory cell array 110 by the row decoder 121 .
  • the page buffer group 123 includes first to nth page buffers PB 1 to PBn.
  • the first to nth page buffers PB 1 to PBn are coupled to the memory cell array 110 through the first to nth bit lines BL 1 to BLn.
  • the first to nth page buffers PB 1 to PBn are operated under the control of the control logic 130 . More specifically, the first to nth page buffers PB 1 to PBn may be operated in response to page buffer control signals PBSIGNALS.
  • the first to nth page buffers PB 1 to PBn may temporarily store data received through the first to nth bit lines BL 1 to BLn or may sense voltages or currents of the bit lines BL 1 to BLn during a read or verify operation.
  • the first to nth page buffers PB 1 to PBn may transfer the data, received through the input/output circuit 125 , to selected memory cells through the first to nth bit lines BL 1 to BLn.
  • the memory cells in the selected page are programmed based on the received data DATA.
  • the first to nth page buffers PB 1 to PBn may read page data by sensing the voltages or currents received through the first to nth bit lines BL 1 to BLn from the selected memory cells.
  • the first to nth page buffers PB 1 to PBn may read data DATA from the memory cells in the selected page through the first to nth bit lines BL 1 to BLn, and may output the read data DATA to the input/output circuit 125 under the control of the column decoder 124 .
  • the first to nth page buffers PB 1 to PBn may allow the first to nth bit lines BL 1 to BLn to float or may apply the erase voltage to the first to nth bit lines BL 1 to BLn.
  • the column decoder 124 may transfer data between the input/output circuit 125 and the page buffer group 123 in response to a column address CADD. For example, the column decoder 124 may exchange data with the first to nth page buffers PB 1 to PBn through data lines DL or may exchange data with the input/output circuit 125 through column lines CL.
  • the input/output circuit 125 may transfer a command CMD and an address ADDR, received from the memory controller (e.g., memory controller 200 of FIG. 1 ) described above with reference to FIG. 1 , to the control logic 130 , or may exchange data DATA with the column decoder 124 .
  • the memory controller e.g., memory controller 200 of FIG. 1
  • ADDR address ADDR
  • the sensing circuit 126 may generate a reference current in response to an enable bit VRYBIT, and may compare a sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current and then output a pass signal PASS or a fail signal FAIL.
  • the control logic 130 may control the peripheral circuit 120 by outputting the operation signal OPSIG, the row address RADD, the page buffer control signals PBSIGNALS, and the enable bit VRYBIT in response to the command CMD and the address ADDR. For example, the control logic 130 may control a read operation on a selected memory block in response to a sub-block read command and an address. Also, the control logic 130 may control an erase operation on a selected sub-block included in a selected memory block in response to a sub-block erase command and an address. In addition, the control logic 130 may determine whether a verify operation has passed or failed in response to the pass or fail signal PASS or FAIL.
  • FIG. 3 is a diagram illustrating an example of a memory cell array of the memory device of FIG. 2 .
  • FIG. 3 is a circuit diagram illustrating any one memory block BLKa of a plurality of memory blocks BLK 1 to BLKz included in the memory cell array 110 of FIG. 2 .
  • the memory block BLKa may be coupled to a first select line, word lines, and a second select line that are coupled in parallel to each other.
  • the word lines may be coupled in parallel to each other between the first and second select lines.
  • the first select line may be a source select line SSL
  • the second select line may be a drain select line DSL.
  • the memory block BLKa may include a plurality of strings coupled between bit lines BL 1 to BLn and a source line SL.
  • the bit lines BL 1 to BLn may be coupled to the strings, respectively, and the source line SL may be coupled in common to the strings. Since the strings may be similarly configured, a string ST coupled to the first bit line BL 1 will be described in detail by way of example.
  • the string ST may include a source select transistor SST, a plurality of memory cells F 1 to F 16 , and a drain select transistor DST, which are coupled in series to each other between the source line SL and the first bit line BL 1 .
  • a single string ST may include at least one source select transistor SST and at least one drain select transistor DST, and fewer or more memory cells than the memory cells F 1 to F 16 illustrated in FIG. 3 may be included in the string ST.
  • a source of the source select transistor SST may be coupled to the source line SL, and a drain of the drain select transistor DST may be coupled to the first bit line BL 1 .
  • the memory cells F 1 to F 16 may be coupled in series between the source select transistor SST and the drain select transistor DST. Gates of the source select transistors SST included in different strings ST may be coupled to the source select line SSL, gates of the drain select transistors DST included in different strings ST may be coupled to the drain select line DSL, and gates of the memory cells F 1 to F 16 may be coupled to a plurality of word lines WL 1 to WL 16 , respectively.
  • a group of memory cells coupled to the same word line, among the memory cells included in different strings ST, may be referred to as a “physical page” (“PPG”). Therefore, the memory block BLKa may include a number of physical pages PPG identical to the number of word lines WL 1 to WL 16 .
  • One memory cell may store one bit of data. This cell is typically designated as a “single-level cell” (“SLC”).
  • SLC single-level cell
  • one physical page PPG may store data corresponding to one logical page LPG.
  • the data corresponding to one logical page LPG may include a number of data bits identical to the number of memory cells included in one physical page PPG.
  • one memory cell may store two or more bits of data.
  • This cell is typically designated as a “multi-level cell” (“MLC”).
  • MLC multi-level cell
  • one physical page PPG may store data corresponding to two or more logical pages LPG.
  • a memory cell in which two or more bits of data are stored is called a multi-level cell (MLC).
  • MLC multi-level cell
  • TLC triple-level cell
  • QLC quadruple-level cell
  • a memory cell scheme in which multiple bits of data are stored has been developed, and the present embodiment may be applied to the memory device 100 in which two or more bits of data are stored in one memory cell.
  • each of the memory blocks may have a three-dimensional (3D) structure.
  • Each of the memory blocks may include a plurality of memory cells stacked vertically on a substrate. The plurality of memory cells are arranged in +X, +Y, and +Z directions.
  • FIG. 4 is a simplified diagram illustrating an example of outputting and updating map data between a host and a storage device.
  • the host 300 of FIG. 4 may include a file system 310
  • the storage device 50 of FIG. 4 may include a flash translation layer 210 and a memory device 100 .
  • the memory device 100 may not physically perform overwriting. Rather, during a program operation, the memory device 100 may perform an erase operation on the plurality of memory cells and thereafter program the plurality of memory cells (i.e., write after erase).
  • the memory controller for controlling the memory device 100 may include the flash translation layer 210 which maps logical block addresses (LBA) to physical block addresses (PBA) so that consecutive write operations are physically performed on the memory device 100 .
  • LBA logical block addresses
  • PBA physical block addresses
  • the flash translation layer 210 may allow the memory device 100 to perform consecutive write operations by mapping a physical block address (PBA) corresponding to a logical block address (LBA) to a new physical block address other than an invalidated address.
  • PBA physical block address
  • LBA logical block address
  • the flash translation layer 210 may form a mapping relationship between the logical block address (LBA) and the physical block address (PBA), and may output the physical block address (PBA) to the memory device 100 .
  • LBA logical block address
  • PBA physical block address
  • the flash translation layer 210 may update a mapping relationship between the logical block address (LBA) and the physical block address (PBA) based on update information UPDATE_INF output from the memory device 100 . That is, the flash translation layer 210 may form a new mapping relationship between the logical block address (LBA) and the physical block address (PBA).
  • LBA logical block address
  • PBA physical block address
  • the file system 310 may improve the performance of the memory device 100 . More specifically, the file system 310 may perform an operation of improving the performance of the memory device 100 during consecutive write operations of the memory device 100 .
  • the file system 310 may sequentially assign logical block addresses (LBA) corresponding to the consecutive program requests.
  • the file system 310 may sequentially assign consecutive logical block addresses (LBA) to the plurality of zones, and may output the consecutive logical block addresses to the storage device 50 .
  • the file system 310 may autonomously update the logical block addresses (LBA) by sequentially assigning the consecutive logical block addresses (LBA) to the plurality of zones. Also, the file system 310 may autonomously perform garbage collection (GC) in the same manner as the memory device 100 . That is, when a logical block address (LBA) of a specific segment, among segments included in a specific zone, is invalidated, garbage collection (GC) may be performed to secure free segments. Such garbage collection (GC) for the file system 310 may be performed during an idle time.
  • LBA logical block address
  • GC garbage collection
  • garbage collection may not be performed, and thus the file system 310 may assign a new logical block address (LBA) to a segment corresponding to an invalidated logical block address (LBA). This is referred to as a “slack space recycling (SSR)”.
  • SSR stack space recycling
  • foreground garbage collection rather than background garbage collection (background GC)
  • background garbage collection background GC
  • LBA logical block address
  • foreground garbage collection is an operation distinguished from background garbage collection (background GC), and denotes an operation performed after the file system 310 has completed an operation currently being performed. Foreground GC may be performed when background GC cannot be performed.
  • a new logical block address may be assigned to an invalidated segment through foreground garbage collection (foreground GC). That is, foreground garbage collection (foreground GC) may be an operation that influences latency, and background garbage collection (background GC) may be an operation that does not influence latency because it is performed at an idle time during the operation of the file system 310 .
  • foreground garbage collection foreground GC
  • background garbage collection background GC
  • the memory device 100 may perform a random write operation rather than consecutive write operations. That is, since new logical block addresses (LBA) are randomly assigned to a plurality of zones of the file system 310 , the memory device 100 may perform a random write operation.
  • LBA new logical block addresses
  • the present disclosure provides a method of assigning a new logical block address (LBA) to a segment corresponding to an invalidated logical block address (LBA) through foreground garbage collection (foreground GC) while performing consecutive write operations on the memory device 100 and assigning logical block addresses (LBA) assigned to a plurality of zones to a single zone.
  • LBA new logical block address
  • foreground GC foreground garbage collection
  • FIG. 5 is a diagram illustrating zones of an example of a file system and programmed memory blocks.
  • FIG. 5 illustrates a plurality of zones included in the file system of FIG. 4 (e.g., file system 310 of FIG. 4 ), and a plurality of memory blocks included in the memory device of FIG. 4 (e.g., memory device 100 of FIG. 4 ).
  • a plurality of zones are first to third zones ZONE 1 to ZONE 3 and a plurality of memory blocks are first to third memory blocks BLK 1 to BLK 3
  • more zones or fewer zones may be included in the file system (e.g., file system 310 of FIG. 4 ), and more memory blocks or fewer memory blocks may be included in the memory device (e.g., memory device 100 of FIG. 4 ).
  • Each of the first to third zones ZONE 1 to ZONE 3 may include a plurality of segments.
  • each of the first to third zones ZONE 1 to ZONE 3 may be a unit on which garbage collection (GC) is performed, where each zone may correspond to a memory block.
  • Each of the plurality of segments may be a unit on which a program operation and a read operation are performed, where each segment may correspond to a page included in a memory block.
  • logical block addresses (LBA) output from the host are logical block addresses (LBA) corresponding to consecutive program requests.
  • LBA logical block addresses
  • consecutive program operations are performed in the example. That is, after pieces of data included in a first file FILE 1 have been consecutively programmed, pieces of data included in a second file FILE 2 and pieces of data included in a third file FILE 3 may be consecutively programmed.
  • the file system (e.g., file system 310 of FIG. 4 ) may include first to third zones ZONE 1 to ZONE 3 , each of which may include seven segments.
  • a logical block address (LBA) may be assigned to each segment.
  • first to seventh logical block addresses LBA 1 to LBA 7 corresponding to pieces of data included in the first file FILE 1 may be assigned to the first zone ZONE 1
  • eighth to fourteenth logical block addresses LBA 8 to LBA 14 corresponding to pieces of data included in the second file FILE 2 may be assigned to the second zone ZONE 2
  • fifteenth to 21st logical block addresses LBA 15 to LBA 21 corresponding to pieces of data included in the third file FILE 3 may be assigned to the third zone ZONE 3 .
  • consecutive program operations that is, consecutive write operations, may be performed on memory blocks included in the memory device (e.g., memory device 100 of FIG. 4 ).
  • the flash translation layer may assign first to seventh logical block addresses LBA 1 to LBA 7 to consecutive physical block addresses. That is, the flash translation layer may sequentially map the first to seventh logical block addresses LBA 1 to LBA 7 to physical block addresses corresponding to pages included in the first memory block BLK 1 .
  • the flash translation layer may sequentially map the eighth to fourteenth logical block addresses LBA 8 to LBA 14 to physical block addresses corresponding to pages included in the second memory block BLK 2 , and may sequentially map the fifteenth to 21st logical block addresses LBA 15 to LBA 21 to physical block addresses corresponding to pages included in the third memory block BLK 3 .
  • the memory device e.g., memory device 100 of FIG. 4
  • consecutive program operations may be performed.
  • the pieces of data included in the first file FILE 1 may be sequentially programmed to the pages included in the first memory block BLK 1
  • the pieces of data included in the second file FILE 2 may be sequentially programmed to the pages included in the second memory block BLK 2
  • the pieces of data included in the third file FILE 3 may be sequentially programmed to the pages included in the third memory block BLK 3 .
  • LBA logical block addresses
  • GC garbage collection
  • FIG. 6 is a diagram illustrating examples of invalidated pages when map update occurs.
  • FIGS. 5 and 6 physical block addresses corresponding to first to 21st pages PAGE 1 to PAGE 21 included in the first to third blocks BLK 1 to BLK 3 of FIG. 5 , and logical block addresses corresponding to the respective physical block addresses are illustrated in FIG. 6 .
  • the first memory block BLK 1 includes first to seventh pages PAGE 1 to PAGE 7
  • the second memory block BLK 2 includes eighth to fourteenth pages PAGE 8 to PAGE 14
  • the third memory block BLK 3 includes fifteenth to 21st pages PAGE 15 to PAGE 21 .
  • the first to 21st logical block addresses LBA 1 to LBA 21 may be mapped to the first to 21-st physical block addresses PBA 1 to PBA 21 . That is, the first to 21-st physical block addresses PBA 1 to PBA 21 may be addresses corresponding to the first to 21-th pages PAGE 1 to PAGE 21 respectively.
  • consecutive program operations may be performed on pages corresponding to the first to seventh physical block addresses PBA 1 to PBA 7 , the eighth to fourteenth physical block addresses PBA 8 to PBA 14 , and the fifteenth to 21-st physical block addresses PBA 15 to PBA 21 .
  • map data may be updated through wear-leveling or garbage collection (GC), and one or more pages in a memory block may be invalidated.
  • GC wear-leveling or garbage collection
  • GC wear-leveling or garbage collection
  • mapping relationships between the logical block addresses (LBA) and the physical block addresses (PBA) are invalidated, the segments included in respective zones of the file system (e.g., file system 310 of FIG. 4 ) may also be invalidated.
  • LBA logical block addresses
  • FIG. 7 is a diagram illustrating an example of updating respective zones of a file system based on map update.
  • FIG. 7 illustrates an example of a process in which, after data of the third page PAGE 3 , data of the sixth page PAGE 6 , data of the ninth page PAGES, data of the tenth page PAGE 10 , data of the fifteenth page PAGE 15 , data of the seventh page PAGE 17 , and data of the eighteenth page PAGE 18 of the memory device shown in FIG. 6 have been invalidated, corresponding segments of respective zones included in the file system (e.g., file system 310 of FIG. 4 ) are invalidated.
  • the file system e.g., file system 310 of FIG. 4
  • map data is updated through wear-leveling or garbage collection (GC)
  • GC garbage collection
  • mapping relationships between logical block addresses (LBA) and physical block addresses (PBA) corresponding to these pages may be invalidated.
  • the third and sixth logical block addresses LBA 3 and LBA 6 assigned to the first zone ZONE 1 , the ninth and tenth logical block addresses LBA 9 and LBA 10 assigned to the second zone ZONE 2 , and the fifteenth, seventeenth, and eighteenth logical block addresses LBA 15 , LBA 17 , and LBA 18 assigned to the third zone ZONE 3 of the file system may be invalidated.
  • garbage collection may be performed by the file system.
  • garbage collection may not be performed by the file system when needed.
  • new logical block addresses may be re-assigned to segments of respective zones of the file system using slack space recycling (SSR).
  • SSR slack space recycling
  • FIG. 8 is a diagram illustrating an example in which logical block addresses are assigned to invalidated segments
  • FIGS. 7 and 8 after segments corresponding to third and sixth logical block addresses LBA 3 and LBA 6 assigned to the first zone ZONE 1 , ninth and tenth logical block addresses LBA 9 and LBA 10 assigned to the second zone ZONE 2 , and fifteenth, seventeenth, and eighteenth logical block addresses LBA 15 , LBA 17 , and LBA 18 assigned to the third zone ZONE 3 in FIG. 7 have been invalidated, assignment of new logical block addresses is illustrated in FIG. 8 .
  • garbage collection may not be performed on the file system.
  • the file system may assign new logical block addresses to respective zones using slack space recycling (SSR) instead of garbage collection (GC).
  • SSR slack space recycling
  • logical block addresses corresponding to pieces of data included in the third file FILE 3 may be assigned to the file system (e.g., file system 310 of FIG. 4 ).
  • the file system may be in a busy state, and thus garbage collection (GC) may not be performed.
  • garbage collection GC
  • an overwrite operation to a specific segment may be performed through slack space recycling (SSR).
  • segments corresponding to the third and sixth logical block addresses LBA 3 and LBA 6 assigned to the first zone ZONE 1 segments corresponding to the ninth and tenth logical block addresses LBA 9 and LBA 10 assigned to the second zone ZONE 2 , and segments corresponding to the fifteenth, seventeenth, and eighteenth logical block addresses LBA 15 , LBA 17 , and LBA 18 assigned to the third zone ZONE 3 have been invalidated
  • logical block addresses corresponding to pieces of data included in the fourth file FILE 4 may be assigned to these invalidated segments in ZONE 1 , ZONE 2 , and ZONE 3 .
  • the logical block addresses corresponding to pieces of data included in the fourth file FILE 4 are not consecutively assigned in a single zone, a random write operation rather than consecutive write operations may be performed. Because of the random write operation, the performance of the storage device may be deteriorated. That is, the mapping relationship between pieces of consecutive data and consecutive logical block addresses may not be formed by the file system (e.g., file system 310 of FIG. 4 ), and thus performance of the storage device may be deteriorated.
  • mapping relationships between consecutive logical block addresses and pieces of inconsecutive data are formed, additional performance loss may be caused in the formation of mapping relationships.
  • a data program method and a mapping data update method when logical block addresses are assigned to respective zones through slack space recycling (SSR) are provided.
  • FIG. 9 is a diagram illustrating an example of programming data after new logical block addresses are assigned to invalid segments.
  • FIGS. 6 , 8 , and 9 a process is illustrated in which, after the mapping relationships between logical block addresses (LBA) and physical block addresses (PBA) have been invalidated in FIG. 6 , logical block addresses corresponding to pieces of data included in the fourth file FILE 4 are assigned to respective invalidated segments in FIG. 8 , after which the pieces of data included in the fourth file FILE 4 are programmed to the memory blocks included in the memory device (e.g., memory device 100 of FIG. 4 ).
  • LBA logical block addresses
  • PBA physical block addresses
  • the memory device includes an additional memory block, for example, a fourth memory block BLK 4 , in addition to first to third memory blocks BLK 1 to BLK 3 .
  • the additional memory block may be a memory block of an over-provisioning (OP) area that is additionally included, besides the memory blocks in a user area.
  • OP over-provisioning
  • logical block addresses corresponding to pieces of data included in the fourth file FILE 4 may be assigned using slack space recycling (SSR) even before garbage collection (GC) is performed to secure free segments. More specifically, since new logical block addresses are assigned to invalidated segments, logical block addresses corresponding to pieces of data included in the fourth file FILE 4 may be assigned to the invalidated segments.
  • SSR slack space recycling
  • GC garbage collection
  • the flash translation layer may translate logical block addresses corresponding to the pieces of data included in the fourth file FILE 4 into physical block addresses.
  • the translated physical block addresses may be addresses corresponding to pages included in the fourth memory block BLK 4 .
  • the memory device may consecutively program pieces of data included in the fourth file FILE 4 to the pages corresponding to the physical block addresses. Thus, consecutive write operations may be performed.
  • the file system e.g., file system 310 of FIG. 4
  • logical block addresses corresponding to pieces of data included in the fourth file FILE 4 may be assigned to invalidated segments. Therefore, even if the memory device (e.g., memory device 100 of FIG. 4 ) is incapable of performing overwriting, consecutive write operations may be performed on the pages included in the fourth memory block BLK 4 .
  • FIG. 10 is a diagram illustrating an example of a process in which garbage collection is performed in a file system.
  • FIGS. 8 and 10 a process in which, after logical block addresses corresponding to pieces of data included in a fourth file FILE 4 have been assigned to respective segments as shown in FIG. 8 , consecutive logical block addresses are assigned to respective segments using garbage collection (GC) is illustrated in FIG. 10 .
  • GC garbage collection
  • garbage collection may be performed on the file system during an idle time so as to secure spare segments.
  • garbage collection may also be triggered even by an internal operation of the host (e.g., host 300 of FIG. 4 ).
  • the first to third zones ZONE 1 to ZONE 3 may be reset to X-th to Z-th zones ZONE_X to ZONE_Z.
  • consecutive logical block addresses may be assigned to the X-th to Z-th zones ZONE_X to ZONE_Z. That is, the logical block addresses corresponding to the pieces of data included in the first to fourth files FILE 1 to FILE 4 may be sequentially assigned again to the X-th to Z-th zones ZONE_X to ZONE_Z.
  • the invalidated segments in the first to third zones ZONE 1 to ZONE 3 may not be assigned in the X-th to Z-th zones ZONE_X to ZONE_Z.
  • the logical block addresses corresponding to pieces of data included in the first file FILE 1 may be sequentially assigned, as X 1 -th to X 5 -th logical block address LBAX 1 to LBAX 5 , to respective segments in the X-th zone ZONE_X.
  • the logical block addresses corresponding to pieces of data included in the second file FILE 2 may be sequentially assigned, as X 6 -th and X 7 -th logical block addresses LBAX 6 and LBAX 7 , to respective segments in the X-th zone ZONE_X, and may be sequentially assigned, as Y 1 -th to Y 3 -th logical block addresses LBAY 1 to LBAY 3 , to respective segments in the Y-th zone ZONE_Y.
  • the logical block addresses corresponding to pieces of data included in the third file FILE 3 may be sequentially assigned, as Y 4 -th to Y 7 -th logical block address LBAY 4 to LBAY 7 , to respective segments in the Y-th zone ZONE_Y.
  • the logical block addresses corresponding to pieces of data included in the fourth file FILE 4 may be sequentially assigned, as Z 1 -th to Z 7 -th logical block address LBAZ 1 to LBAZ 7 , to respective segments in the Z-th zone ZONE_Z.
  • garbage collection As described above, as garbage collection (GC) is performed on the file system (e.g., file system 310 of FIG. 4 ), logical block addresses corresponding to consecutive pieces of data included in the first to fourth files FILE 1 to FILE 4 may be sequentially assigned to segments of the X-th to Z-th zones ZONE_X to ZONE_Z. Therefore, the logical block addresses corresponding to pieces of data included in the fourth file system FILE 4 may be assigned to the segments of the Z-th zone ZONE_Z, which is a single zone.
  • GC garbage collection
  • the flash translation layer e.g., flash translation layer 210 of FIG. 4
  • LBA logical block address
  • PBA physical block address
  • FIG. 11 is a diagram illustrating mapping relationships that are changed after garbage collection has been performed on a file system.
  • mapping relationships that are changed after garbage collection (GC) has been performed on the file system (e.g., file system 310 of FIG. 4 ) in FIG. 10 are illustrated in FIG. 11 .
  • the flash translation layer when update information depending on the performance of garbage collection (GC) is received from the file system, the flash translation layer (e.g., flash translation layer 210 of FIG. 4 ) may update the mapping relationships between the logical block address (LBA) and the physical block address (PBA).
  • LBA logical block address
  • PBA physical block address
  • the X 1 -th to X 5 -th logical block addresses LBAX 1 to LBAX 5 corresponding to pieces of data included in the first FILE 1 may form mapping relationships with the first to fifth physical block addresses PBA 1 to PBA 5 respectively corresponding to pages included in the first memory block BLK 1 .
  • the X 6 -th and X 7 -th logical block addresses LBAX 6 and LBAX 7 and Y 1 -th to Y 3 -th logical block addresses LBAY 1 to LBAY 3 which correspond to pieces of data included in the second file FILE 2 , may form mapping relationships with the sixth and seventh physical block addresses PBA 6 and PBA 7 , which correspond to pages included in the first memory block BLK 1 , and eighth to tenth physical block addresses PBA 8 to PBA 10 , which correspond to pages included in the second memory block BLK 2 .
  • the Y 4 -th to Y 7 -th logical block addresses LBAY 4 to LBAY 7 corresponding to pieces of data included in the file FILE 3 may form mapping relationships with eleventh to fourteenth physical block addresses PBA 11 to PBA 14 corresponding to pages included in the second memory block BLK 2 .
  • the pieces of data included in the first to third files FILE 1 to FILE 3 are sequentially programmed to pages in the first and second memory blocks BLK 1 and BLK 2 , and thus the pieces of data in the pages in the first and second memory blocks BLK 1 and BLK 2 may be treated as consecutive data.
  • the third memory block BLK 3 may become a free block. Thereafter, new data may be programmed to pages included in the third memory block BLK 3 .
  • the flash translation layer e.g., flash translation layer 210 of FIG. 4
  • the Z 1 -th to Z 7 -th logical block addresses LBAZ 1 to LBAZ 7 corresponding to pieces of data included in the fourth file FILE 4 may form respective mapping relationships with physical block addresses corresponding to pages included in the fourth memory block BLK 4 .
  • mapping relationships may be updated without moving data of the pages included in the fourth memory block BLK 4 . That is, because only the mapping relationships are updated without moving data in the pages in the fourth memory block BLK 4 , pieces of data of the pages in the fourth memory block BLK 4 may be treated as consecutive pieces of data.
  • pieces of data programmed to the pages in the memory block without movement of the data may be treated as consecutive pieces of data.
  • FIG. 12 is a flowchart illustrating an example of the operation of an electronic system according to an embodiment.
  • a host or a file system (e.g., file system 310 of FIG. 4 ) of the host may assign logical block addresses corresponding to consecutive pieces of data to a plurality of zones of the file system.
  • the host may sequentially assign logical block addresses corresponding to the consecutive pieces of data so as to rapidly access the consecutive pieces of data.
  • a file system included in a host of the electronic system may include a plurality of zones, and each zone may include a set of segments.
  • the host or the file system may sequentially assign logical block addresses corresponding to consecutive pieces of data (e.g., data files) to the sets of segments of the plurality of zones.
  • assigning logical block addresses corresponding to consecutive pieces of data to the sets of segments of the plurality of zones is shown in FIG. 5 .
  • the memory controller may generate mapping relationships between logical block addresses and physical block addresses corresponding to consecutive pages in a plurality of memory blocks, for example, based on logical block addresses output from the host.
  • the logical block addresses output from the host may be logical block addresses corresponding to consecutive pieces of data.
  • the memory controller may output the physical addresses to the memory device. An example of generating mapping relationships between the logical block addresses and physical block addresses is shown in FIG. 5 .
  • the memory controller may, based on the mapping relationships, control the memory device to program the consecutive pieces of data to consecutive pages in the plurality of memory blocks that correspond to physical block addresses output from the memory controller.
  • An example of programming the consecutive pieces of data to the consecutive pages in the plurality of memory blocks is shown in FIGS. 5 and 6 .
  • the memory controller may update the mapping relationships, where the updated mapping relationships indicate one or more physical block addresses associated with invalid or outdated data. For example, when the map data is updated through wear-leveling or garbage collection (GC), the memory controller may update the mapping relationships between the logical block addresses and the physical block addresses based on the update information output from the memory device. An example of updating the mapping relationships is shown in FIG. 6 .
  • GC wear-leveling or garbage collection
  • the host may invalidate segments in a specific zone, among the plurality of zones included in the file system. That is, as the map data is updated, segments to which the corresponding logical block addresses are assigned may be invalidated based on the newly formed mapping relationships. One or more segments in the plurality of zones may be changed to the invalid segments.
  • An example of invalidating segments in the plurality of zones of the file system based on updated mapping relationships is shown in FIGS. 6 and 7 .
  • the host may assign new logical block addresses corresponding to consecutive pieces of a data file to the invalid segments, where each of the invalid segments may have been assigned a logical block address mapped to a physical block address of the one or more physical block addresses associated with invalid or outdated data.
  • garbage collection may not be performed on the file system for a long period of time.
  • no unassigned segments may be available, and thus new logical block addresses may not be assigned to unassigned segments.
  • new logical block addresses may overwrite the logical block addresses that have been assigned to the invalidated segments, through slack space recycling (SSR).
  • SSR slack space recycling
  • Assigning the new logical block addresses corresponding to the consecutive pieces of the data file to the invalid segments may cause the memory controller to map the new logical block addresses assigned to the invalid segments to physical block addresses that correspond to consecutive pages in a memory block of the plurality of memory blocks.
  • the memory controller may use the mapping to program the data file to consecutive pages in a memory block of the memory device, such as pages in a memory block in an over-provisioning area, as shown in, for example, FIG. 9 .
  • the host may perform garbage collection (GC), and may output a command, indicating that the mapping relationship has been updated through the garbage collection (GC), to the memory controller.
  • GC garbage collection
  • the host or the file system may autonomously perform garbage collection (GC), and zones in the host may be reset to new zones except for the invalidated segments through garbage collection (GC) as shown in, for example, FIG. 10 .
  • GC garbage collection
  • the host or the file system may assign the new logical block addresses that are assigned to the invalid segments to the set of segments in a zone of the plurality of zones. Thereafter, the host may output a command, indicating that the mapping relationships have been updated through garbage collection (GC), to the memory controller.
  • GC garbage collection
  • the memory controller may form new mapping relationships between logical block addresses and physical block addresses based on the command that has been received from the host and that indicates that the mapping relationships have been updated.
  • the physical block addresses may be addresses corresponding to pages included in the memory block of an over-provisioning (OP) area additionally included, in addition to the memory blocks in the user area.
  • OP over-provisioning
  • new logical block addresses corresponding to consecutive pieces of the data file may be mapped to physical block addresses corresponding to pages in the new memory block, and thus the consecutive pieces of the data file may be programmed to the pages in the new memory block (e.g., BLK 4 in FIG. 11 ).
  • the memory controller may, based on the updated mapping information, control the memory device to move the consecutive pieces of data to consecutive pages in the plurality of memory blocks as shown in, for example, FIG. 11 , where one or more memory blocks may be free blocks.
  • FIG. 13 is a flowchart illustrating an example of the operation of an electronic system according to an embodiment.
  • a host of the electronic system may enter an idle time.
  • the idle time may be a period during which no operation is performed.
  • garbage collection may be performed on a file system included in the host.
  • garbage collection may be performed on the file system so that spare segments are secured in the file system.
  • SSR slack space recycling
  • the memory controller may update the mapping relationships. For example, as garbage collection (GC) is performed on the file system, zones in the file system may be reset, and logical block addresses corresponding to consecutive pieces of data may be sequentially re-assigned to the segments in the reset zones. The memory controller may then update the mapping relationships between logical block addresses and physical block addresses, based on the logical block addresses sequentially re-assigned to the segments in the reset zones.
  • GC garbage collection
  • garbage collection may be performed on the storage device based on the updated mapping relationships. For example, because the logical block addresses are reassigned to respective zones of the file system, the memory controller may update the mapping relationships between logical block addresses and the physical block addresses. Furthermore, the memory device may be controlled by the memory controller to move the data based on the updated mapping relationships.
  • the logical block addresses assigned to the invalidated segments may be re-assigned to segments in one zone, only mapping relationships may be updated without movement of data in the memory device, and thus pieces of data corresponding to logical block addresses assigned to one zone may be treated as consecutive pieces of data.
  • FIG. 14 is a block diagram illustrating an example of a memory controller of the storage device of FIG. 1 .
  • a memory controller 1000 is coupled to a host and a memory device. In response to a request received from the host, the memory controller 1000 may access the memory device. For example, the memory controller 1000 may be configured to control write, read, erase, and background operations of the memory device. The memory controller 1000 may provide an interface between the memory device and the host. The memory controller 1000 may run firmware for controlling the memory device.
  • the memory controller 1000 may include a processor 1010 , a memory buffer 1020 , an error correction code (ECC) circuit 1030 , a host interface 1040 , a buffer control circuit 1050 , a memory interface 1060 , and a bus 1070 .
  • ECC error correction code
  • the bus 1070 may provide channels between components of the memory controller 1000 .
  • the processor 1010 may control the overall operation of the memory controller 1000 and may perform a logical operation.
  • the processor 1010 may communicate with an external host through the host interface 1040 and also communicate with the memory device through the memory interface 1060 . Further, the processor 1010 may communicate with the memory buffer 1020 through the buffer control circuit 1050 .
  • the processor 1010 may control the operation of the storage device by using the memory buffer 1020 as a working memory, a cache memory or a buffer memory.
  • the processor 1010 may perform the function of a flash translation layer (FTL).
  • the processor 1010 may translate a logical block address (LBA), provided by the host, into a physical block address (PBA) through the FTL.
  • LBA logical block address
  • PBA physical block address
  • the FTL may receive the LBA and translate the LBA into the PBA using a mapping table. Examples of an address mapping method performed through the FTL may include various methods according to a mapping unit. Representative address mapping methods include a page mapping method, a block mapping method, and a hybrid mapping method.
  • the processor 1010 may randomize data received from the host. For example, the processor 1010 may use a randomizing seed to randomize data received from the host.
  • the randomized data may be provided, as data to be stored, to the memory device and may be programmed in the memory cell array.
  • the processor 1010 may run software or firmware to perform the randomizing or derandomizing operation.
  • the processor 1010 may run software or firmware to perform randomizing and derandomizing operations.
  • the memory buffer 1020 may be used as a working memory, a cache memory, or a buffer memory of the processor 1010 .
  • the memory buffer 1020 may store codes and commands executed by the processor 1010 .
  • the memory buffer 1020 may store data that is processed by the processor 1010 .
  • the memory buffer 1020 may include a static RAM (SRAM) or a dynamic RAM (DRAM).
  • the ECC circuit 1030 may perform error correction.
  • the ECC circuit 1030 may perform error correction code (ECC) encoding based on data to be written to the memory device through the memory interface 1060 .
  • ECC-encoded data may be transferred to the memory device through the memory interface 1060 .
  • the ECC circuit 1030 may perform ECC decoding based on data received from the memory device through the memory interface 1060 .
  • the ECC circuit 1030 may be included as the component of the memory interface 1060 in the memory interface 1060 .
  • the host interface 1040 may communicate with the external host under the control of the processor 1010 .
  • the host interface 1040 may perform communication using at least one of various communication methods such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed Interchip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnection (PCI), PCI express (PCIe), Nonvolatile Memory express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMedia Card (MMC), embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM) communication methods.
  • USB Universal Serial Bus
  • SATA Serial AT Attachment
  • SAS Serial Attached SCSI
  • HSIC High Speed Interchip
  • SCSI Small Computer System Interface
  • PCI Peripheral Component Interconnection
  • PCIe PCI express
  • NVMe Nonvolatile Memory express
  • UFS Universal Flash Storage
  • the buffer control circuit 1050 may control the memory buffer 1020 under the control of the processor 1010 .
  • the memory interface 1060 may communicate with the memory device under the control of the processor 1010 .
  • the memory interface 1060 may transmit/receive commands, addresses, and data to/from the memory device through channels.
  • the memory controller 1000 may not include the memory buffer 1020 and the buffer control circuit 1050 .
  • the processor 1010 may control the operation of the memory controller 1000 using codes.
  • the processor 1010 may load codes from a nonvolatile memory device (e.g., ROM) provided in the memory controller 1000 .
  • the processor 1010 may load codes from the memory device through the memory interface 1060 .
  • the bus 1070 of the memory controller 1000 may be divided into a control bus and a data bus.
  • the data bus may be configured to transmit data in the memory controller 1000
  • the control bus may be configured to transmit control information such as commands or addresses in the memory controller 1000 .
  • the data bus and the control bus may be isolated from each other, and may neither interfere with each other nor influence each other.
  • the data bus may be coupled to the host interface 1040 , the buffer control circuit 1050 , the ECC circuit 1030 , and the memory interface 1060 .
  • the control bus may be coupled to the host interface 1040 , the processor 1010 , the buffer control circuit 1050 , the memory buffer 1020 , and the memory interface 1060 .
  • FIG. 15 illustrates an example of a memory card system in which the storage device according to an embodiment may be used.
  • a memory card system 2000 may include a memory controller 2100 , a memory device 2200 , and a connector 2300 .
  • the memory controller 2100 is coupled to the memory device 2200 .
  • the memory controller 2100 may access the memory device 2200 .
  • the memory controller 2100 may be control read, write, erase, and background operations of the memory device 2200 .
  • the memory controller 2100 may provide an interface between the memory device 2200 and a host.
  • the memory controller 2100 may run firmware for controlling the memory device 2200 .
  • the memory device 2200 may be implemented in the same way as the memory device (e.g., memory device 100 of FIG. 1 ) described above with reference to FIG. 1 .
  • the memory controller 2100 may include components, such as a RAM, a processor, a host interface, a memory interface, and an ECC circuit.
  • the memory controller 2100 may communicate with an external device through the connector 2300 .
  • the memory controller 2100 may communicate with an external device (e.g., a host) based on a specific communication protocol.
  • the memory controller 2100 may communicate with the external device through at least one of various communication protocols such as universal serial bus (USB), multi-media card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI-express (PCI-E), advanced technology attachment (ATA), serial-ATA (SATA), parallel-ATA (PATA), small computer system interface (SCSI), enhanced small disk interface (ESDI), integrated drive electronics (IDE), Firewire, universal flash storage (UFS), Wi-Fi, Bluetooth, and nonvolatile memory express (NVMe) protocols.
  • the connector 2300 may be defined by at least one of the above-described various communication protocols.
  • the memory device 2200 may be implemented as any of various nonvolatile memory devices, such as an Electrically Erasable and Programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a Phase-change RAM (PRAM), a Resistive RAM (ReRAM), a Ferroelectric RAM (FRAM), a Spin Transfer Torque Magnetic RAM (STT-MRAM).
  • EEPROM Electrically Erasable and Programmable ROM
  • NAND flash memory a NAND flash memory
  • NOR flash memory NOR flash memory
  • PRAM Phase-change RAM
  • ReRAM Resistive RAM
  • FRAM Ferroelectric RAM
  • STT-MRAM Spin Transfer Torque Magnetic RAM
  • the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to configure a memory card.
  • the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to configure a memory card such as a PC card (personal computer memory card international association: PCMCIA), a compact flash (CF) card, a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro or eMMC), a SD card (SD, miniSD, microSD, or SDHC), or a universal flash storage (UFS).
  • PC card personal computer memory card international association: PCMCIA
  • CF compact flash
  • SM or SMC smart media card
  • MMC multimedia card
  • RS-MMC multimedia card
  • MMCmicro or eMMC multimedia card
  • SD card Secure Digital, Secure Digital High Capacity
  • SDHC Secure Digital High Capacity
  • UFS universal flash storage
  • FIG. 16 is a block diagram of an example of a solid state drive (SSD) system in which a storage device according to an embodiment may be used.
  • SSD solid state drive
  • an SSD system 3000 may include a host 3100 and an SSD 3200 .
  • the SSD 3200 may exchange signals SIG with the host 3100 through a signal connector 3001 and may receive power PWR through a power connector 3002 .
  • the SSD 3200 may include an SSD controller 3210 , a plurality of nonvolatile memories 3221 to 322 n , an auxiliary power supply 3230 , and a buffer memory 3240 .
  • the SSD controller 3210 may perform the function of the memory controller (e.g., memory controller 200 of FIG. 1 ) described above with reference to FIG. 1 .
  • the SSD controller 3210 may control the plurality of nonvolatile memories 3221 to 322 n in response to the signals SIG received from the host 3100 .
  • the signals SIG may be signals based on the interfaces of the host 3100 and the SSD 3200 .
  • the signals SIG may be signals defined by at least one of various interfaces such as universal serial bus (USB), multi-media card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI-express (PCI-E), advanced technology attachment (ATA), serial-ATA (SATA), parallel-ATA (PATA), small computer system interface (SCSI), enhanced small disk interface (ESDI), integrated drive electronics (IDE), Firewire, universal flash storage (UFS), Wi-Fi, Bluetooth, and nonvolatile memory express (NVMe) interfaces.
  • USB universal serial bus
  • MMC multi-media card
  • eMMC embedded MMC
  • PCI peripheral component interconnection
  • PCI-express PCI-express
  • ATA advanced technology attachment
  • SATA serial-ATA
  • PATA parallel-ATA
  • SCSI small computer system interface
  • ESDI enhanced small disk interface
  • IDE integrated drive electronics
  • Firewire universal flash storage
  • UFS universal flash storage
  • Wi-Fi Wi-Fi
  • Bluetooth wireless local flash storage
  • the auxiliary power supply 3230 may be coupled to the host 3100 through the power connector 3002 .
  • the auxiliary power supply 3230 may be supplied with power PWR from the host 3100 and may be charged.
  • the auxiliary power supply 3230 may supply the power of the SSD 3200 when the supply of power from the host 3100 is not smoothly performed.
  • the auxiliary power supply 3230 may be positioned inside the SSD 3200 or positioned outside the SSD 3200 .
  • the auxiliary power supply 3230 may be disposed in a main board and may supply auxiliary power to the SSD 3200 .
  • the buffer memory 3240 functions as a buffer memory of the SSD 3200 .
  • the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of nonvolatile memories 3221 to 322 n or may temporarily store metadata (e.g., mapping tables) of the nonvolatile memories 3221 to 322 n .
  • the buffer memory 3240 may include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM or nonvolatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.
  • FIG. 17 is a block diagram illustrating an example of a user system in which the storage device according to an embodiment may be used.
  • a user system 4000 may include an application processor 4100 , a memory module 4200 , a network module 4300 , a storage module 4400 , and a user interface 4500 .
  • the application processor 4100 may run components included in the user system 4000 , an Operating System (OS) or a user program.
  • the application processor 4100 may include controllers, interfaces, graphic engines, etc. for controlling the components included in the user system 4000 .
  • the application processor 4100 may be provided as a system-on-chip (SoC).
  • the memory module 4200 may function as a main memory, a working memory, a buffer memory or a cache memory of the user system 4000 .
  • the memory module 4200 may include volatile RAMs such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or nonvolatile RAMs such as PRAM, ReRAM, MRAM, and FRAM.
  • the application processor 4100 and the memory module 4200 may be packaged based on package-on-package (POP) and may then be provided as a single semiconductor package.
  • POP package-on-package
  • the network module 4300 may communicate with external devices.
  • the network module 4300 may support wireless communication, such as Code Division Multiple Access (CDMA), Global System for Mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, or Wi-Fi communication.
  • CDMA Code Division Multiple Access
  • GSM Global System for Mobile communication
  • WCDMA wideband CDMA
  • TDMA Time Division Multiple Access
  • LTE Long Term Evolution
  • WiMAX Wireless Fidelity
  • WLAN Wireless Local Area Network
  • UWB Wireless Fidelity
  • Bluetooth Wireless Fidelity
  • the storage module 4400 may store data.
  • the storage module 4400 may store data received from the application processor 4100 .
  • the storage module 4400 may transmit the data stored in the storage module 4400 to the application processor 4100 .
  • the storage module 4400 may be implemented as a nonvolatile semiconductor memory device, such as a Phase-change RAM (PRAM), a Magnetic RAM (MRAM), a Resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, or a NAND flash memory having a three-dimensional (3D) structure.
  • the storage module 4400 may be provided as a removable storage medium (i.e., removable drive), such as a memory card or an external drive of the user system 4000 .
  • the storage module 4400 may include a plurality of nonvolatile memory devices, each of which may be operated in the same way as the memory device described above with reference to FIGS. 2 and 3 .
  • the storage module 4400 may be operated in the same way as the storage device 50 described above with reference to FIG. 1 .
  • the user interface 4500 may include interfaces which input data or instructions to the application processor 4100 or output data to an external device.
  • the user interface 4500 may include user input interfaces such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, and a piezoelectric device.
  • the user interface 4500 may further include user output interfaces such as a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display device, an Active Matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • AMOLED Active Matrix OLED
  • F2FS flash friendly file system
  • an overwrite operation is performed on an invalid segment, and logical block addresses are translated into addresses corresponding to consecutive data by moving logical block addresses to one area through garbage collection during an idle time, thus improving the performance of an electronic system including a host, a memory controller, and a memory device.
  • F2FS flash friendly file system
US17/304,076 2020-12-02 2021-06-14 Electronic system including host, memory controller and memory device and method of operating the same Active US11543986B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020200166882A KR20220077691A (ko) 2020-12-02 2020-12-02 호스트, 메모리 컨트롤러 및 메모리 장치를 포함하는 전자 시스템 및 이의 동작 방법
KR10-2020-0166882 2020-12-02

Publications (2)

Publication Number Publication Date
US20220171532A1 US20220171532A1 (en) 2022-06-02
US11543986B2 true US11543986B2 (en) 2023-01-03

Family

ID=81752619

Family Applications (1)

Application Number Title Priority Date Filing Date
US17/304,076 Active US11543986B2 (en) 2020-12-02 2021-06-14 Electronic system including host, memory controller and memory device and method of operating the same

Country Status (3)

Country Link
US (1) US11543986B2 (ko)
KR (1) KR20220077691A (ko)
CN (1) CN114579475A (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11733895B2 (en) * 2021-03-31 2023-08-22 Silicon Motion, Inc. Control method of flash memory controller and associated flash memory controller and storage device
US11748011B2 (en) * 2021-03-31 2023-09-05 Silicon Motion, Inc. Control method of flash memory controller and associated flash memory controller and storage device
US20230222055A1 (en) * 2022-01-11 2023-07-13 Western Digital Technologies, Inc. Log File System (LFS) Invalidation Command and Operational Mode

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140177085A1 (en) * 2012-12-26 2014-06-26 Kabushiki Kaisha Toshiba Disk storage apparatus and method for shingled magnetic recording
KR101447188B1 (ko) 2007-07-31 2014-10-08 삼성전자주식회사 플래시 메모리에 최적화된 입출력 제어 방법 및 장치
US20160179386A1 (en) * 2014-12-17 2016-06-23 Violin Memory, Inc. Adaptive garbage collection
KR102050732B1 (ko) 2012-09-28 2019-12-02 삼성전자 주식회사 컴퓨팅 시스템 및 컴퓨팅 시스템의 데이터 관리 방법
US11061814B1 (en) * 2013-03-15 2021-07-13 EMC IP Holding Company LLC Managing data storage caching and tiering
US20220206689A1 (en) * 2020-12-31 2022-06-30 Micron Technology, Inc. Access of a memory system based on fragmentation

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101447188B1 (ko) 2007-07-31 2014-10-08 삼성전자주식회사 플래시 메모리에 최적화된 입출력 제어 방법 및 장치
KR102050732B1 (ko) 2012-09-28 2019-12-02 삼성전자 주식회사 컴퓨팅 시스템 및 컴퓨팅 시스템의 데이터 관리 방법
US20140177085A1 (en) * 2012-12-26 2014-06-26 Kabushiki Kaisha Toshiba Disk storage apparatus and method for shingled magnetic recording
US11061814B1 (en) * 2013-03-15 2021-07-13 EMC IP Holding Company LLC Managing data storage caching and tiering
US20160179386A1 (en) * 2014-12-17 2016-06-23 Violin Memory, Inc. Adaptive garbage collection
US20220206689A1 (en) * 2020-12-31 2022-06-30 Micron Technology, Inc. Access of a memory system based on fragmentation

Also Published As

Publication number Publication date
CN114579475A (zh) 2022-06-03
US20220171532A1 (en) 2022-06-02
KR20220077691A (ko) 2022-06-09

Similar Documents

Publication Publication Date Title
US11194736B2 (en) Memory controller having improved map data access performance and method of operating the same
US11036632B2 (en) Memory controller and operating method thereof
US11543986B2 (en) Electronic system including host, memory controller and memory device and method of operating the same
US11307803B2 (en) Storage device for suspending program operation and performing read operation and operating method thereof
US20210157525A1 (en) Memory controller and operating method thereof
US11449417B2 (en) Memory controller performing host-aware performance booster mode and method of operating the same
CN111444115B (zh) 存储装置及其操作方法
US11954021B2 (en) Storage device and operating method thereof
KR20220113159A (ko) 저장 장치 및 그 동작 방법
KR20210113905A (ko) 메모리 컨트롤러 및 그 동작 방법
KR20210090439A (ko) 메모리 컨트롤러 및 그 동작 방법
US20200233812A1 (en) Storage device and method of operating the same
US10996881B2 (en) Storage device and method of operating the same
US11960733B2 (en) Memory controller and method of operating the same
US11593023B2 (en) Memory controller and method of operating the same
US11836370B2 (en) Storage device and operating method thereof
US11636899B2 (en) Memory device and method of operating the same
KR102626058B1 (ko) 메모리 컨트롤러 및 그 동작 방법
US11500768B2 (en) Storage device performing garbage collection and method of operating the same
US11841795B2 (en) Storage device for setting a flag in a mapping table according to a sequence number and operating method thereof
US11294590B2 (en) Storage device with fail page replacement capability and operating method thereof
US11868658B2 (en) Memory controller including first processor for generating commands and second processor for generating logging information and method of operating the memory controller
US20240094945A1 (en) Memory controller and memory system including the same
US20220269610A1 (en) Memory controller and method of operating the same
KR20220170664A (ko) 호스트 장치, 저장 장치 및 그 동작 방법

Legal Events

Date Code Title Description
AS Assignment

Owner name: SK HYNIX INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KANG, HYE MI;REEL/FRAME:056534/0901

Effective date: 20210609

FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: AWAITING TC RESP, ISSUE FEE PAYMENT VERIFIED

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE