US11501696B2 - Pixel driving device and method for driving pixel - Google Patents

Pixel driving device and method for driving pixel Download PDF

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Publication number
US11501696B2
US11501696B2 US17/320,413 US202117320413A US11501696B2 US 11501696 B2 US11501696 B2 US 11501696B2 US 202117320413 A US202117320413 A US 202117320413A US 11501696 B2 US11501696 B2 US 11501696B2
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transistor
capacitor
driving
voltage
stage
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US20220036809A1 (en
Inventor
Chia-En Wu
Ming-Hsien Lee
Wei-Chia Chiu
Kuan-Yu Chen
Chia-Yen Lin
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AU Optronics Corp
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AU Optronics Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/064—Adjustment of display parameters for control of overall brightness by time modulation of the brightness of the illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present disclosure relates to display device and method. More particularly, the present disclosure relates to a pixel driving device and a method for driving pixel.
  • Micro light emitting device features a high luminance under a high driving current. Therefore, in a conventional structure of a driving circuit, an internal threshold voltage of driving transistor will generate a difference under different situations. Under a higher driving current, an impedance of a driving circuit will generate a difference in a power supply voltage. An internal threshold voltage of driving transistor and an impedance of a driving circuit both affect a driving current so as to generate a difference in luminance of micro light emitting device.
  • the pixel driving device includes a capacitor, a reset circuit, a compensation circuit, a driving transistor and a first transistor.
  • the capacitor includes a first end and a second end.
  • the reset circuit is coupled to the first end and the second end of the capacitor.
  • the compensation circuit is coupled to the first end and the second end of the capacitor.
  • the driving transistor includes a first end, a second end and a control end.
  • the control end of the driving transistor is coupled to the first end of the capacitor.
  • the first transistor includes a first end, a second end, and a control end. Each of The first end and the second end of the first transistor is coupled between the second end of the driving transistor and the second end of the capacitor.
  • the reset circuit is configured to reset the first end of the capacitor to a power supply voltage and reset the second end of the capacitor to a reference voltage according to a first sweep signal respectively in a first stage.
  • the compensation circuit is configured to write a data voltage into the first end of the capacitor via the driving transistor so that a voltage of the first end of the capacitor is at a first voltage and the second end of the capacitor is maintained at the reference voltage according to a second sweep signal in a second stage.
  • the first transistor is configured to turn on so as to generate a driving voltage difference between the first voltage of the first end of the capacitor and the reference voltage of the second end of the capacitor according to a control signal in a third stage.
  • the driving transistor is configured to output a driving current to a luminous element according to the driving voltage difference in the third stage.
  • the method for driving pixel is adapted for a pixel driving device.
  • the pixel driving device includes a capacitor, a driving transistor and a first transistor.
  • a control end of the driving transistor is coupled to a first end of the capacitor.
  • Each of a first end and a second end of the first transistor is coupled to a second end of the capacitor and a second end of the driving transistor respectively.
  • the method for driving pixel includes: resetting the first end of the capacitor to a power supply voltage and resetting the second end of the capacitor to a reference voltage according to a first sweep signal respectively in a first stage; writing a data voltage into the first end of the capacitor so that a voltage of the first end of the capacitor is at a first voltage and the second end of the capacitor is maintained at the reference voltage via the driving transistor according to a second sweep signal in a second stage; turning on to generate a driving voltage difference between the first voltage of the first end of the capacitor and the reference voltage of the second end of the capacitor according to a control signal in a third stage; and outputting a driving current to a luminous element according to the driving voltage difference in the third stage.
  • FIG. 1 depicts a schematic diagram of a pixel driving device according to some embodiments of the present disclosure
  • FIG. 2 depicts a timing diagram of signals of a method for driving pixel according to some embodiments of the present disclosure
  • FIG. 3 depicts a flow diagram of a method for driving pixel according to some embodiments of the present disclosure
  • FIG. 4 depicts a state diagram of a pixel driving device according to some embodiments of the present disclosure
  • FIG. 5 depicts a state diagram of a pixel driving device according to some embodiments of the present disclosure
  • FIG. 6 depicts a state diagram of a pixel driving device according to some embodiments of the present disclosure.
  • FIG. 7 depicts a state diagram of a pixel driving device according to some embodiments of the present disclosure.
  • FIG. 1 depicts a schematic diagram of a pixel driving device according to some embodiments of the present disclosure.
  • a pixel driving device 100 includes a reset circuit 110 , a compensation circuit 120 , a capacitor C 1 , a driving transistor DM 1 , a first transistor M 1 , and a luminous element L.
  • a display device (not shown in figure) includes a plurality of pixels. Each of the pixels includes at least one pixel driving device 100 .
  • the pixel driving device 100 further includes a seventh transistor M 7 and an eighth transistor M 8 .
  • the luminous element L includes one of a micro Light Emitting Diode ( ⁇ LED) and an organic light emitting diode (OLED).
  • ⁇ LED micro Light Emitting Diode
  • OLED organic light emitting diode
  • the capacitor C 1 includes a first end N 1 and a second end N 2 .
  • the reset circuit 110 is coupled to the first end N 1 and the second end N 2 of the capacitor C 1 .
  • the compensation circuit 120 is coupled to the first end N 1 and the second end N 2 of the capacitor C 1 .
  • the driving transistor DM 1 includes a first end, a second end, and a control end. The control end of the driving transistor is coupled to the first end N 1 of the capacitor C 1 .
  • the first transistor M 1 includes a first end, a second end, and a control end. Each of the first end and the second end of the first transistor M 1 is coupled between the second end of the driving transistor DM 1 and the second end N 2 of the capacitor C 1 .
  • FIG. 2 depicts a timing diagram of signals of a method for driving pixel according to some embodiments of the present disclosure.
  • the reset circuit 110 is configured to reset the first end N 1 of the capacitor C 1 to a power supply voltage VDD and reset the second end N 2 of the capacitor C 1 to a reference voltage Vref respectively according to a first sweep signal S 1 in a first stage T 1 .
  • the compensation circuit 120 is configured to write a data voltage Vdata into the first end N 1 of the capacitor C 1 via the driving transistor DM 1 according to a second sweep signal S 2 in a second stageT 2 so that a voltage of the first end N 1 capacitor C 1 is at a first voltage and the second end of the capacitor C 1 is maintained at the reference voltage Vref.
  • the first transistor M 1 is configured to turn on according to a control signal EM so as to generate a driving voltage difference between the first voltage of the first end N 1 of the capacitor C 1 and the reference voltage Vref of the second end N 2 of the capacitor C 1 in a third stage T 3 .
  • the driving transistor DM 1 is configured to output a driving current to the luminous element L according to the driving voltage difference in the third stage T 3 .
  • the reset circuit 110 includes a second transistor M 2 and a third transistor M 3 .
  • the second transistor M 2 includes a first end, a second end, and a control end.
  • the first end of the second transistor M 2 is electrically connected to the first end N 1 of the capacitor C 1 .
  • the second end of the second transistor M 2 is configured to receive the power supply voltage VDD.
  • the control end of the second transistor M 2 is configured to reset the first end N 1 of the capacitor C 1 to the power supply voltage VDD according to the first sweep signal S 1 in the first stage T 1 .
  • the third transistor M 3 includes a first end, a second end, and a control end.
  • the first end of the third transistor M 3 is electrically connected to the second end N 2 of the capacitor C 1 .
  • the second end of the third transistor M 3 is configured to receive the reference voltage Vref.
  • the control end of the third transistor M 3 is configured to reset the second end N 2 of the capacitor C 1 to the reference voltage Vref according to the first sweep signal S 1 in the first stage T 1 .
  • the compensation circuit 120 includes a fourth transistor M 4 , a fifth transistor M 5 , and a sixth transistor M 6 .
  • the fourth transistor M 4 includes a first end, a second end, and a control end. The first end of the fourth transistor M 4 is electrically connected to the first end of the driving transistor DM 1 . The second end of the fourth transistor M 4 is electrically connected to the first end N 1 of the capacitor C 1 .
  • the control end of the fourth transistor M 4 is configured to write the data voltage Vdata into the first end N 1 of the capacitor C 1 via driving transistor DM 1 according to the second sweep signal S 2 in the second stageT 2 .
  • the fifth transistor M 5 includes a first end, a second end, and a control end.
  • the first end of the fifth transistor M 5 is electrically connected to the second end N 2 of the capacitor C 1 .
  • the second end of the fifth transistor M 5 is configured to receive the reference voltage Vref.
  • the control end of the fifth transistor M 5 is configured to maintain the second end N 2 of the capacitor C 1 at the reference voltage Vref according to the second sweep signal S 2 in the second stage T 2 .
  • the sixth transistor M 6 includes a first end, a second end, and a control end.
  • the first end of the sixth transistor M 6 is electrically connected to the second end of the driving transistor DM 1 .
  • the second end of the sixth transistor M 6 is configured to receive the data voltage Vdata.
  • the control end of sixth transistor M 6 is configured to write the data voltage Vdata into the first end N 1 of the capacitor C 1 via the driving transistor DM 1 according to the second sweep signal S 2 in the second stage T 2 .
  • the luminous element L includes a first end and a second end.
  • the first end of the luminous element L is electrically connected to the second end of the driving transistor DM 1 .
  • the second end of the luminous element L is configured to receive a power supply voltage VSS.
  • the second end of the luminous element L is electrically connected to the first end of the driving transistor DM 1
  • the first end of the luminous element L is configured to receive the power supply voltage VDD via driving transistor DM 1 .
  • each of the seventh transistor M 7 and the eighth transistor M 8 is configured to turn on so as to output the driving current to the luminous element L according to the control signal EM in the third stage T 3 .
  • the seventh transistor M 7 includes a first end, a second end, and a control end. The first end of the seventh transistor M 7 is configured to receive the power supply voltage VDD. The second end of the seventh transistor M 7 is electrically connected to the first end of the driving transistor DM 1 . The control end of the seventh transistor M 7 is configured to turn on so as to output the driving current to the luminous element L according to the control signal EM in the third stage T 3 .
  • the eighth transistor M 8 includes a first end, a second end, and a control end.
  • the first end of the eighth transistor M 8 is electrically connected to the second end of the driving transistor DM 1 .
  • the second end of the eighth transistor M 8 is electrically connected to the luminous element L.
  • the control end of the eighth transistor M 8 is configured to turn on so as to output the driving current to the luminous element L according to the control signal EM in the third stage T 3 .
  • control signal EM includes a pulse width modulation signal.
  • a duty cycle of the pulse width modulation signal is adjustable so as to control the luminance of the luminous element L.
  • FIG. 3 depicts a flow diagram of a method for driving pixel according to some embodiments of the present disclosure.
  • the method for driving pixel 300 can be implemented by the pixel driving device 100 .
  • FIG. 4 to FIG. 7 depict a state diagram of a pixel driving device according to some embodiments of the present disclosure, correspond to the pixel driving device 100 shown in Fig. 1 .
  • the step 310 is performed to reset the first end of the capacitor to a power supply voltage and reset the second end of the capacitor to a reference voltage according to a first sweep signal respectively in a first stage.
  • the first sweep signal S 1 is at a high level, and the reset circuit 110 turns on according to the first sweep signal S 1 .
  • the second transistor M 2 of the reset circuit 110 turns on according to the first sweep signal S 1 , and the second end of the second transistor M 2 is configured to receive and transmit the power supply voltage VDD to the first end N 1 of the capacitor C 1 so as to reset the first end N 1 of the capacitor C 1 at the power supply voltage VDD.
  • a potential of the first end N 1 of the capacitor C 1 is at the power supply voltage VDD.
  • the third transistor M 3 of the reset circuit 110 turns on according to the first sweep signal S 1 , and the second end of the third transistor M 3 is configured to receive and transmit the reference voltage Vref to the second end N 2 of the capacitor C 1 so as to reset the second end N 2 of capacitor C 1 at the reference voltage Vref. At this time, a potential of the second end N 2 of the capacitor C 1 is at the reference voltage Vref.
  • the rest signals are at low level, therefore, the rest circuits of the pixel driving device 100 are turned off.
  • the step 320 is performed to write a data voltage into the first end of the capacitor so that a voltage of the first end of the capacitor is at a first voltage, and the second end of the capacitor is maintained at the reference voltage via the driving transistor according to a second sweep signal in a second stage.
  • the compensation circuit 120 is turned on according to the second sweep signal S 2 .
  • the fifth transistor M 5 of the compensation circuit 120 is turned on according to the second sweep signal S 2 , the second end of the fifth transistor M 5 is configured to receive and transmit the reference voltage Vref. Because the rest signals are at low signal, the reset circuit 110 and the first transistor M 1 are turned off, and do not affect the fifth transistor M 5 .
  • the fifth transistor M 5 can maintain the second end N 2 of the capacitor C 1 at a potential which is rest in the first stage T 1 . At this time, a potential of the second end N 2 of the capacitor C 1 is still at the reference voltage Vref.
  • the fourth transistor M 4 and the sixth transistor M 6 of the compensation circuit 120 are turned on according to the second sweep signal S 2 .
  • the driving transistor DM 1 is turned on according to a potential of the first end N 1 of the capacitor C 1 .
  • the driving transistor DM 1 , the fourth transistor M 4 , and the sixth transistor M 6 form a path to generate a compensation current Ic.
  • the second end of the sixth transistor M 6 is configured to receive the data voltage Vdata, and compensate the first end N 1 of the capacitor C 1 at the first voltage via the driving transistor DM 1 .
  • a potential of the first end N 1 of the capacitor C 1 is at the first voltage, and the first voltage is the data voltage Vdata plus a threshold voltage Vth of the driving transistor DM 1 .
  • the step 330 is performed to turn on the first transistor to generate a driving voltage difference between the first voltage of the first end of the capacitor and the reference voltage of the second end of the capacitor according to a control signal in a third stage.
  • the control signal EM is at high level
  • the first transistor M 1 , the seventh transistor M 7 , and the eighth transistor M 8 are turned on according to the control signal EM.
  • a potential which the first transistor M 1 is coupled to the second end N 2 of the capacitor C 1 is changed from the reference voltage Vref to a potential Vled the luminous element L, and the first voltage of the first end N 1 of the capacitor C 1 responds to a potential of the second end N 2 of the capacitor C 1 .
  • a potential of the first end N 1 of the capacitor C 1 rises from the first voltage (Vdata+Vth) to (Vdata+Vth ⁇ Vref+Vled).
  • the step 340 is performed to output a driving current to a luminous element according to the driving voltage difference in the third stage.
  • the driving transistor DM 1 outputs the driving current Id to the luminous element L according to the driving voltage difference between the control end and the second end of the driving transistor DM 1 .
  • the driving voltage difference between the control end and the second end of the driving transistor DM 1 is equal to a voltage difference between the first end N 1 of the capacitor C 1 and the second end N 2 of the capacitor C 1 .
  • Id is a driving current
  • VGS is a voltage difference between the control end of the driving transistor DM 1 and the second end of the driving transistor DM 1
  • Vth is a threshold voltage.
  • a potential of the control end of the driving transistor DM 1 is at (Vdata+Vth ⁇ Vref+Vled)
  • a potential of the second end of the driving transistor DM 1 is at Vled.
  • the pixel driving device of the present disclosure cooperates with a suitable method for driving pixel so as to eliminate the threshold voltage Vth of the driving transistor DM 1 .
  • the driving current Id depends on a difference between the data voltage Vdata and the reference voltage Vref.
  • the driving current Id is independent of the power supply voltage VDD/VSS, and is unaffected under the power supply voltage VDD/VSS.
  • each of the first sweep signal S 1 , the second sweep signal S 2 and the control signal EM is at low level, and all of transistors of the pixel driving device 100 are turned off to be reset.
  • the present disclosure provides a pixel driving device and a method for driving pixel so as to improve a difference of a threshold voltage of a transistor and solve a problem that a driving current is affected by a power supply voltage.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
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