US11373698B2 - Semiconductor device, semiconductor system including the same and operating method for a semiconductor system - Google Patents

Semiconductor device, semiconductor system including the same and operating method for a semiconductor system Download PDF

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US11373698B2
US11373698B2 US15/987,586 US201815987586A US11373698B2 US 11373698 B2 US11373698 B2 US 11373698B2 US 201815987586 A US201815987586 A US 201815987586A US 11373698 B2 US11373698 B2 US 11373698B2
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signal
clock signal
refresh
memory
speed
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US20180342285A1 (en
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Woongrae Kim
Tae-Yong Lee
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SK Hynix Inc
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SK Hynix Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0409—Online test

Definitions

  • Various embodiments of the present disclosure relate to a semiconductor design technique, and more particularly, to a semiconductor device, a semiconductor system including the semiconductor device, and an operating method of the semiconductor system.
  • a semiconductor system has been developed to support an operation in both a high-speed mode and a low-speed mode.
  • the high-speed mode and the low-speed mode may relate to a clock signal. That is, the semiconductor system may operate in synchronization with the clock signal and act in the high-speed mode or the low-speed mode determined according to the speed, i.e., a frequency, of the clock signal. Further, the semiconductor system may operate in synchronization with a rising edge and a falling edge of the clock signal in the high-speed mode or the low-speed mode.
  • Various embodiments of the present disclosure are directed to a semiconductor device that may control a refresh cycle in response to the speed (i.e., a frequency) of a clock signal, a semiconductor system including the semiconductor device, and an operating method of the semiconductor system.
  • a semiconductor device may include: a monitoring circuit suitable for generating a monitoring signal indicating whether a speed of a memory clock signal is changed based on a speed information signal representing speed information of the memory clock signal; a cycle control circuit suitable for generating a refresh cycle control signal for controlling a refresh cycle based on a system clock signal, the memory clock signal, the monitoring signal and a refresh flag signal; and a control circuit suitable for generating the memory clock signal and the refresh flag signal based on the speed information signal, the system clock signal and the refresh cycle control signal.
  • a semiconductor system may include: a control device suitable for generating a memory clock signal having a predetermined speed and generating a memory command signal at a moment when a refresh cycle which is controlled corresponding to a speed of the memory clock signal is considered, based on a system clock signal and a system command signal; and a memory device suitable for performing a predetermined operation, determined based on the memory command signal, with an operational speed corresponding to the memory clock signal.
  • an operating method of a semiconductor system may include: monitoring whether a speed of a memory clock is changed during a refresh operation; and generating a predetermined command signal according to a monitoring result, wherein: when the speed of the memory clock corresponds to a reference speed, the predetermined command signal is generated after a first refresh cycle from a moment when a refresh command signal for controlling the refresh operation is generated; and when the speed of the memory clock is higher than the reference speed, the predetermined command signal is generated after a second refresh cycle that is longer than a first refresh cycle from another moment when the refresh command signal is generated.
  • FIG. 1 is a block diagram illustrating a semiconductor system in accordance with an embodiment of the present disclosure
  • FIG. 2 is a block diagram illustrating a control device shown in FIG. 1 ;
  • FIG. 3 is a block diagram illustrating a cycle control circuit shown in FIG. 2 ;
  • FIG. 4 is a block diagram illustrating a first calculation block shown in FIG. 3 ;
  • FIG. 5 is a block diagram illustrating a second calculation block shown in FIG. 3 ;
  • FIG. 6 is a timing diagram illustrating an operation of a semiconductor system shown in FIG. 1 .
  • FIG. 7 is a table where command signals are combined to determine which operation is performed.
  • the semiconductor system may include a control device 100 and a memory device 200 .
  • the control device 100 may generate a memory clock signal CLK_MEM and a plurality of command signals CS, CA ⁇ 0:6> in order for controlling the memory device 200 based at least on a system clock signal CLK_SOC and a system command signal CMD_SOC. For example, the control device 100 may divide or multiply a frequency of the system clock signal CLK_SOC to generate the memory clock signal CLK_MEM based on the system command signal CMD_SOC.
  • control device 100 may generate the command signals CS, CA ⁇ 0:6>, used for controlling at least one of a refresh operation, an active operation, a precharge operation, a write operation and a read operation of the memory device 200 , based on the memory clock signal CLK_MEM and the command signal CMD_SOC. Particularly, the control device 100 may take a refresh cycle into account to generate the command signals CS, CA ⁇ 0:6>.
  • the refresh cycle may be determined according to a speed, i.e., a frequency of the memory clock signal CLK_MEM.
  • the system command signal CMD_SOC may include a speed information signal which represents speed information, i.e., frequency information of the memory clock signal CLK_MEM.
  • the system clock signal CLK_SOC and the system command signal CMD_SOC may be provided from a host device (not illustrated in FIG. 1 ).
  • the control device 100 may include a controller such as a central processing unit (CPU).
  • the memory device 200 may perform a predetermined operation based on the memory clock signal CLK_MEM and the command signals CS, CA ⁇ 0:6>.
  • the memory device 200 may include a DRAM that performs the refresh operation, the active operation, the precharge operation, the write operation, the read operation, and so on.
  • FIG. 2 is a block diagram illustrating the control device 100 shown in FIG. 1 .
  • the control device 100 may include a monitoring circuit 110 , a cycle control circuit 120 , and a control circuit 130 .
  • the monitoring circuit 110 may generate a monitoring signal EN indicating a speed change (or frequency change) of the memory clock signal CLK_MEM, which may be recognized based on the system command signal CMD_SOC. For example, the monitoring circuit 110 may activate the monitoring signal EN when the current speed of the memory clock signal CLK_MEM is higher than a previous speed.
  • the cycle control circuit 120 may generate a refresh cycle control signal tRFC_V having a period, a section or a cycle corresponding to the refresh cycle, based at least on the system clock signal CLK_SOC, the memory clock signal CLK_MEM, the monitoring signal EN and a refresh flag signal FLAG_REF.
  • the control circuit 130 receiving the system command signal CMD_SOC, the system clock signal CLK_SOC and the refresh cycle control signal tRFC_V, may generate the memory clock signal CLK_MEM, the command signals CS, CA ⁇ 0:6> and the refresh flag signal FLAG_REF.
  • the memory clock signal CLK_MEM may have a frequency corresponding to (or representing) the speed information.
  • the command signals CS, CA ⁇ 0:6> may be generated at a moment when the refresh cycle is considered.
  • the command signals CS, CA ⁇ 0:6> may be generated in synchronization with the memory clock signal CLK_MEM.
  • the command signals CS, CA ⁇ 0:6> may be combined to determine which operation is performed as shown in FIG. 7 .
  • the command signals CS, CA ⁇ 0:6> may include a refresh signal REF for controlling the refresh operation, active signals ACT 1 and ACT 2 for controlling the active operation, a precharge signal PCG for controlling the precharge operation, a write signal WR for controlling the write operation, and a read signal RD for controlling the read operation. Since the number of cases (2 ⁇ circumflex over ( ) ⁇ 8) according to the number of 8-bit signals (i.e., CS and CA ⁇ 0:6>) is limited, the command signals CS, CA ⁇ 0:6> may be generated or activated twice for a single operation.
  • a first refresh signal REF 1 may be generated in synchronization with a rising edge R 1 of the memory clock signal CLK_MEM, and a second refresh signal REF 2 may be subsequently generated in synchronization with a falling edge F 1 of the memory clock signal CLK_MEM.
  • the second refresh signal REF 2 may include information AB indicating a type of the refresh operation.
  • the information AB may indicate any one of a per-bank refresh operation and all-banks refresh operation.
  • the refresh flag signal FLAG_REF may be activated when the command signals CS, CA ⁇ 0:6> are generated as the refresh signal REF.
  • FIG. 3 is a block diagram illustrating the cycle control circuit 120 shown in FIG. 2 .
  • the cycle control circuit 120 may include a first calculation section 121 and a second calculation section 123 .
  • the first calculation section 121 may calculate a control value of the refresh cycle, based on at least one of the system clock signal CLK_SOC, the memory clock signal CLK_MEM, the monitoring signal EN and the refresh flag signal FLAG_REF, and generate a first calculation signal TCK/2 corresponding to the calculation result. For example, the first calculation section 121 may determine a half (1 ⁇ 2) cycle of the memory clock signal CLK_MEM as the control value.
  • the second calculation section 123 may generate the refresh cycle control signal tRFC_V based on the system clock signal CLK_SOC and the first calculation signal TCK/2. For example, the second calculation section 123 may generate the refresh cycle control signal tRFC_V corresponding to any one of a predetermined reference value and the calculated control value.
  • FIG. 4 is a block diagram illustrating the first calculation section 121 shown in FIG. 3 .
  • the first calculation section 121 may include a first enable block LOG 0 , a calculation control block FFs, a first count block CNT 0 , and a storing block RGT.
  • the first enable block LOG 0 may generate a first enable signal EN 0 , which is activated during a period before the speed of the memory clock signal CLK_MEM is changed, based on the monitoring signal EN and the refresh flag signal FLAG_REF.
  • the first enable block LOG 0 may include an inverter for inverting the monitoring signal EN, and a logic AND gate for performing an AND operation onto an output signal of the inverter and the refresh flag signal FLAG_REF to generate the first enable signal EN 0 .
  • the calculation control block FFs may generate a count control signal CNT_CTRL, which is activated during a count period corresponding to the half (1 ⁇ 2) cycle of the memory clock signal CLK_MEM, based on the first enable signal EN 0 , the memory clock signal CLK_MEM and the system clock signal CLK_SOC.
  • the calculation control block FFs may include a D flip-flop. The D flip-flop is enabled based on the first enable signal EN 0 and generates the count control signal CNT_CTRL, which corresponds to a logic level of the memory clock signal CLK_MEM, based on the system clock signal CLK_SOC.
  • the first count block CNT 0 may count the system clock signal CLK_SOC during the count period based on the count control signal CNT_CTRL and generate a count signal CNT 0 _V corresponding to a result of the count.
  • the first count block CNT 0 may include a counter.
  • the storing block RGT may store the count signal CNT 0 _V as the first calculation signal TCK/2.
  • the storing block RGT may include a register.
  • FIG. 5 is a block diagram illustrating the second calculation section 123 shown in FIG. 3 .
  • the second calculation section 123 may include a second count block CNT 1 , a plurality of shifting blocks SR 0 to SRK, a first selection block MUX 0 , a second enable block LOG 1 , and a second selection block MUX 1 .
  • the second count block CNT 1 may count the system clock signal CLK_SOC to generate a first cycle control signal tRFC_V 1 corresponding to the reference value.
  • the second count block CNT 1 may include a counter.
  • the shifting blocks SR 0 , . . . , SRK may sequentially shift the first cycle control signal tRFC_V 1 by a unit control value based on the system clock signal CLK_SOC to generate a plurality of shifting signals M 0 , . . . , MK (K is a positive integer).
  • each of the shifting blocks SR 0 to SRK may include a shift register.
  • the shifting blocks SR 0 to SRK may be coupled in series to each other.
  • a first shifting block SR 0 arranged at a front end among the shifting blocks SR 0 to SRK may shift the first cycle control signal tRFC_V 1 by the unit control value based on the system clock signal CLK_SOC to generate a first shifting signal M 0 among the shifting signals M 0 to MK.
  • Second to (K+1) th shifting blocks SR 1 to SRK among the shifting blocks SR 0 to SRK may shift the first to Kth shifting signals M 0 to MK ⁇ 1 generated from the first to Kth shifting blocks SR 0 to SRK ⁇ 1 arranged at front ends of the second to (K+1) th shifting blocks SR 1 to SRK by the unit control value based on the system clock signal CLK_SOC to generate second to (K+1) th shifting signals M 1 to MK.
  • the first selection block MUX 0 may select any one of the shifting signals M 0 to MK, based on the first calculation signal TCK/2, as a second cycle control signal tRFC_V 2 .
  • the first selection block MUX 0 may include a multiplexer.
  • the second enable block LOG 1 may generate a second enable signal EN 1 reflecting both whether the speed of the memory clock signal CLK_MEM is changed and whether the refresh operation is performed, based on the monitoring signal EN and the refresh flag signal FLAG_REF.
  • the second enable block LOG 1 may include a logic AND gate for performing an AND operation onto the monitoring signal EN and the refresh flag signal FLAG_REF to generate the second enable signal EN 1 .
  • the second selection block MUX 1 may select any one of the first and second cycle control signals tRFC_V 1 and tRFC_V 2 as the refresh cycle control signal tRFC_V, based on the second enable signal EN 1 .
  • the second selection block MUX 1 may include a multiplexer.
  • FIG. 6 is a timing diagram illustrating an operation of the semiconductor system shown in FIG. 1 .
  • the monitoring circuit 110 may generate the monitoring signal EN indicating whether the speed of the memory clock signal CLK_MEM is changed, based on the speed information included in the system command signal CMD_SOC. For example, when the speed information includes low-speed information LM corresponding to a low-speed mode, the monitoring circuit 110 may continuously deactivate the monitoring signal EN.
  • the cycle control circuit 120 may generate the refresh cycle control signal tRFC_V corresponding to the low-speed mode based on the system clock signal CLK_SOC, the memory clock signal CLK_MEM, the monitoring signal EN and the refresh flag signal FLAG_REF.
  • the control circuit 130 may generate the memory clock signal CLK_MEM, the command signals CS, CA ⁇ 0:6> and the refresh flag signal FLAG_REF based on the system command signal CMD_SOC, the system clock signal CLK_SOC and the refresh cycle control signal tRFC_V.
  • the control circuit 130 may generate the memory clock signal CLK_MEM having a lower speed (i.e., a low frequency) than the system clock signal CLK_SOC based on the low-speed information LM included in the system command signal CMD_SOC.
  • control circuit 130 may generate the command signals CS, CA ⁇ 0:6> corresponding to a first refresh operation and activate the refresh flag signal FLAG_REF, based on refresh information RM included in the system command signal CMD_SOC.
  • the control circuit 130 may generate the command signals CS, CA ⁇ 0:6> as the first refresh signal REF 1 in synchronization with a first rising edge of the memory clock signal CLK_MEM corresponding to a predetermined moment, and then generate the command signals CS, CA ⁇ 0:6> as the first refresh signal REF 1 in synchronization with a first falling edge of the memory clock signal CLK_MEM.
  • the command signals CS, CA ⁇ 0:6> may be generated two times.
  • the memory device 200 may generate a first internal refresh signal REF_INT 1 corresponding to the first refresh signal REF 1 based on the command signals CS, CA ⁇ 0:6> generated two times. If the command signals CS, CA ⁇ 0:6> are generated and entered the second time, the memory device 200 may generate the first internal refresh signal REF_INT 1 . It is because the command signals CS, CA ⁇ 0:6> generated the second time includes information capable of determining whether the refresh operation is the per-bank refresh operation or the all-banks refresh operation. The memory device 200 may perform the per-bank refresh operation or the all-banks refresh operation based on the first internal refresh signal REF_INT 1 .
  • the monitoring circuit 110 may continuously deactivate the monitoring signal EN based on the low-speed information LM.
  • the cycle control circuit 120 may generate the refresh cycle control signal tRFC_V corresponding to the low-speed mode based on the system clock signal CLK_SOC, the memory clock signal CLK_MEM, the monitoring signal EN and the refresh flag signal FLAG_REF.
  • the control circuit 130 may generate the memory clock signal CLK_MEM, the command signals CS, CA ⁇ 0:6> and the refresh flag signal FLAG_REF, based on the system command signal CMD_SOC, the system clock signal CLK_SOC and the refresh cycle control signal tRFC_V. For example, the control circuit 130 may generate the memory clock signal CLK_MEM having a lower speed (i.e., a low frequency) than the system clock signal CLK_SOC based on the low-speed information LM included in the system command signal CMD_SOC.
  • control circuit 130 may generate the command signals CS, CA ⁇ 0:6> corresponding to a second refresh operation and activate the refresh flag signal FLAG_REF, based on the refresh information RM included in the system command signal CMD_SOC.
  • the control circuit 130 may generate the command signals CS, CA ⁇ 0:6> corresponding to the second refresh operation after a refresh cycle tRFC corresponding to the reference value from a moment when the command signals CS, CA ⁇ 0:6> corresponding to the first refresh operation are generated, based on the refresh cycle control signal tRFC_V.
  • control circuit 130 may generate the command signals CS, CA ⁇ 0:6> as the second refresh signal REF 2 in synchronization with a second rising edge of the memory clock signal CLK_MEM corresponding to a moment after the refresh cycle tRFC, and then generate the command signals CS, CA ⁇ 0:6> as the second refresh signal REF 2 in synchronization with a second falling edge of the memory clock signal CLK_MEM. Since the number of cases (e.g., 2 ⁇ circumflex over ( ) ⁇ 8) that may be represented according to the limited number of signals (e.g., 8) is limited, the command signals CS, CA ⁇ 0:6> may be generated twice.
  • the memory device 200 may generate a second internal refresh signal REF_INT 2 corresponding to the second refresh signal REF 2 based on the command signals CS, CA ⁇ 0:6> generated twice.
  • the memory device 200 may generate the second internal refresh signal REF_INT 2 . This is because the command signals CS, CA ⁇ 0:6> generated the second time include information capable of determining whether the refresh operation is the per-bank refresh operation or the all-banks refresh operation.
  • the memory device 200 may perform the per-bank refresh operation or the all-banks refresh operation based on the second internal refresh signal REF_INT 2 .
  • the monitoring circuit 110 may activate the monitoring signal EN based on the high-speed information HM.
  • the cycle control circuit 120 may generate the refresh cycle control signal tRFC_V corresponding to the high-speed mode based on the system clock signal CLK_SOC, the memory clock signal CLK_MEM, the monitoring signal EN and the refresh flag signal FLAG_REF. For example, the cycle control circuit 120 may calculate a control value “a” of the refresh cycle, and generate the refresh cycle control signal tRFC_V corresponding to an added-up value of the reference value and the control value “a”. The control value “a” may correspond to a half (1 ⁇ 2) cycle of the memory clock signal CLK_MEM.
  • the control circuit 130 may generate the memory clock signal CLK_MEM, the command signals CS, CA ⁇ 0:6> and the refresh flag signal FLAG_REF based on the system command signal CMD_SOC, the system clock signal CLK_SOC and the refresh cycle control signal tRFC_V.
  • the control circuit 130 may generate the memory clock signal CLK_MEM having a higher speed (i.e., a high frequency) than the memory clock signal CLK_MEM of the low-speed mode based on the high-speed information HM included in the system command signal CMD_SOC.
  • control circuit 130 may generate the command signals CS, CA ⁇ 0:6> corresponding to a first active operation and deactivate the refresh flag signal FLAG_REF, based on the active information AM included in the system command signal CMD_SOC.
  • the control circuit 130 may generate the command signals CS, CA ⁇ 0:6> corresponding to the first active operation after a refresh cycle Adaptive tRFC corresponding to the added-up value from a moment when the command signals CS, CA ⁇ 0:6> corresponding to the first refresh operation are generated, based on the refresh cycle control signal tRFC_V.
  • control circuit 130 may generate the command signals CS, CA ⁇ 0:6> as a first active signal ACT 1 in synchronization with a third rising edge of the memory clock signal CLK_MEM corresponding to a moment after the refresh cycle Adaptive tRFC, and then generate the command signals CS, CA ⁇ 0:6> as the first active signal ACT 1 in synchronization with a third falling edge of the memory clock signal CLK_MEM. Since the number of cases (e.g., 2 ⁇ circumflex over ( ) ⁇ 8) that may be represented according to the limited number of 8-bit signals (e.g., CS and CA ⁇ 0:6>) is limited, the command signals CS, CA ⁇ 0:6> may be generated twice.
  • the memory device 200 may generate a first internal active signal ACT_INT 1 corresponding to the first active signal ACT 1 based on the command signals CS, CA ⁇ 0:6> generated twice. Since the first internal active signal ACT_INT 1 is activated after the second internal refresh signal REF_INT 2 is deactivated, it may prevent the second refresh operation from overlapping (i.e., conflicting) with the first active operation in a time domain.
  • An operating method for the semiconductor system in accordance with an embodiment of the present disclosure may include monitoring whether or not the speed of the memory clock signal CLK_MEM is changed during the refresh operation, and generating a predetermined command signal based on a monitoring result.
  • the second refresh signal REF 2 may be generated after the first refresh cycle, for example, tRFC, from a moment when the refresh signal for controlling the refresh operation, for example, REF 1 , is generated, when the speed of the memory clock signal CLK_MEM corresponds to the low-speed mode.
  • a predetermined command signal for example, the first active signal ACT 1
  • the second refresh cycle for example, Adaptive tRFC, that is longer than the first refresh cycle, for example, tRFC, from a moment when the refresh signal, for example, REF 2 , is generated, when the speed of the memory clock signal CLK_MEM corresponds to the high-speed mode as a monitoring result.
  • a conflict between the refresh operation before the speed of the clock signal is adjusted and a predetermined operation after the speed of the clock signal is adjusted may be prevented.
  • operational reliability may be improved.

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