US11237768B2 - Memory device changing memory area in which data is stored and operating method thereof - Google Patents

Memory device changing memory area in which data is stored and operating method thereof Download PDF

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US11237768B2
US11237768B2 US16/915,457 US202016915457A US11237768B2 US 11237768 B2 US11237768 B2 US 11237768B2 US 202016915457 A US202016915457 A US 202016915457A US 11237768 B2 US11237768 B2 US 11237768B2
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data
change
address
command
memory
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US20210181987A1 (en
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Gi Pyo UM
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SK Hynix Inc
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    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
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    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

Definitions

  • Various embodiments of the present disclosure generally relate to an electronic device, and more particularly, to a memory device and a method of operating the memory device.
  • a storage device stores data under the control of a host device such as a computer, a smartphone, or a smartpad.
  • a storage device include a hard disk drive (HDD) which stores data in a magnetic disk, and a solid state drive (SSD) or a memory card which stores data in a semiconductor memory, particularly, a nonvolatile memory.
  • HDD hard disk drive
  • SSD solid state drive
  • memory card which stores data in a semiconductor memory, particularly, a nonvolatile memory.
  • a storage device may include a memory device in which data is stored and a memory controller which controls storage of the data in the memory device.
  • Such memory devices may a volatile memory or a nonvolatile memory.
  • Representative examples of a nonvolatile memory include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase-change random access memory (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and a ferroelectric RAM (FRAM).
  • Various embodiments of the present disclosure are directed to a memory device that changes a memory area in which data is stored, and a method of operating the memory device.
  • the memory device may include a memory cell array configured to include a plurality of memory areas, an input/output circuit configured to receive a command, an address, and data from an external controller, a page buffer group configured to include a plurality of page buffers respectively coupled to the plurality of memory areas through a plurality of bit lines, a row decoder configured to select a memory area, on which an operation corresponding to the command is to be performed, from among the plurality of memory areas, based on a row address included in the address, a column decoder configured to transfer the data to a page buffer of the plurality of page buffers according to a column address included in the address and an address controller configured to control the row decoder and the column decoder so that the data is stored in another memory area other than the selected memory area, in response to an address change command received from the external controller.
  • the memory device may include a memory cell array configured to include a plurality of memory areas, an input/output circuit configured to receive a command, an address, and data from an external controller, a page buffer group configured to include a plurality of page buffers respectively coupled to the plurality of memory areas through a plurality of bit lines, a row decoder configured to select a memory area, on which an operation corresponding to the command is to be performed, from among the plurality of memory areas according to a row address included in the address, a column decoder configured to transfer the data to a page buffer of the plurality of page buffers according to a column address included in the address and an address controller configured to control the column decoder so that change data for changing the data is stored in the page buffer of the plurality of page buffers in response to a data change command that is received from the external controller.
  • An embodiment of the present disclosure may provide for a method of operating a memory device, the memory device including a plurality of memory areas and a plurality of page buffers respectively coupled to the plurality of memory areas through a plurality of bit lines.
  • the method may include receiving a command, an address, and data from an external controller, selecting a memory area, on which an operation corresponding to the command is to be performed, from among the plurality of memory areas according to a row address included in the address, transferring the data to a page buffer of the plurality of page buffers according to a column address included in the address, receiving an address change command for instructing a change of the address and storing the data in another memory area other than the selected memory area in response to the address change command.
  • An embodiment of the present disclosure may provide for an operating method of a memory system, the memory system including a controller and a memory device.
  • the operating method may include sequentially providing, by a controller to the memory device, one or more of first and second command groups, updating, by the memory device in response to the first command group, data currently buffered in a page buffer indicated by a column address to updated data, the column address and the updated data being included in the first command group and programming, by the memory device in response to the confirm command, data currently buffered in page buffers into a memory region indicated by a last provided row address, wherein the second command group includes a row address different from a row address included in an immediately previous command group, wherein the first command group selectively includes a row address different from a row address included in an immediately previous command group.
  • An embodiment of the present disclosure may provide for an operating method of a controller.
  • the operating method may include, by sequentially providing one or more of first and second command groups, controlling a memory device to update, in response to the first command group, data currently buffered in a page buffer indicated by a column address to updated data, the column address and the updated data being included in the first command group and program, in response to the confirm command, data currently buffered in page buffers into a memory region indicated by a last provided row address, wherein the second command group includes a row address different from a row address included in an immediately previous command group, wherein the first command group selectively includes a row address different from a row address included in an immediately previous command group.
  • An embodiment of the present disclosure may provide for an operating method of a memory device operative in response to sequential one or more of first and second command groups.
  • the operating method may include updating, in response to the first command group, data currently buffered in a page buffer indicated by a column address to updated data, the column address and the updated data being included in the first command group and programming, in response to the confirm command, data currently buffered in page buffers into a memory region indicated by a last provided row address, wherein the second command group includes a row address different from a row address included in an immediately previous command group, wherein the first command group selectively includes a row address different from a row address included in an immediately previous command group.
  • FIG. 1 is a block diagram illustrating a storage device.
  • FIG. 2 is a diagram illustrating the structure of a memory device, such as that of FIG. 1 .
  • FIG. 3 is a diagram illustrating an embodiment of a memory cell array, such as that of FIG. 2 .
  • FIG. 4 is a circuit diagram illustrating a representative memory block BLKa of memory blocks BLK 1 to BLKz of FIG. 3 .
  • FIG. 5 is a circuit diagram illustrating a representative memory block BLKb of the memory blocks BLK 1 to BLKz of FIG. 3 .
  • FIG. 6 is a diagram for explaining the pin configuration of a memory device, such as that of FIG. 1 .
  • FIG. 7 is a diagram for explaining commands, an address, and data that are input through data input/output lines of FIG. 6 .
  • FIGS. 8A and 8B are diagrams for explaining commands and/or addresses that are received through data input/output lines to change a row address.
  • FIG. 9 is a diagram for explaining the operation of a memory device which changes a row address based on the commands and/or addresses received.
  • FIG. 10 is a diagram for explaining commands, addresses, and data that are received through data input/output lines to change data.
  • FIG. 11 is a diagram for explaining the operation of a memory device which changes data and/or a row address based on the commands, addresses, and data received.
  • FIG. 12 is a diagram illustrating a cache program operation.
  • FIG. 13 is a diagram illustrating a cache program operation to which the present invention is applied.
  • FIGS. 14A and 14B are diagrams for explaining a case where address change commands or data change commands are successively received.
  • FIGS. 15A and 15B are diagrams for explaining a case where an address change command and a data change command are received together.
  • FIG. 16 is a flowchart illustrating operation of a memory device according to an embodiment of the present disclosure.
  • FIG. 17 is a flowchart illustrating operation of a memory device according to an embodiment of the present disclosure.
  • FIG. 18 is a flowchart illustrating operation of a memory device according to an embodiment of the present disclosure.
  • FIG. 19 is a block diagram illustrating an example of a solid state drive (SSD) system to which a storage device is applied according to an embodiment of the present disclosure.
  • SSD solid state drive
  • FIG. 1 is a block diagram illustrating a storage device.
  • a storage device 50 may include a memory device 100 , a memory controller 200 , and a buffer memory (not illustrated).
  • the storage device 50 may store data under the control of a host 300 , such as a mobile phone, a smartphone, an MP3 player, a laptop computer, a desktop computer, a game console, a television (TV), a tablet PC, or an in-vehicle infotainment system.
  • a host 300 such as a mobile phone, a smartphone, an MP3 player, a laptop computer, a desktop computer, a game console, a television (TV), a tablet PC, or an in-vehicle infotainment system.
  • the storage device 50 may be configured as any of various types of storage devices depending on a host interface that is a scheme for communication with the host 300 .
  • the storage device 50 may be implemented as a solid state disk (SSD), a multimedia card such as an MMC, an embedded MMC (eMMC), a reduced size MMC (RS-MMC), or a micro-MMC, a secure digital card such as an SD, a mini-SD, or a micro-SD, a universal storage bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card-type storage device, a peripheral component interconnection (PCI)-card type storage device, a PCI express (PCI-E) card-type storage device, a compact flash (CF) card, a smart media card, and/or a memory stick.
  • SSD solid state disk
  • MMC multimedia card
  • eMMC embedded MMC
  • RS-MMC reduced size MMC
  • micro-MMC micro-M
  • the storage device 50 may be manufactured in any of various types of package forms.
  • the storage device 50 may be manufactured as package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer-level fabricated package (WFP), and/or wafer-level stack package (WSP).
  • POP package on package
  • SIP system in package
  • SOC system on chip
  • MCP multi-chip package
  • COB chip on board
  • WFP wafer-level fabricated package
  • WSP wafer-level stack package
  • the memory device 100 may store data.
  • the memory device 100 is operated in response to the control of the memory controller 200 .
  • the memory device 100 may include a memory cell array including a plurality of memory cells which store data.
  • the memory cell array may include a plurality of memory blocks.
  • Each memory block may include a plurality of memory cells, which may constitute a plurality of pages.
  • each page may be a unit by which data is stored in the memory device 100 or by which data stored in the memory device 100 is read.
  • a memory block may be a unit by which data is erased.
  • the memory device 100 may take many alternative forms, such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate fourth generation (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory device, a resistive RAM (RRAM), a phase-change memory (PRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FRAM), or a spin transfer torque RAM (STT-RAM).
  • DDR SDRAM double data rate synchronous dynamic random access memory
  • LPDDR4 SDRAM low power double data rate fourth generation SDRAM
  • GDDR SDRAM graphics double data rate SDRAM
  • LPDDR SDRAM low power DDR SDRAM
  • RDRAM Rambus dynamic random access memory
  • NAND flash memory a NAND flash memory
  • vertical NAND flash memory a vertical NAND
  • the memory device 100 may be implemented in a two-dimensional (2D) array structure or a three-dimensional (3D) array structure.
  • the present disclosure may also be applied not only to a flash memory device in which a charge storage layer is formed of a conductive floating gate (FG), but also to a charge trap flash (CTF) memory device in which a charge storage layer is formed of an insulating layer.
  • FG conductive floating gate
  • CTF charge trap flash
  • the memory device 100 may be operated in a single-level cell (SLC) manner in which one data bit is stored in one memory cell.
  • the memory device 100 may be operated in a manner in which at least two data bits are stored in one memory cell.
  • the memory device 100 may be operated in a multi-level cell (MLC) manner in which two data bits are stored in one memory cell, a triple-level cell (TLC) manner in which three data bits are stored in one memory cell, or a quadruple-level cell (QLC) manner in which four data bits are stored in one memory cell.
  • MLC multi-level cell
  • TLC triple-level cell
  • QLC quadruple-level cell
  • the memory device 100 may receive a command and an address from the memory controller 200 , and may access the area of the memory cell array, selected by the address. That is, the memory device 100 may perform an operation corresponding to the command on the area selected by the address. For example, the memory device 100 may perform a write operation (i.e., program operation), a read operation or an erase operation in response to the received command.
  • a program command is received
  • the memory device 100 may program data to the area selected by the address.
  • a read command is received, the memory device 100 may read data from the area selected by the address.
  • an erase command is received, the memory device 100 may erase data stored in the area selected by the address.
  • the memory device 100 may include an address controller 150 .
  • the address controller 150 may control the received address based on an address change command and/or a data change command received from the memory controller 200 .
  • the address change command may instruct a change of a scheme of programming data received from the memory controller 200 .
  • the address change command may instruct a change of a data program scheme in response to a command that is received before a confirm command is received.
  • the memory device 100 may receive an address from the memory controller 200 , wherein the address received from the memory controller 200 may include a row address and a column address.
  • the address controller 150 may control a peripheral circuit (see FIG. 2 ) so that at least one of the received row address and column address is used.
  • the address controller 150 may output the column address to a column decoder and the row address to a row decoder. Thereafter, the column decoder may select a page buffer corresponding to the column address, and the row decoder may select a memory area corresponding to the row address.
  • the memory area may be any area within a memory cell array. That is, the memory area may be at least one memory block.
  • the address controller 150 may control the peripheral circuit so that the received data is stored in the page buffer using the column address and a memory area in which the data is to be stored is selected using the row address.
  • the memory controller 200 may control the overall operation of the storage device 50 .
  • the memory controller 200 may run firmware (FW).
  • firmware such as a Flash Translation Layer (FTL) for controlling communication between the host 300 and the memory device 100 .
  • FTL Flash Translation Layer
  • the memory controller 200 may receive data and a logical block address (LBA) from the host 300 , and may translate the logical block address (LBA) into a physical block address (PBA) indicating the address of memory cells which are included in the memory device 100 and in which data is to be stored. Further, the memory controller 200 may store a logical-physical address mapping table, which configures mapping relationships between logical block addresses (LBA) and physical block addresses (PBA), in the buffer memory.
  • LBA logical block address
  • PBA physical block address
  • the memory controller 200 may control the memory device 100 so that a program operation, a read operation or an erase operation is performed in response to a request received from the host 300 .
  • the memory controller 200 may convert the program request into a program command, and may provide the program command, a physical block address (PBA), and data to the memory device 100 .
  • PBA physical block address
  • the memory controller 200 may convert the read request into a read command, select a physical block address corresponding to the logical block address, and thereafter provide the read command and the physical block address (PBA) to the memory device 100 .
  • the memory controller 200 may convert the erase request into an erase command, select a physical block address corresponding to the logical block address, and thereafter provide the erase command and the physical block address (PBA) to the memory device 100 .
  • PBA physical block address
  • the memory controller 200 may autonomously generate a program command, an address, and data without receiving a request from the host 300 , and may transmit them to the memory device 100 .
  • the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations, such as a program operation for wear leveling and a program operation for garbage collection.
  • the memory controller 200 may control data exchange between the host 300 and the buffer memory (not illustrated). Alternatively, the memory controller 200 may temporarily store system data for controlling the memory device 100 in the buffer memory. For example, the memory controller 200 may temporarily store data, input from the host 300 , in the buffer memory, and may then transmit the data, temporarily stored in the buffer memory, to the memory device 100 .
  • the buffer memory may be used as a working memory or a cache memory for the memory controller 200 .
  • the buffer memory may store codes or commands that are executed by the memory controller 200 .
  • the buffer memory may store data that is processed by the memory controller 200 .
  • the buffer memory may be implemented as a DRAM such as a double data rate SDRAM (DDR SDRAM), a double data rate fourth generation (DDR4) SDRAM, a low power double data rate fourth generation (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR) SDRAM, or a Rambus DRAM (RDRAM), or as a static RAM (SRAM).
  • DDR SDRAM double data rate SDRAM
  • DDR4 SDRAM double data rate fourth generation SDRAM
  • LPDDR4 SDRAM low power double data rate fourth generation SDRAM
  • GDDR graphics double data rate SDRAM
  • LPDDR low power DDR SDRAM
  • RDRAM Rambus DRAM
  • SRAM static RAM
  • the storage device 50 may not include the buffer memory.
  • a volatile memory device disposed outside the storage device 50 may function as the buffer memory.
  • the memory controller 200 may control at least two memory devices 100 .
  • the memory controller 200 may control the memory devices 100 by way of an interleaving scheme to improve operating performance.
  • the host 300 may communicate with the storage device 50 using at least one of various communication methods, such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed Interchip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnection (PCI), PCI express (PCIe), Nonvolatile Memory express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMedia Card (MMC), embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and/or Load Reduced DIMM (LRDIMM) communication methods.
  • USB Universal Serial Bus
  • SATA Serial AT Attachment
  • SAS Serial Attached SCSI
  • HSIC High Speed Interchip
  • SCSI Small Computer System Interface
  • PCI Peripheral Component Interconnection
  • PCIe PCI express
  • NVMe Nonvolatile Memory express
  • UFS Universal Flash Storage
  • SD Secure Digital
  • MMC MultiMedia Card
  • eMMC embedded
  • FIG. 2 is a diagram illustrating a structure of the memory device of FIG. 1 .
  • the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and control logic 130 .
  • the memory cell array 110 includes a plurality of memory blocks BLK 1 to BLKz.
  • the plurality of memory blocks BLK 1 to BLKz are coupled to a row decoder 121 through row lines RL.
  • Each of the memory blocks BLK 1 to BLKz may be coupled to a page buffer group 123 through bit lines BL 1 to BLn.
  • Each of the memory blocks BLK 1 to BLKz may include a plurality of memory cells.
  • the plurality of memory cells may be nonvolatile memory cells. Memory cells coupled to the same word line may be defined as a single page. Therefore, a single memory block may include a plurality of pages.
  • the row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line.
  • Each of the memory cells included in the memory cell array 110 may be implemented as a single-level cell (SLC) capable of storing one data bit, a multi-level cell (MLC) capable of storing two data bits, a triple-level cell (TLC) capable of storing three data bits, or a quadruple-level cell (QLC) capable of storing four data bits.
  • SLC single-level cell
  • MLC multi-level cell
  • TLC triple-level cell
  • QLC quadruple-level cell
  • the peripheral circuit 120 may perform a program operation, a read operation, or an erase operation on a selected area of the memory cell array 110 under the control of the control logic 130 .
  • the peripheral circuit 120 may drive the memory cell array 110 .
  • the peripheral circuit 120 may apply various operating voltages to the row lines RL and the bit lines BL 1 to BLn or discharge the applied voltages under the control of the control logic 130 .
  • the peripheral circuit 120 may include the row decoder 121 , a voltage generator 122 , the page buffer group 123 , a column decoder 124 , an input/output circuit 125 , and a sensing circuit 126 .
  • the row decoder 121 is coupled to the memory cell array 110 through the row lines RL.
  • the row lines RL may include the at least one source select line, the plurality of word lines, and the at least one drain select line.
  • the word lines may include normal word lines and dummy word lines.
  • the row lines RL may further include a pipe select line.
  • the row decoder 121 may decode a row address RADD received from the control logic 130 .
  • the row decoder 121 selects at least one of the memory blocks BLK 1 to BLKz according to the decoded address. Further, the row decoder 121 may select at least one word line WL of the selected memory block so that voltages generated by the voltage generator 122 are applied to the at least one word line WL according to the decoded address.
  • the row decoder 121 may apply a program voltage to a selected word line and apply a program pass voltage having a level lower than that of the program voltage to unselected word lines.
  • the row decoder 121 may apply a verify voltage to a selected word line and apply a verify pass voltage higher than the verify voltage to unselected word lines.
  • the row decoder 121 may apply a read voltage to a selected word line and apply a read pass voltage higher than the read voltage to unselected word lines.
  • the erase operation of the memory device 100 is performed on a memory block basis.
  • the row decoder 121 may select one memory block according to the decoded address.
  • the row decoder 121 may apply a ground voltage to word lines coupled to the selected memory block.
  • the voltage generator 122 may be operated under the control of the control logic 130 .
  • the voltage generator 122 may generate a plurality of voltages using an external supply voltage provided to the memory device 100 .
  • the voltage generator 122 may generate various operating voltages Vop that are used for program, read, and erase operations in response to an operation signal OPSIG.
  • the voltage generator 122 may generate a program voltage, a verify voltage, a pass voltages, a read voltage, an erase voltage, etc. under the control of the control logic 130 .
  • the voltage generator 122 may generate an internal supply voltage by regulating the external supply voltage.
  • the internal supply voltage generated by the voltage generator 122 is used as an operating voltage for the memory device 100 .
  • the voltage generator 122 may generate a plurality of voltages using the external supply voltage or the internal supply voltage.
  • the voltage generator 122 may include a plurality of pumping capacitors for receiving the internal supply voltage and generate a plurality of voltages by selectively enabling the plurality of pumping capacitors under the control of the control logic 130 .
  • the generated voltages may be supplied to the memory cell array 110 by the row decoder 121 .
  • the page buffer group 123 includes first to n-th page buffers PB 1 to PBn, which are coupled to the memory cell array 110 through the first to n-th bit lines BL 1 to BLn, respectively.
  • the first to n-th page buffers PB 1 to PBn are operated under the control of the control logic 130 .
  • the first to n-th page buffers PB 1 to PBn may be operated in response to page buffer control signals PBSIGNALS.
  • the first to n-th page buffers PB 1 to PBn may temporarily store data received through the first to n-th bit lines BL 1 to BLn or may sense voltages or currents of the bit lines BL 1 to BLn during a read or verify operation.
  • the first to n-th page buffers PB 1 to PBn may transfer the data DATA, received through the input/output circuit 125 , to selected memory cells through the first to n-th bit lines BL 1 to BLn.
  • the memory cells in the selected page are programmed based on the received data DATA.
  • the first to n-th page buffers PB 1 to PBn may read page data by sensing the voltages or currents received through the first to n-th bit lines BL 1 to BLn from the selected memory cells.
  • the first to n-th page buffers PB 1 to PBn may read data DATA from the memory cells in the selected page through the first to n-th bit lines BL 1 to BLn, and may output the read data DATA to the input/output circuit 125 under the control of the column decoder 124 .
  • the first to n-th page buffers PB 1 to PBn may allow the first to n-th bit lines BL 1 to BLn to float or may apply the erase voltage to the first to n-th bit lines BL 1 to BLn.
  • the column decoder 124 may transfer data between the input/output circuit 125 and the page buffer group 123 in response to a column address CADD. For example, the column decoder 124 may exchange data with the first to n-th page buffers PB 1 to PBn through data lines DL or may exchange data with the input/output circuit 125 through column lines CL.
  • the input/output circuit 125 may transfer a command CMD and an address ADDR, received from the memory controller 200 described above with reference to FIG. 1 , to the control logic 130 , or may exchange data DATA with the column decoder 124 .
  • the sensing circuit 126 may generate a reference current in response to an enable bit VRYBIT, and may compare a sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current and then output a pass signal PASS or a fail signal FAIL.
  • the control logic 130 may control the peripheral circuit 120 by outputting the operation signal OPSIG, the row address RADD, the page buffer control signals PBSIGNALS, and the enable bit VRYBIT in response to the command CMD and the address ADDR. In addition, the control logic 130 may determine whether a verify operation has passed or failed in response to the pass or fail signal PASS or FAIL.
  • the memory cells included in the memory cell array 110 may be programmed to any one of a plurality of program states in each memory cell.
  • the number of program states for a given memory cell depends on its type, i.e., SLC, MLC, TLC, QLC, etc.
  • a target program state of the corresponding memory cell may be determined to be any one of the plurality of program states depending on the data to be stored.
  • control logic 130 may include an address controller 150 .
  • the address controller 150 may control a column address and a row address included in the address ADDR received from the memory controller 200 (shown in FIG. 1 ).
  • the address controller 150 may control the column and row addresses so that the column address is transmitted to the column decoder 124 and the row address is transmitted to the row decoder 121 .
  • the memory device 100 may sequentially receive the address ADDR and the data DATA.
  • the memory device 100 may receive a new command.
  • the new command may be an address change command or a data change command.
  • the address change command may be for instructing the storage of data in a new memory area, regardless of the row address included in the address ADDR received from the memory controller 200 before receiving the address change command.
  • the memory area may be any one of areas included in the memory cell array 110 . That is, the memory area may be an area corresponding to at least one memory block.
  • the data change command may be for changing the data DATA received from the memory controller 200 to other data.
  • a change address received, together with the data change command, from the memory controller 200 may include a change row address as well as a change column address.
  • the memory device 100 may store the change data in a new memory area based on the change row address.
  • the memory device 100 may receive a new command, and may store data in another memory area (i.e., a memory area other than a previously determined memory area) in response to the new command. Therefore, the data is stored in the memory area other than the previously determined memory area, and thus a data storage scheme may change.
  • another memory area i.e., a memory area other than a previously determined memory area
  • data may be stored using a scheme, such as a multi-level cell (MLC), triple-level cell (TLC) or quadruple-level cell (QLC) scheme, based on a subsequently received change address.
  • MLC multi-level cell
  • TLC triple-level cell
  • QLC quadruple-level cell
  • data may be stored using a scheme, such as a single-level cell (SLC), multi-level cell (MLC), or quadruple-level cell (QLC) scheme, based on a subsequently received change address.
  • the memory device 100 may storage data using various schemes, such as the SLC and the MLC schemes.
  • a program scheme changes, a new row address is required, and thus the memory device 100 may ignore the received row address and receive a new address (i.e., a change address) from the memory controller 200 .
  • the new address or the change address may be received together with an address change command or a data change command.
  • the address controller 150 may output the column address to the column decoder 124 .
  • the column decoder 124 may decode the column address CADD, and may then determine a page buffer in which the data received from the memory controller 200 is to be stored. When the page buffer is determined by the column decoder 124 , the data received from the memory controller 200 may be stored in the corresponding page buffer.
  • the address controller 150 may output the row address to the row decoder 121 .
  • the row decoder 121 may decode the row address, and may then determine a memory area in which the data received from the memory controller 200 is to be stored. When the memory area is determined by the row decoder 121 , the data received from the memory controller 200 may be stored in the corresponding memory area.
  • FIG. 3 is a diagram illustrating an embodiment of the memory cell array of FIG. 2 .
  • the memory cell array 110 includes a plurality of memory blocks BLK 1 to BLKz.
  • Each memory block may have a three-dimensional (3D) structure.
  • Each memory block includes a plurality of memory cells stacked on a substrate. Such memory cells are arranged in a positive X (+X) direction, a positive Y (+Y) direction, and a positive Z (+Z) direction.
  • the structure of each memory block is described in detail below with reference to FIGS. 4 and 5 .
  • FIG. 4 is a circuit diagram illustrating a representative memory block BLKa of the memory blocks BLK 1 to BLKz of FIG. 3 .
  • the memory block BLKa includes a plurality of cell strings CS 11 to CS 1 m and CS 21 to CS 2 m .
  • each of the cell strings CS 11 to CS 1 m and CS 21 to CS 2 m may be formed in a ‘U’ shape.
  • m cell strings are arranged in a row direction (i.e. a positive (+) X direction).
  • two cell strings are illustrated as being arranged in a column direction (i.e. a positive (+) Y direction). However, this illustration is made for clarity; it will be understood that three or more cell strings may be arranged in the column direction.
  • Each of the plurality of cell strings CS 11 to CS 1 m and CS 21 to CS 2 m includes at least one source select transistor SST, first to n-th memory cells MC 1 to MCn, a pipe transistor PT, and at least one drain select transistor DST.
  • the source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC 1 to MCp.
  • the source select transistors of cell strings arranged in the same row are coupled to a source select line extending in a row direction, and source select transistors of cell strings arranged in different rows are coupled to different source select lines.
  • source select transistors of cell strings CS 11 to CS 1 m in a first row are coupled to a first source select line SSL 1 .
  • the source select transistors of cell strings CS 21 to CS 2 m in a second row are coupled to a second source select line SSL 2 .
  • source select transistors of the cell strings CS 11 to CS 1 m and CS 21 to CS 2 m may be coupled in common to a single source select line.
  • the first to n-th memory cells MC 1 to MCn in each cell string are coupled between the source select transistor SST and the drain select transistor DST.
  • the first to n-th memory cells MC 1 to MCn may be divided into first to p-th memory cells MC 1 to MCp and p+1-th to n-th memory cells MCp+1 to MCn.
  • the first to p-th memory cells MC 1 to MCp are sequentially arranged in a direction opposite a positive (+) Z direction and are connected in series between the source select transistor SST and the pipe transistor PT.
  • the p+1-th to n-th memory cells MCp+1 to MCn are sequentially arranged in the +Z direction and are connected in series between the pipe transistor PT and the drain select transistor DST.
  • the first to p-th memory cells MC 1 to MCp and the p+1-th to n-th memory cells MCp+1 to MCn are coupled to each other through the pipe transistor PT.
  • the gates of the first to n-th memory cells MC 1 to MCn of each cell string are coupled to first to n-th word lines WL 1 to WLn, respectively.
  • a gate of the pipe transistor PT of each cell string is coupled to a pipeline PL.
  • the drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MCp+1 to MCn.
  • the cell strings in a row direction are coupled to drain select lines extending in a row direction. Drain select transistors of cell strings CS 11 to CS 1 m in the first row are coupled to a first drain select line DSL 1 . Drain select transistors of cell strings CS 21 to CS 2 m in a second row are coupled to a second drain select line DSL 2 .
  • Cell strings arranged in a column direction are coupled to bit lines extending in a column direction.
  • cell strings CS 11 and CS 21 in a first column are coupled to a first bit line BL 1 .
  • Cell strings CS 1 m and CS 2 m in an m-th column are coupled to an m-th bit line BLm.
  • the memory cells coupled to the same word line in cell strings arranged in a row direction constitute a single page.
  • memory cells coupled to the first word line WL 1 among the cell strings CS 11 to CS 1 m in the first row, constitute a single page.
  • Memory cells coupled to the first word line WL 1 among the cell strings CS 21 to CS 2 m in the second row, constitute a single additional page.
  • Cell strings arranged in the direction of a single row may be selected by selecting any one of the drain select lines DSL 1 and DSL 2 .
  • a single page may be selected from the selected cell strings by selecting any one of the word lines WL 1 to WLn.
  • even bit lines and odd bit lines instead of first to m-th bit lines BL 1 to BLm, may be provided. Further, even-numbered cell strings, among the cell strings CS 11 to CS 1 m or CS 21 to CS 2 m arranged in a row direction, may be coupled to the even bit lines, respectively, and odd-numbered cell strings, among the cell strings CS 11 to CS 1 m or CS 21 to CS 2 m arranged in the row direction, may be coupled to the odd bit lines, respectively.
  • one or more of the first to n-th memory cells MC 1 to MCn may be used as dummy memory cells.
  • dummy memory cell(s) are provided to reduce an electric field between the source select transistor SST and the memory cells MC 1 to MCp.
  • dummy memory cell(s) are provided to reduce an electric field between the drain select transistor DST and the memory cells MCp+1 to MCn.
  • the reliability of the operation of the memory block BLKa is improved, but the size of the memory block BLKa is increased.
  • the size of the memory block BLKa is reduced, but the reliability of the operation of the memory block BLKa may be deteriorated.
  • each of the dummy memory cells may have a required threshold voltage.
  • a program operation may be performed on all or some of the dummy memory cells.
  • the threshold voltages of the dummy memory cells control the voltages that are applied to the dummy word lines coupled to respective dummy memory cells, and thus the dummy memory cells may have required threshold voltages.
  • FIG. 5 is a circuit diagram illustrating a representative memory block BLKb of the memory blocks BLK 1 to BLKz of FIG. 3 .
  • the memory block BLKb includes a plurality of cell strings CS 11 ′ to CS 1 m ′ and CS 21 ′ to CS 2 m ′.
  • Each of the plurality of cell strings CS 11 ′ to CS 1 m ′ and CS 21 ′ to CS 2 m ′ extends in a positive Z (+Z) direction.
  • Each of the cell strings CS 11 ′ to CS 1 m ′ and CS 21 ′ to CS 2 m ′ includes at least one source select transistor SST, first to n-th memory cells MC 1 to MCn, and at least one drain select transistor DST, which are stacked on a substrate (not illustrated) below the memory block BLKb.
  • the source select transistor SST of each cell string is connected between a common source line CSL and memory cells MC 1 to MCn.
  • the source select transistors of cell strings arranged in the same row are coupled to the same source select line.
  • Source select transistors of cell strings CS 11 ′ to CS 1 m ′ arranged in a first row are coupled to a first source select line SSL 1 .
  • Source select transistors of cell strings CS 21 ′ to CS 2 m ′ arranged in a second row are coupled to a second source select line SSL 2 .
  • source select transistors of the cell strings CS 11 ′ to CS 1 m ′ and CS 21 ′ to CS 2 m ′ may be coupled in common to a single source select line.
  • the first to n-th memory cells MC 1 to MCn in each cell string are connected in series between the source select transistor SST and the drain select transistor DST.
  • the gates of the first to n-th memory cells MC 1 to MCn are coupled to first to n-th word lines WL 1 to WLn, respectively.
  • the drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC 1 to MCn. Drain select transistors of cell strings arranged in a row direction are coupled to drain select lines extending in a row direction. The drain select transistors of the cell strings CS 11 ′ to CS 1 m ′ in the first row are coupled to a first drain select line DSL 1 . The drain select transistors of the cell strings CS 21 ′ to CS 2 m ′ in the second row are coupled to a second drain select line DSL 2 .
  • the memory block BLKb of FIG. 5 has an equivalent circuit similar to that of the memory block BLKa of FIG. 4 except that a pipe transistor PT is excluded from each cell string.
  • even bit lines and odd bit lines instead of first to m-th bit lines BL 1 to BLm, may be provided. Further, even-numbered cell strings, among the cell strings CS 11 ′ to CS 1 m ′ or CS 21 ′ to CS 2 m ′ arranged in a row direction, may be coupled to the even bit lines, respectively, and odd-numbered cell strings, among the cell strings CS 11 ′ to CS 1 m ′ or CS 21 ′ to CS 2 m ′ arranged in the row direction, may be coupled to the odd bit lines, respectively.
  • At least one of the first to n-th memory cells MC 1 to MCn may be used as a dummy memory cell.
  • FIG. 6 is a diagram for explaining the pin configuration of the memory device of FIG. 1 .
  • the memory device 100 may communicate with an external controller through a plurality of data input/output lines.
  • the memory device 100 may communicate with the external controller through control signal lines which include a chip enable line CE #, a write enable line WE #, a read enable line RE #, an address latch enable line ALE, a command latch enable line CLE, a write protect line WP #, and a ready/busy line R/B, and data input/output lines DQ.
  • the memory device 100 may receive a chip enable signal from the external controller through the chip enable line CE #.
  • the memory device 100 may receive a write enable signal from the external controller through the write enable line WE #.
  • the memory device 100 may receive a read enable signal from the external controller through the read enable line RE #.
  • the memory device 100 may receive an address latch enable signal from the external controller through the address latch enable line ALE.
  • the memory device 100 may receive a command latch enable signal from the external controller through the command latch enable line CLE.
  • the memory device 100 may receive a write protect signal from the external controller through the write protect line WP #.
  • the memory device 100 may provide the memory controller 200 (shown in FIG. 1 ) with a ready/busy signal, indicating whether the memory device 100 is in a ready state or in a busy state, through the ready/busy line RB.
  • the chip enable signal may be a control signal for selecting the memory device 100 .
  • the chip enable signal When the chip enable signal is in a ‘high’ state and the memory device 100 is in a ‘ready’ state, the memory device 100 may enter a low-power standby state.
  • the write enable signal may be a control signal for performing control such that commands, addresses, and input data which are applied to the memory device 100 are stored in a latch.
  • the read enable signal may be a control signal for enabling the output of serial data.
  • the address latch enable signal may be one of control signals used by the host to indicate which one of a command, an address, and data corresponds to the type of signal input to the data input/output lines DQ.
  • the command latch enable signal may be one of control signals used by the host to indicate which one of a command, an address, and data corresponds to the type of signal input to the data input/output lines DQ.
  • the memory device 100 of FIG. 1 may identify that the signal input through the data input/output lines DQ is a command.
  • the memory device 100 may identify that the signal input through the data input/output lines DQ is an address.
  • the write protect signal may be a control signal for deactivating the program operation and the erase operation that are performed by the memory device 100 .
  • the ready/busy signal may be for identifying the status of the memory device 100 .
  • the ready/busy signal in a low state indicates that the memory device 100 is currently performing at least one operation.
  • the ready/busy signal in a high state indicates that the memory device 100 is currently performing no operation.
  • the ready/busy signal may be in a low state while the memory device 100 is performing a program operation, a read operation, or an erase operation.
  • the memory controller 200 described with reference to FIG. 1 may determine a termination time which is the time at which the program operation or the erase operation is terminated based on the ready/busy signal.
  • FIG. 7 is a diagram for explaining commands, an address, and data that are input through data input/output lines DQ of FIG. 6 .
  • FIG. 7 illustrates the flow of commands, an address, and data that are input through the conventional data input/output lines DQ of FIG. 6 . That is, FIG. 7 illustrates a first command CMD 1 , a first address ADDR 1 , first data DATA 1 , and a second command CMD 2 that are sequentially input through the data input/output lines DQ of FIG. 6 .
  • the first command CMD 1 may be a setup command.
  • the setup command may be a command indicating a scheme of programming the data received from the memory controller 200 . That is, in response to the setup command, a scheme corresponding to a single-level cell (SLC) scheme, a multi-level cell (MLC) scheme, a triple-level cell (TLC) scheme, or a quadruple-level cell (QLC) scheme, and/or a program scheme corresponding to any one of a page program scheme, a multi-plane scheme, and a cache program scheme may be determined.
  • SLC single-level cell
  • MLC multi-level cell
  • TLC triple-level cell
  • QLC quadruple-level cell
  • the first address ADDR 1 may be received through the data input/output lines DQ.
  • the first address ADDR 1 may include a column address and a row address. That is, the first address ADDR 1 may indicate a page buffer in which the data received from the memory controller 200 is to be temporarily stored and a memory area in which the data stored in the page buffer is to be stored.
  • the memory area in which data is to be stored may be any one of the memory blocks BLK 1 to BLKz included in the memory cell array 110 (shown in FIG. 2 ).
  • the memory device 100 may sequentially receive a column address and a row address included in the first address ADDR 1 . Based on the received column address, a page buffer included in the page buffer group 123 (shown in FIG. 2 ) may be determined, and based on the received row address, a memory area or a memory block in which the data stored in the page buffer is to be stored may be determined.
  • the first data DATA 1 received through the data input/output lines DQ after the first address ADDR 1 , may be data to be stored or programmed in the memory cell array 110 .
  • the first data DATA 1 may be temporarily stored in any one of page buffers included in the page buffer group 123 , and may then be programmed to a memory area determined based on the row address.
  • the memory area in which the first data DATA 1 is to be stored has been determined based on the first address ADDR 1 , there is a need to change the memory area in which the first data DATA 1 is to be stored depending on the amount of data received from an external controller or depending on whether pieces of data are successively received from the external controller.
  • data other than the first data DATA 1 is temporarily stored in the page buffer corresponding to a memory area even if the first data DATA 1 should be stored in the memory area, there is a need to change the data stored in the pager buffer.
  • the memory device 100 may receive a command for changing a memory area in which data is to be stored or a command for changing data temporarily stored in the page buffer. Details related to this operation are described below with reference to FIGS. 8A and 8B and subsequent drawings.
  • a second command CMD 2 received through the data input/output lines DQ after the first data DATA 1 , may be a confirm command.
  • the confirm command may be for instructing the initiation of an operation corresponding to the command determined in response to the setup command. Therefore, when the memory device 100 receives the confirm command, the memory device 100 may program the first data DATA 1 received from the memory controller 200 to any one of the plurality of memory areas.
  • the memory device 100 may initiate the operation of programming data after receiving the confirm command.
  • the memory device 100 may determine the memory area in which data is to be stored in response to the command received before the confirm command is received, or may determine the memory area in which changed data is to be stored after the data stored in the page buffer group 123 has changed.
  • FIGS. 8A and 8B are diagrams for explaining commands and/or addresses that are received through data input/output lines DQ to change a row address.
  • FIG. 8A illustrates a case where a command and an address are received before a confirm command is received to change a row address
  • FIG. 8B illustrates a case where only an address is received before a confirm command is received to change a row address.
  • a first command CMD 1 , a first address ADDR 1 , and first data DATA 1 may be sequentially received from an external controller through the data input/output lines DQ of FIG. 6 .
  • the first command CMD 1 may be a setup command
  • the second command CMD 2 may be a confirm command.
  • the setup command may be for determining a scheme of programming the data received from the external controller
  • the confirm command may be for instructing the initiation of an operation corresponding to the command determined in response to the setup command.
  • the first address ADDR 1 may include a column address and a row address.
  • the first data DATA 1 may be data to be programmed to the memory device 100 .
  • the first data DATA 1 may be temporarily stored in a page buffer corresponding to the column address included in the first address ADDR 1 .
  • the memory device 100 may program the first data DATA 1 stored in the page buffer to the memory cell array 110 .
  • a scheme of programming the first data DATA 1 may be determined based on the row address of the first address ADDR 1 .
  • the memory device 100 may receive an address change command and a change address from the external controller before receiving the confirm command.
  • the memory device 100 may receive a third command CMD 3 and a third address ADDR 3 ( 801 ).
  • the third command CMD 3 may be an address change command
  • the third address ADDR 3 may be a change address.
  • the address change command may be for instructing a change of a memory area in which data is to be stored based on the change address. That is, the memory area in which the first data DATA 1 is to be stored may change based on the third command CMD 3 and the third address ADDR 3 , and thus a method of storing the first data DATA 1 may change.
  • the third command CMD 3 is the address change command for changing a row address
  • the memory area in which the first data DATA 1 is to be stored may be determined based only on the row address, regardless of the column address included in the third address ADDR 3 .
  • the operation of the memory device 100 which determines the memory area in which the first data DATA 1 is to be stored based on the third command CMD 3 and the third address ADDR 3 , that is, based on the address change command and the change address, is described in detail below with reference to FIG. 9 .
  • the third address ADDR 3 for determining again the memory area in which the first data DATA 1 is to be stored may be received from the external controller.
  • the memory device 100 may receive only the third address ADDR 3 , which is a change address without receiving an address change command, in order to change the memory area in which the first data DATA 1 is to be stored ( 803 ).
  • the memory device 100 may sequentially receive the first command CMD 1 , the first address ADDR 1 , and the first data DATA 1 from the external controller through the data input/output lines DQ of FIG. 6 .
  • the memory device 100 may receive only the third address ADDR 3 from the external controller.
  • the memory device 100 may change the memory area, determined by the first address ADDR 1 , based on the third address ADDR 3 .
  • the memory area in which the first data DATA 1 is to be stored may change based only on the third address ADDR 3 that is received before the second command CMD 2 , that is, the confirm command, is received.
  • FIG. 9 is a diagram for explaining the operation of a memory device which changes a row address based on the commands and/or addresses received in FIGS. 8A and 8B .
  • FIG. 9 illustrates a memory cell array 110 , a row decoder 121 , a page buffer group 123 , a column decoder 124 , an input/output circuit 125 , and an address controller 150 , among components of the memory device of FIG. 2 .
  • the remaining components of the memory device of FIG. 2 are omitted in FIG. 9 .
  • an address change command CMD_AC of FIG. 9 may be the third command CMD 3 of FIG. 8A
  • a change address ADDR_C of FIG. 9 may be the third address ADDR 3 of FIGS. 8A and 8B . That is, FIG. 9 illustrates the operation of the memory device performed based on the address change command CMD_AC and the change address ADDR_C that are received before the confirm command is received.
  • data DATA is assumed to be the first data DATA 1 of FIGS. 8A and 8B .
  • the input/output circuit 125 may receive the address change command CMD_AC and the change address ADDR_C from the external controller through the data input/output lines DQ of FIG. 6 .
  • the input/output circuit 125 may transmit the address change command CMD_AC and the change address ADDR_C that are received from the external controller to the control logic 130 of FIG. 2 .
  • the address controller 150 included in the control logic 130 may control the row decoder 121 and the column decoder 124 so that the data DATA is stored in another memory area other than a selected memory area in response to the address change command CMD_AC.
  • the address change command CMD_AC may be for instructing a change of an address received from the external controller, in detail, the row address included in the first address ADDR 1 of FIGS. 8A and 8B .
  • the address controller 150 may receive the change address ADDR_C from the input/output circuit 125 .
  • the address controller 150 may output a change column address CADD_C, among addresses included in the change address ADDR_C, to the column decoder 124 , and may output a change row address RADD_C, among the addresses, to the row decoder 121 .
  • the address controller 150 may control the row decoder 121 so that another memory area other than a previously selected memory area is selected depending on the change row address RADD_C.
  • the address controller 150 may output the change row address RADD_C to the row decoder 121 , and the row decoder 121 may select a memory area corresponding to the change row address RADD_C from among memory areas included in the memory cell array 110 by decoding the change row address RADD_C.
  • the row decoder 121 may select the memory area corresponding to the change row address RADD_C, thus enabling a data storage scheme to be changed.
  • the data storage scheme has been determined to be a single-level cell (SLC)
  • the data may be stored using another scheme, such as a multi-level cell (MLC), a triple-level cell (TLC) or a quadruple-level cell (QLC), by selecting the memory area corresponding to the change row address RADD_C.
  • MLC multi-level cell
  • TLC triple-level cell
  • QLC quadruple-level cell
  • the change address ADDR_C may include the change column address CADD_C.
  • the address change command CMD_AC is for changing a row address and only the change address ADDR_C is externally received, together with the address change command CMD_AC, change data for changing data stored in the page buffer group 123 or storing data in the page buffer group 123 is not received. Therefore, even if the change column address CADD_C included in the change address ADDR_C has been output to the column decoder 124 , data may not change.
  • the memory device 100 when the memory device 100 receives a subsequent data change command, a subsequent change address, and subsequent data from the external controller after receiving the address change command CMD_AC and the change address ADDR_C, the data previously stored in the page buffer group 123 may be changed into the subsequently-received data based on the change column address included in the subsequent change address.
  • the column decoder 124 may decode the change column address and then change data previously stored in a page buffer corresponding to the change column address, or then store the subsequently-received data in the page buffer corresponding to the change column address.
  • the row address may change again. That is, even if the row address has changed in response to the address change command CMD_AC, a memory area in which externally received data is to be stored may change based on the row address included in the change address received together with the data change command.
  • a new address change command and a new change address may be received.
  • the memory area in which data is to be stored has changed in response to the address change command CMD_AC, when the new address change command is received, the memory area in which the data is to be stored may change again based on a change row address included in the new change address.
  • the memory device 100 may change again based on a change row address included in a change address, received together with a new address change command or data change command that is received before a confirm command is received.
  • FIG. 10 is a diagram for explaining commands, addresses, and data that are received through data input/output lines DQ to change data.
  • FIG. 10 illustrates a case where commands, addresses, and data are received through the data input/output lines DQ of FIG. 6 before a confirm command is received to change data stored in page buffers in the page buffer group 123 of FIG. 2 .
  • the first data DATA 1 may be temporarily stored in a page buffer corresponding to the column address included in the first address ADDR 1 .
  • the memory device 100 may store the first data DATA 1 , stored in the page buffer, in a memory area corresponding to the row address included in the first address ADDR 1 in response to a program command determined based on the first command CMD 1 .
  • the memory device 100 may receive new data from the external controller, and may then store the new data in the corresponding page buffer.
  • the memory device 100 may receive a fourth command CMD 4 , a fourth address ADDR 4 , and fourth data DATA 4 ( 1001 ).
  • the fourth command CMD 4 may be the data change command for changing data stored in the page buffer or storing the data in another page buffer in the page buffer group
  • the fourth address ADDR 4 may be for selecting any one of page buffers in the page buffer group
  • the fourth data DATA 4 may be data to which previously stored data is to be changed, or data to be newly stored in the page buffer.
  • the data change command CMD 4 , the change address ADDR 4 , and the change data DATA 4 may be received, and thus the data DATA 1 stored in the page buffer in the page buffer group may change into the data DATA 4 , or alternatively, the data DATA 4 may be stored in the page buffer corresponding to the change address ADDR 4 and in which no data is stored. Thereafter, when the confirm command CMD 2 is received, the data DATA 4 stored in the page buffers included in the page buffer group may be programmed to a memory area corresponding to the row address included in the first address ADDR 1 .
  • a memory area in which the first data DATA 1 is to be stored may be determined, according to the fourth address ADDR 4 , to be another memory area other than a memory area corresponding to the first address ADDR 1 . Therefore, in response to the data change command, the memory area in which data is to be stored may also change in addition to the change of data or storage of new data. When the memory area in which data is to be stored changes, a method of storing the first data DATA 1 may change.
  • FIG. 11 is a diagram for explaining the operation of a memory device which changes data and/or a row address based on the commands, addresses, and data received in FIG. 10 .
  • FIG. 11 illustrates a memory cell array 110 , a row decoder 121 , a voltage generator 122 , a page buffer group 123 , a column decoder 124 , an input/output circuit 125 , and a control logic 130 , among components of the memory device 100 of FIG. 2 .
  • the remaining components of the memory device 100 of FIG. 2 are omitted in the memory device 100 of FIG. 11 .
  • a data change command CMD_DC of FIG. 11 may be the fourth command CMD 4 of FIG. 10
  • a change address ADDR_C of FIG. 11 may be the fourth address ADDR 4 of FIG. 10
  • change/new data DATA_C of FIG. 11 may be the fourth data DATA 4 of FIG. 10 . That is, FIG. 11 illustrates the operation of the memory device performed based on the data change command CMD_DC and the change address ADDR_C that are received before the confirm command is received.
  • the input/output circuit 125 may receive the data change command CMD_DC and the change address ADDR_C from an external controller through the data input/output lines DQ of FIG. 6 .
  • the input/output circuit 125 may transmit the data change command CMD_DC and the change address ADDR_C, which are received from the external controller, to the control logic 130 , and may transmit the change/new data DATA_C to the column decoder 124 .
  • control logic 130 may receive the data change command CMD_DC, and may control the change address ADDR_C so that the change/new data DATA_C is stored in any one of the page buffers PB 1 to PBn in the page buffer group 123 .
  • the address controller 150 in the control logic 130 may receive the change address ADDR_C including a change column address CADD_C and a change row address RADD_C from the input/output circuit 125 .
  • the address controller 150 may control the row decoder 121 and the column decoder 124 so that new data DATA_C is stored in a page buffer, corresponding to the change column address CADD_C, and in which data is temporarily stored, or in a page buffer in which no data is stored.
  • the data change command CMD_DC for storing DATA_C in the page buffer in which data is temporarily stored may be for instructing a change of the first data DATA 1 (see FIG. 10 ).
  • the address controller 150 may output the change column address CADD_C, among addresses included in the change address ADDR_C, to the column decoder 124 , and may output the change row address RADD_C, among the addresses, to the row decoder 121 .
  • the address controller 150 may control the column decoder 124 so that a page buffer in which data is to be stored is selected depending on the change column address CADD_C.
  • the address controller 150 may output the change column address CADD_C to the column decoder 124 , and the column decoder 124 may select a page buffer corresponding to the change column address CADD_C by decoding the change column address CADD_C. That is, the column decoder 124 may receive DATA_C from the input/output circuit 125 , and may transmit DATA_C to the page buffer corresponding to the change column address CADD_C.
  • the column decoder 124 may change the data previously stored in the page buffers in the page buffer group 123 or store new data in the page buffers in the page buffer group 123 by transmitting DATA_C to the page buffer corresponding to the change column address CADD_C.
  • DATA_C may represent either data resulting from changing the previously-stored data or new data.
  • the change address ADDR_C may include the change row address RADD_C. Therefore, although the data change command CMD_DC has been received from the external controller, the memory device 100 may change the memory area in which data is to be stored to another memory area other than the memory area corresponding to the first address ADDR 1 (see FIG. 10 ), based on the change row address RADD_C included in the change address ADDR_C received together with the data change command CMD_DC.
  • DATA_C stored in the page buffer group 123 may be stored in a new memory area corresponding to the change row address RADD_C included in the change address ADDR_C.
  • the memory device 100 may subsequently receive another address change command and another change address from the external controller. In this case, based on the subsequent change row address included in the subsequent change address received together with the subsequent address change command, the memory area in which the DATA_C stored in the page buffer group 123 is to be stored may further change.
  • the memory area in which data is to be stored may further change based on the subsequent change address that is received together with the subsequent address change command from the external controller.
  • a subsequent data change command or a subsequent address change command, a subsequent change address, and subsequent change data may be received.
  • data previously stored in the page buffers included in the page buffer group 123 may change into the subsequent change data, or alternatively, the subsequent change data may be stored in the page buffers corresponding to the subsequent change address.
  • the memory area in which data is to be stored may further change.
  • the memory area in which data is to be stored may further change based on a subsequent change row address included in the subsequent change address received together with the subsequent address change command or the subsequent data change command that is received before a confirm command is received.
  • FIG. 12 is a diagram illustrating a cache program operation.
  • each of page buffers PB 1 to PBn included in the page buffer group 123 of FIG. 11 may include a cache latch and a main latch. Data received from an external controller may be stored in the cache latch, and data received from the cache latch may be stored in the main latch. The data stored in the main latch may be programmed to a specific area or memory block, among a plurality of memory blocks BLK 1 to BLKz, in the memory cell array 110 of FIG. 11 .
  • FIG. 12 illustrates any one of the page buffers PB 1 to PBn in the page buffer group 123 of FIG. 11 .
  • FIG. 12 illustrates a conventional cache program operation.
  • the cache program operation may include programming data stored in the main latch and storing data received from an external controller in the cache latch, which are simultaneously performed. By shortening the time required for the program operation through the cache program operation, the program operation may be efficiently performed.
  • first data DATA 1 may be transferred from the external controller (DATA 1 Transfer), and may then be stored in the cache latch. Thereafter, at time t 1 , the first data DATA 1 , stored in the cache latch, may be copied to the main latch (DATA 1 Copy).
  • the first data DATA 1 When the first data DATA 1 is stored in the main latch, the first data DATA 1 may be programmed to a memory cell array at time t 2 .
  • second data DATA 2 may be transferred from the external controller (DATA 2 Transfer).
  • the operation of programming the first data DATA 1 and the operation of receiving the second data DATA 2 from the external controller and storing the second data DATA 2 in the cache latch may be simultaneously performed, and thus the program operation may be efficiently performed.
  • the second data DATA 2 stored in the cache latch, may be copied to the main latch (DATA 2 Copy).
  • the second data DATA 2 stored in the main latch may be programmed to the memory cell array (DATA 2 Program) at the same time that third data DATA 3 may be transferred from the external controller, and may be stored in the cache latch (DATA 3 Transfer).
  • the third data DATA 3 stored in the cache latch, may be copied to the main latch.
  • the present disclosure may be applied to the above-described cache program operation. That is, the data stored in the cache latch may be changed, and the data stored in the main latch may be stored in another memory area, that is, a memory area other than a previously determined memory area.
  • FIG. 13 is a diagram illustrating a cache program operation to which the present disclosure is applied.
  • FIG. 13 illustrates a case where, during performance of a cache program operation, the memory device 100 receives a data change command before receiving a confirm command from the external controller.
  • first data DATA 1 may be received from the external controller and stored in the cache latch (DATA 1 Transfer).
  • the first data DATA 1 stored in the cache latch may be copied to the main latch (DATA 1 Copy).
  • the first data DATA 1 stored in the main latch may be programmed (DATA 1 Program) at the same time that second data DATA 2 received from the external controller may be stored in the cache latch (DATA 2 Transfer).
  • the memory device 100 may receive a data change command, a change address, and change data from the external controller.
  • the change data is third data DATA 3 .
  • the memory device 100 may store the change data DATA 3 in a page buffer corresponding to the change column address included in the change address in response to the data change command received from the external controller. That is, at time t 3 , the second data DATA 2 stored in the cache latch may change to third data DATA 3 (i.e., Change DATA 2 to DATA 3 ). At this time, when the change row address is also included in the change address, a memory area in which the third data DATA 3 is to be stored may also change together with the data DATA 3 .
  • the third data DATA 3 stored in the cache latch may be copied to the main latch at time t 4 (DATA 3 Copy). Thereafter, at time t 5 , the third data DATA 3 stored in the main latch is programmed (DATA 3 Program) at the same time that fourth data DATA 4 received from the external controller may be stored in the cache latch (DATA 4 Transfer).
  • the data stored in the cache latch may change in response to the data change command received from the external controller before the confirm command is received, and, in addition, the memory area to which the data stored in the cache latch is to be programmed may also change.
  • FIGS. 14A and 14B are diagrams for explaining a case where address change commands or data change commands are successively received.
  • FIG. 14A illustrates a case where address change commands, described in FIG. 8A , are successively input
  • FIG. 14B illustrates a case where data change commands, described in FIG. 10 , are successively input.
  • a first command CMD 1 , a first address ADDR 1 , and first data DATA 1 may be sequentially received from an external controller through the data input/output lines DQ of FIG. 6 . Thereafter, before a second command CMD 2 is received, a third command CMD 3 , a third address ADDR 3 , a fifth command CMD 5 , and a fifth address ADDR 5 may be sequentially received ( 1401 ).
  • the third command CMD 3 and the fifth command CMD 5 may be address change commands for instructing a change of a memory area in which data is to be stored, and the third address ADDR 3 and the fifth address ADDR 5 may be change addresses for changing the memory area.
  • the third command CMD 3 and the third address ADDR 3 may be received from the external controller. That is, in order to change a scheme of programming the first data DATA 1 , an address change command and a change address may be received.
  • the memory device 100 may receive a subsequent address change command CMD 5 and a subsequent change address ADDR 5 from the external controller, and may then change the memory area in which the data DATA 1 is to be stored.
  • address change commands CMD 3 and CMD 5 and change addresses ADDR 3 and ADDR 5 may be successively received from the external controller, and the memory area in which the first data DATA 1 is to be stored may be determined based on the change address ADDR 5 received immediately before the second command CMD 2 is received. That is, the memory area in which the first data DATA 1 is to be stored may be determined based on the change row address included in the fifth address ADDR 5 that is received immediately before the second command CMD 2 is received.
  • a first command CMD 1 , a first address ADDR 1 , and first data DATA 1 may be sequentially received from the external controller through the data input/output lines DQ of FIG. 6 . Thereafter, before the second command CMD 2 is received, a fourth command CMD 4 , a fourth address ADDR 4 , fourth data DATA 4 , a sixth command CMD 6 , a sixth address ADDR 6 , and sixth data DATA 6 may be sequentially received ( 1403 ).
  • the fourth command CMD 4 and the sixth command CMD 6 may be data change commands for instructing a change of data stored in the page buffer, the fourth address ADDR 4 and the sixth address ADDR 6 may be change addresses for changing the data, and the fourth data DATA 4 and the sixth data DATA 6 may be change data to replace existing data.
  • the fourth command CMD 4 , the fourth address ADDR 4 , and the fourth data DATA 4 may be received from the external controller. That is, in order to change the first data DATA 1 to the fourth data DATA 4 and store the fourth data DATA 4 , the data change command CMD 4 , the change address ADDR 4 , and the change data DATA 4 may be received.
  • the fourth data DATA 4 may change to the sixth data DATA 6 based on a subsequent data change command CMD 6 , a subsequent change address ADDR 6 , and subsequent data DATA 6 that are subsequently received.
  • the memory device 100 may receive the subsequent data change command CMD 6 , the subsequent change address ADDR 6 , and the subsequent data DATA 6 from the external controller, and may then change data previously stored in the page buffer corresponding to the subsequent change address ADDR 6 .
  • data change commands CMD 4 and CMD 6 , change addresses ADDR 4 and ADDR 6 , and change data DATA 4 and DATA 6 may be successively received, and data to be stored in the memory area may be determined based on the change data DATA 6 that is received immediately before the second command CMD 2 is received. That is, the sixth data DATA 6 , received immediately before the second command CMD 2 is received, may be determined to be data that is to be stored in the memory area corresponding to the subsequent change address ADDR 6 .
  • FIGS. 15A and 15B are diagrams for explaining a case where an address change command and a data change command are received together.
  • FIG. 15A illustrates a case where, after the address change command described in FIG. 8A has been received, the data change command described in FIG. 10 is received
  • FIG. 15B illustrates a case where, after the data change command described in FIG. 10 has been received, the address change command described in FIG. 8A is received.
  • FIGS. 15A and 15B operations which are the same as those of FIGS. 8A and 8B and FIG. 10 are not described again here.
  • a third command CMD 3 may be an address change command for instructing a change of a memory area in which data is to be stored
  • a third address ADDR 3 may be a change address for changing the memory area
  • a fourth command CMD 4 may be a data change command for instructing a change of the data stored in a page buffer
  • a fourth address ADDR 4 may be a change address for changing the data
  • fourth data DATA 4 may be change data to replace existing data.
  • a first command CMD 1 , a first address ADDR 1 , and first data DATA 1 may be sequentially received from the external controller through the data input/output lines DQ of FIG. 6 . Thereafter, before the second command CMD 2 is received, the third command CMD 3 , the third address ADDR 3 , the fourth command CMD 4 , the fourth address ADDR 4 , and the fourth data DATA 4 may be sequentially received ( 1501 ).
  • the third command CMD 3 and the third address ADDR 3 may be received from the external controller. That is, in order to change a scheme of programming the first data DATA 1 , an address change command CMD 3 and a change address ADDR 3 may be received.
  • the memory area in which the first data DATA 1 is to be stored is determined. Then, the data change command CMD 4 may be received. That is, even if the address change command CMD 3 and the change address ADDR 3 have been received from the external controller, the memory device 100 may receive a data change command CMD 4 , a change address ADDR 4 , and change data DATA 4 from the external controller, and may then change the data previously stored in the page buffer corresponding to the change address ADDR 4 .
  • a memory area in which data is to be stored may also change together with the data, that is, change to a memory area corresponding to the change row address and the change data DATA 4 .
  • a data change command CMD 4 , a change address ADDR 4 , and change data DATA 4 may be received after an address change command CMD 3 and a change address ADDR 3 have been received from the external controller, and not only data stored in the page buffer, but also the memory area in which the data is to be stored may also change. That is, the memory area in which the fourth data DATA 4 is to be stored may be determined based on the change row address included in the fourth address ADDR 4 that is received before the second command CMD 2 is received.
  • a first command CMD 1 , a first address ADDR 1 , and first data DATA 1 may be sequentially received from the external controller through the data input/output lines DQ of FIG. 6 . Thereafter, before the second command CMD 2 is received, the fourth command CMD 4 , the fourth address ADDR 4 , the fourth data DATA 4 , the third command CMD 3 , and the third address ADDR 3 may be sequentially received ( 1503 ).
  • the fourth command CMD 4 , the fourth address ADDR 4 , and the fourth data DATA 4 may be received from the external controller. That is, in order to change the first data DATA 1 to the fourth data DATA 4 and store the fourth data DATA 4 , the data change command CMD 4 , the change address ADDR 4 , and the change data DATA 4 may be received.
  • the memory device 100 may receive an address change command CMD 3 and a change address ADDR 3 from the external controller. That is, although the memory area in which data DATA 4 is to be stored has been determined by the change address ADDR 4 received together with the data change command CMD 4 , or by the address ADDR 1 received before the data change command CMD 4 is received, the memory area in which data DATA 4 is to be stored may change based on the address change command CMD 3 received from the external controller.
  • the memory area in which the fourth data DATA 4 is to be stored may change depending on the change row address included in the third address ADDR 3 .
  • an address change command CMD 3 and a change address ADDR 3 may be received after a data change command CMD 4 , a change address ADDR 4 , and change data DATA 4 have been received from the external controller, and not only data stored in the page buffer, but also the memory area in which the data is to be stored may also change. That is, the memory area in which the fourth data DATA 4 is to be stored may be determined based on the change row address included in the third address ADDR 3 that is received before the second command CMD 2 is received.
  • FIG. 16 is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure.
  • the memory device may receive a setup command from the memory controller.
  • the setup command may indicate a scheme of programming data. That is, in response to the setup command, a single-level cell (SLC) scheme, a multi-level cell (MLC) scheme, a triple-level cell (TLC) scheme, or a quadruple-level cell (QLC) scheme may be determined, and/or a page program scheme, a multi-plane scheme, or a cache program scheme may be determined in response to the setup command.
  • SLC single-level cell
  • MLC multi-level cell
  • TLC triple-level cell
  • QLC quadruple-level cell
  • the memory device may receive an address and data from the external controller.
  • the address may include a column address and a row address.
  • Data may be stored in a page buffer corresponding to the column address included in the address at step S 1605 , and the data stored in the page buffer may be programmed to an area of the memory cell array.
  • a new command may be received before a confirm command for instructing the programming of the data stored in the page buffer to the memory cell array is received. Therefore, after the data has been stored in the page buffer, it may be determined whether the memory device has received a confirm command from the external controller at step S 1607 .
  • the memory device may perform an operation corresponding to a command determined in response to the confirm command at step S 1609 . That is, using a program scheme determined in response to the setup command, the data stored in the page buffer may be programmed to the memory cell array.
  • step S 1607 when it is determined that the memory device has not received a confirm command (N at S 1607 ), it is determined whether the memory device has received a new command from the external controller at step S 1611 .
  • the process may return to step S 1607 where it is determined whether the memory device has received a confirm command. That is, until the confirm command is received, it may be determined whether the memory device has received a new command.
  • step S 1611 when it is determined that the memory device has received a new command (Y at S 1611 ), the memory device may perform an operation corresponding to the new command at step S 1613 .
  • the new command may be an address change command for changing a memory area in which data is to be stored or a data change command for changing the data stored in the page buffer.
  • the process returns to step S 1607 where it is determined whether the memory device has received a confirm command. That is, until the confirm command is received, the memory area in which data is to be stored may change, and data stored in the page buffer may change.
  • FIG. 17 is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure.
  • FIG. 17 illustrates sub-steps of step S 1613 when a new command is an address change command.
  • the memory device may receive an address change command and a change address from the external controller.
  • the change address may include a change row address.
  • the address change command for changing the memory area in which data is to be stored may be received, and another memory area other than a previously selected memory area may be selected based on the change row address included in the change address that is received together with the address change command at step S 1703 .
  • the memory device may change a scheme of programming data depending on the memory area in which the data is to be stored.
  • FIG. 18 is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure.
  • FIG. 18 illustrates sub-steps of step S 1613 when a new command is a data change command.
  • the memory device may receive a data change command, a change address, and change data from the external controller.
  • the data change command may be for instructing a change of data temporarily stored in a page buffer. Therefore, in response to the data change command, the memory device may select a page buffer corresponding to a change column address included in the change address at step S 1803 . When the page buffer corresponding to the change column address is selected, the memory device may store the change data in the selected page buffer at step S 1805 .
  • the page buffer may be selected and the data stored in the selected page buffer may be changed to the change data, or alternatively, new data may be stored in the selected page buffer.
  • the memory device may determine whether the change address includes a change row address at step S 1807 .
  • the change address includes the change row address (Y at S 1807 )
  • another memory area other than a previously selected memory area may be selected based on the change row address included in the change address at step S 1809 . That is, in response to the data change command, the data stored in the page buffer may change at the same time that the memory area to which the change data is to be programmed may change.
  • FIG. 19 is a block diagram illustrating an example of a solid state drive (SSD) system to which a storage device may be applied according to an embodiment of the present disclosure.
  • SSD solid state drive
  • an SSD system 3000 may include a host 3100 and an SSD 3200 .
  • the SSD 3200 may exchange signals SIG with the host 3100 through a signal connector 3001 and may receive power PWR through a power connector 3002 .
  • the SSD 3200 may include an SSD controller 3210 , a plurality of flash memories 3221 to 322 n , an auxiliary power supply 3230 , and a buffer memory 3240 .
  • the SSD controller 3210 may perform the function of the memory controller 200 described above with reference to FIG. 1 .
  • the SSD controller 3210 may control the plurality of flash memories 3221 to 322 n in response to the signals SIG received from the host 3100 .
  • the signals SIG may be signals based on the interfaces of the host 3100 and the SSD 3200 .
  • the signals SIG may be defined by at least one of various interfaces such as universal serial bus (USB), multi-media card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI-express (PCI-E), advanced technology attachment (ATA), serial-ATA (SATA), parallel-ATA (PATA), small computer small interface (SCSI), enhanced small disk interface (ESDI), integrated drive electronics (IDE), Firewire, universal flash storage (UFS), Wi-Fi, Bluetooth, and/or nonvolatile memory express (NVMe) interfaces.
  • USB universal serial bus
  • MMC multi-media card
  • eMMC embedded MMC
  • PCI peripheral component interconnection
  • PCI-express PCI-express
  • ATA advanced technology attachment
  • SATA serial-ATA
  • PATA parallel-ATA
  • SCSI small computer small interface
  • ESDI enhanced small disk interface
  • IDE integrated drive electronics
  • Firewire universal flash storage
  • UFS universal flash storage
  • Wi-Fi Wi-Fi
  • Bluetooth wireless local flash storage
  • the auxiliary power supply 3230 may be coupled to the host 3100 through the power connector 3002 .
  • the auxiliary power supply 3230 may be supplied with power PWR from the host 3100 and may be charged.
  • the auxiliary power supply 3230 may supply the power of the SSD 3200 when power from the host 3100 is not smoothly delivered.
  • the auxiliary power supply 3230 may be positioned inside the SSD 3200 or positioned outside the SSD 3200 .
  • the auxiliary power supply 3230 may be disposed in a main board and may supply auxiliary power to the SSD 3200 .
  • the buffer memory 3240 functions as a buffer memory of the SSD 3200 .
  • the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322 n or may temporarily store metadata (e.g., mapping tables) of the flash memories 3221 to 322 n .
  • the buffer memory 3240 may include any of various volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and/or GRAM or any of various nonvolatile memories such as FRAM, ReRAM, STT-MRAM, and/or PRAM.
  • Each of the plurality of flash memories 3221 to 322 n may include an address controller.
  • the address controller may change a memory area in which data is to be stored or the data stored in the page buffer in response to an address change command or a data change command received from the SSD controller 3210 .
  • the plurality of flash memories 3221 to 322 n may receive an address change command or a data change command before receiving a confirm command for instructing the initiation of a program operation from the SSD controller 3210 .
  • each of the plurality of flash memories 3221 to 322 n may also receive a change address together with the address change command or the data change command.
  • Each of the flash memories 3221 to 322 n selects a memory area corresponding to a change row address included in the change address, thus changing a data program scheme received from the SSD controller 3210 .
  • a memory device and a method of operating the memory device which reselect a memory area, in which data is to be stored, in response to a newly received command, i.e., a setup command, thus enabling a data program scheme to be changed.

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