US11042126B2 - Time-to-digital converter - Google Patents

Time-to-digital converter Download PDF

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US11042126B2
US11042126B2 US16/900,452 US202016900452A US11042126B2 US 11042126 B2 US11042126 B2 US 11042126B2 US 202016900452 A US202016900452 A US 202016900452A US 11042126 B2 US11042126 B2 US 11042126B2
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signal
ring oscillator
output signal
inverter
counter
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US20200310359A1 (en
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Chao Yuan
Rui Yu
Xuesong Chen
Supeng LIU
Theng Tee Yeo
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Huawei International Pte Ltd
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/005—Time-to-digital converters [TDC]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal

Definitions

  • the present disclosure relates to a time-to-digital converter (TDC).
  • TDC time-to-digital converter
  • Time-to-digital converters have been widely used for more than 20 years in numerous applications requiring precise time-interval measurement. Some examples of the applications include particle and high-energy physics, biomedical imaging (e.g. PET scan), and various time-of-flight (ToF) measurements. Due to the advancement of CMOS technologies, TDCs have also been adopted in All-digital phase-locked loops (ADPLLs) for digital communication systems. By converting time or phase information to digital codes, TDCs have enabled PLLs to evolve towards a fully digital domain to replace conventional analog PLLs. Another emerging field of application for TDCs is TDC-based analog-to-digital converters (ADCs).
  • ADCs analog-to-digital converters
  • TDCs Although the requirements for TDCs differ for various applications, a set of desired general specifications can be defined to include the following: possess a high-resolution, provide a large-dynamic range, exhibit low-power consumption, and occupy a small IC area. Two types of conventional TDCs are next briefly discussed below.
  • FIG. 1 a shows a pseudo-differential flash-type TDC 100 used in a counter-based ADPLL in accordance with the prior art.
  • a high-frequency signal CKV and its complementary signal are first edge-aligned, and passed through a complementary series of 48 inverters.
  • the inverters act as delay elements, and each inverter is configured with a resolution of T inv between 16 ps to 21 ps. Consequently, the CKV signal is eventually delayed by a total time of kT inv , after propagating through k number of inverters—see clock timing diagrams 150 in FIG. 1 b .
  • the delayed-clock replica vector is subsequently sampled using an array of 48 sense-amplifier-based D flip-flops (SADFF), on receipt of a FREF signal. It can be seen that after passing through each inverter, the polarity of the signal is reversed. To therefore generate the correct output, the positive and negative inputs of 7 adjacent SADFF are to be inverted.
  • SADFF sense-amplifier-based D flip-flops
  • the delay-line TDC 100 typically suffers from a trade-off between resolution and dynamic range. For a fixed number of inverter stages, higher resolution means smaller dynamic range, and vice versa. So to extend the dynamic range, the number of inverter stages has to be increased substantially. But this then results in large power consumption and increases the actual IC area needed for implementing the circuit components of the delay-line TDC 100 . Moreover, as the number of inverter stages grows, mismatch among the inverter stages causes severe linearity issue. In addition, the sampling time with different DFFs cannot be perfectly aligned in actual circuit implementation, due to component mismatch. Particularly, the FREF signal is usually transmitted through a buffer tree to be distributed to the DFFs.
  • Any imbalance in the buffer tree may introduce skew for the sampling time of DFFs.
  • the misalignment of the sampling time of different DFFs, and the delay mismatches among the delay cells are thus major sources of non-linearity for the delay-line TDC 100 .
  • a ring-oscillator (RO) based TDC 200 is depicted in FIG. 2 .
  • the delay-line in the RO-based TDC 200 is configured in a ring arrangement.
  • the free-running RO which comprises an odd number of inverters, is used to generate multiple phases at a relative high frequency.
  • the phase from the last stage of the RO is then fed to a high-speed counter, which is configured to run at a high frequency and is switched on constantly.
  • Start and stop signals sample the ring oscillator phases as well as the counter output, respectively. The time difference between the start and stop signals correspond to the eventual TDC output.
  • the sampled counter output can be erroneous, since the start and stop signals are not synchronized with the counter clock.
  • certain assumptions regarding the delay design of the RO-based TDC 200 have been made, which are extremely difficult to satisfy in actual production. As PVT variations and device mismatches come into play, the actual delay time may vary significantly from the target delay time. Hence, there is a high risk that the proposed error correction algorithm (for the RO-based TDC 200 ) may not work as intended in actual manufacturing environments. Further, the continuous free running arrangement for the RO tends to incur substantial power consumption. Adding to that, the counter is always switched on, which wastes power.
  • a time-to-digital converter comprising: a ring oscillator module configured to receive a sampling signal, an addressing signal, and a preset signal, the ring oscillator module includes: a ring oscillator arranged with a plurality of inverters; a phase sampler configured to sample phase signals generated by the inverters of the ring oscillator for generating a first output signal, on receipt of the sampling signal; a counter clock generator configured to generate first and second clock signals, based on receipt of the sampling signal and respective phase signals generated by the first and last inverters of the ring oscillator; first and second counters configured to respectively generate first and second counter output signals, based on receipt of the first and second clock signals respectively; and a data sampler configured to sample the first and second counter output signals to respectively generate second and third output signals; and a digital error correction module arranged to process the first, second and third output signals for generating a digital signal representative of a time difference between receipt
  • TDC time-to-digital converter
  • the data sampler may be implemented using a D flip-flops circuit.
  • the phase sampler may be implemented using a sense-amplifier-based D flip-flops circuit.
  • the first output signal may include a resultant phase signal based upon the phase signals generated by the inverters.
  • the TDC may further comprise a digital control module arranged to receive the start and stop signals for generating the sampling signal, the addressing signal, and the preset signal.
  • the digital control module includes: a pseudo-random code generator configured to generate the identification to randomly address one of the inverters of the ring oscillator selected to be preset; and a control signal generator configured to generate the sampling signal and the preset signal.
  • the identification may be predetermined to preset a same inverter at each conversion cycle.
  • the digital error correction module may be configured to perform the following step for processing the first, second and third output signals: determining if the phase signal generated by the first inverter has a value of 0 or 1. If the phase signal generated by the first inverter has a value of 0, the third output signal is selected for processing by the digital error correction module, or if the phase signal generated by the first inverter has a value of 1, the second output signal is selected for processing by the digital error correction module, in which the second output signal is further processed using both a value of the phase signal generated by the last inverter and a predefined value associated with a corresponding inverter selected to be preset at each conversion cycle of the ring oscillator, wherein the predefined value is further associated with the identification.
  • the counter clock generator may include being arranged to stop the phase signals generated by the first and last inverters that are provided to the counter clock generator, in which stoppage of the phase signals is performed based on the sampling signal.
  • a method of time-to-digital conversion using the TDC of the first aspect comprises: (i) generating the phase signals by the inverters of the ring oscillator; (ii) sampling the phase signals by the phase sampler for generating a first output signal, on receipt of the sampling signal by the ring oscillator module; (iii) generating first and second clock signals by the counter clock generator, based on receipt of the sampling signal and phase signals generated respectively by the first and last inverters of the ring oscillator; (iv) generating first and second counter output signals by the first and second counters, based on receipt of the first and second clock signals respectively; (v) sampling the first and second counter output signals by the data sampler to respectively generate second and third output signals; and (vi) processing the first, second and third output signals by the digital error correction module for generating a digital signal representative of a time difference between receipt of a start signal and receipt of a stop signal by the TDC.
  • the method also includes operating the ring oscillator between first and second modes on receipt of the preset signal, in which in the first mode, the ring oscillator is electrically switched on for a period corresponding to the time difference, and in the second mode, the ring oscillator is electrically switched off by presetting an inverter based on the addressing signal, which includes an identification of the inverter selected to be preset at each conversion cycle of the ring oscillator.
  • step (vi) may include: determining if the phase signal generated by the first inverter has a value of 0 or 1, wherein if the phase signal generated by the first inverter has a value of 0, the third output signal is selected for processing by the digital error correction module, or if the phase signal generated by the first inverter has a value of 1, the second output signal is selected for processing by the digital error correction module, in which the second output signal is further processed using both a value of the phase signal generated by the last inverter and a predefined value associated with a corresponding inverter selected to be preset at each conversion cycle of the ring oscillator.
  • the predefined value is further associated with the identification.
  • a time-to-digital converter comprising: a ring oscillator module configured to receive a sampling signal, an addressing signal, and a preset signal.
  • the ring oscillator module includes: a ring oscillator arranged with a plurality of inverters; a phase sampler configured to sample phase signals generated by the inverters of the ring oscillator for generating a first output signal, on receipt of the sampling signal; a counter clock generator configured to generate first and second clock signals, based on receipt of the sampling signal and respective phase signals generated by the first and last inverters of the ring oscillator; first and second counters configured to respectively generate first and second counter output signals, based on receipt of the first and second clock signals respectively; and a data sampler configured to sample the first and second counter output signals to respectively generate second and third output signals; a digital error correction module arranged to process the first, second and third output signals for generating a digital signal representative of a time difference between receipt of
  • FIG. 1 a shows schematics of an inverter-based delay-line time-to-digital converter (TDC), and FIG. 1 b shows clock timing diagrams of clock signals generated at different stages of the delay-line TDC of FIG. 1 a , according to the prior art.
  • TDC delay-line time-to-digital converter
  • FIG. 2 shows schematics of a ring-oscillator (RO) based TDC, according to the prior art.
  • RO ring-oscillator
  • FIG. 3 shows schematics of a proposed TDC, according to an embodiment.
  • FIG. 4 is a flow diagram of a method of time-to-digital conversion using the TDC of FIG. 3 .
  • FIG. 5 shows clock timing diagrams illustrating an example of possible errors occurring in a conventional counter output selection method for a 5-stage ring oscillator TDC, according to the prior art.
  • FIGS. 6 a and 6 b are timing diagrams of a proposed digital error correction method used in the TDC of FIG. 3 .
  • FIG. 7 shows a flow diagram of the proposed digital error correction method.
  • FIG. 8 illustrates random presetting of different inverters of a ring oscillator in the TDC of FIG. 3 at different conversion cycles.
  • FIG. 9 depicts graphical comparison of measured TDC differential non-linearity (DNL) results.
  • FIG. 10 depicts timing diagrams of the TDC of FIG. 3 , when configured to be operated using a varying preset_address scheme.
  • FIG. 11 depicts timing diagrams of the TDC of FIG. 3 , when configured to be operated using a fixed preset_address scheme.
  • FIG. 3 is a schematic diagram of a proposed time-to-digital converter (TDC) 300 , according to an embodiment.
  • the TDC 300 may also be referred to as a recirculating TDC 300 .
  • the TDC 300 comprises a (presettable) ring oscillator module 302 and a digital error correction module 304 .
  • the ring oscillator module 302 is configured to receive a sampling signal, an addressing signal, and a preset signal, and the ring oscillator module 302 includes: a ring oscillator 3022 arranged with a plurality of inverters 3024 (sequentially arranged in N-stages, where N represents the number of stages, e.g.
  • N may be 15); a phase sampler 3026 configured to sample phase signals (i.e. indicated respectively as V out ⁇ 0>, V out ⁇ 1>, . . . V out ⁇ N ⁇ 1> in FIG. 3 ) generated by the inverters 3024 of the ring oscillator 3022 for generating a first output signal (i.e. indicated as frac in FIG. 3 ), on receipt of the sampling signal; a counter clock generator 3028 (implemented using conventional AND logic gates and) configured to generate first and second clock signals (i.e. indicated respectively as clk_cnt0 and clk_cnt1 in FIG.
  • first and second counters 3030 , 3032 i.e. indicated as CNT0 and CNT1 in FIG. 3 ) configured to respectively generate first and second counter output signals (i.e. indicated respectively as cnt0 and cnt1 in FIG. 3 ), based on receipt of the first and second clock signals respectively; and a data sampler 3034 configured to sample the first and second counter output signals to respectively generate second and third output signals.
  • the digital error correction module 304 is arranged to process the first, second and third output signals for generating a digital signal representative of a time difference between receipt of a start signal and receipt of a stop signal by the TDC 300 .
  • the digital error correction module 304 is devised to correct a miscounting error arising due to the first and second clock signals (i.e. clk_cnt0 and clk_cnt1) not synchronized with the clock frequency of the start and stop signals (i.e. both signals have the same clock frequency), thereby causing the second and third output signals to be erroneous in that respect.
  • the digital signal is generated in the form of a binary code in this case.
  • the start signal and the stop signal are respectively generated in response to occurrence and termination of an event, in which the time difference between the occurrence and termination is to be measured using the TDC 300 .
  • the counter clock generator 3028 is arranged to stop the phase signals generated by the first and last inverters 3024 that are provided to the counter clock generator 3028 , in which the stoppage of the phase signals is performed based on the sampling signal.
  • the ring oscillator 3022 is arranged to be operated between first and second modes on receipt of the preset signal, in which in the first mode, the ring oscillator 3022 is electrically switched on for a period corresponding to the time difference, and in the second mode, the ring oscillator 3022 is electrically switched off by presetting an inverter 3024 based on the addressing signal, which includes an identification of the inverter 3024 selected to be preset at each conversion cycle of the ring oscillator 3022 . That is, the ring oscillator 3022 is switched on and switched off by the preset signal in both said modes.
  • the phase sampler 3026 is implemented using a sense-amplifier-based D flip-flops (SA-DFFs) circuit (e.g. using N number of SA-DFFs, and the N in this context has the same value as the number of stages configured for the ring oscillator 3022 ), while the data sampler 3034 is implemented using a D flip-flops circuit.
  • the first output signal i.e frac
  • the first output signal may also be defined in the format of: frac ⁇ 0; N ⁇ 1>, and there is a one-to-one mapping with V out ⁇ 0; N ⁇ 1>.
  • frac ⁇ 0> is an equivalent sampled value of V out ⁇ 0>
  • frac ⁇ 2> is then an equivalent sampled value of V out ⁇ 2>, so on and so forth, as will be understood.
  • the TDC 300 may optionally further comprise a digital control module 306 arranged to receive the start and stop signals transmitted to the TDC 300 . Based on receipt of the start and stop signals, the digital control module 306 is configured to generate the sampling signal, the addressing signal, and the preset signal. Particularly, the digital control module 306 includes: a pseudo-random code generator 3062 (implemented in the form of a TDC preset randomization module) configured to generate the identification (i.e.
  • an N-bit preset_address to randomly address one of the inverters 3024 of the ring oscillator 3022 selected to be preset at each (time-to-digital) conversion cycle of the ring oscillator 3022 ; and a control signal generator 3064 configured to generate the sampling signal and the preset signal.
  • the digital control module 306 is functionable as a control signal generation block of the TDC 300 .
  • the pseudo-random code generator 3062 is configured to perform modulo operations in order to generate the N-bit preset_address. Then, to clarify the definition of “conversion cycle,” it is to be noted that the TDC 300 is configured to be operated on two input clocks running at a same frequency.
  • conversion cycle in this context means from the start of a (time-to-digital) conversion to the start of a next immediate (time-to-digital) conversion. Basically, the “conversion cycle” is therefore equal to one clock cycle of an input signal to the TDC 300 .
  • the N-bit preset_address is linked to the start_code, and there is a one-to-one mapping between the N-bit preset_address and the start_code.
  • the start_code may also be known as the start_phase, which is the initial phase of the ring oscillator 3022 , during the preset state (i.e. the second mode). This initial phase is encoded by a TDC encoder to generate a binary code (i.e. the start_code).
  • the one-to-one mapping refers to associating the start_code with the N-bit preset_address.
  • the method 400 comprises: at step 402 , generating the phase signals by the inverters 3024 of the ring oscillator 3022 ; at step 404 , sampling the phase signals by the phase sampler 3026 for generating a first output signal (on receipt of the sampling signal by the ring oscillator module); at step 406 , generating first and second clock signals by the counter clock generator 3028 (based on receipt of the sampling signal and phase signals generated respectively by the first and last inverters 3024 of the ring oscillator 3022 ); at step 408 , generating first and second counter output signals by the first and second counters 3030 , 3032 (based on receipt of the first and second clock signals respectively); at step 410 , sampling the first and second counter output signals by the data sampler 3034 to respectively generate second and third output signals; and at step 412 , processing the first, second and third output signals by the digital error correction module
  • the method 400 also includes a step of operating (not shown) the ring oscillator 3022 between first and second modes on receipt of the preset signal, in which in the first mode, the ring oscillator 3022 is electrically switched on for a period corresponding to the time difference, and in the second mode, the ring oscillator 3022 is electrically switched off by presetting an inverter 3024 based on the addressing signal, which includes an identification of the inverter 3024 selected to be preset at each conversion cycle of the ring oscillator 3022 .
  • FIG. 5 shows clock timing diagrams 500 illustrating an example of possible errors occurring in a conventional counter output selection method (not shown) for a 5-stage ring oscillator TDC, according to the prior art.
  • the counter output i.e CNT0
  • the counter output is generally considered error-free, and therefore selected as the final counter value.
  • miscounting problem may still manifest in this conventional selection method at the transition of frac_phase from 2N ⁇ 1 to 0, or from N to N+1. The reason for this may be due to mismatch of ring oscillator phase sampling the SA-DFF clock and counter output sampling DFF clock, in which the said two clock signals are derived from a common source.
  • the two sets of DFFs are usually designed with different circuit structures to save power and IC area.
  • the SA-DFFs are customized latch-type dynamic comparators that are optimized for power, speed and metastability, whereas the DFFs used to sample counter outputs are normally not optimized as such.
  • a digital error correction method 700 is hereby proposed to be used in the TDC 300 of FIG. 3 , in which the first and second clock signals of the first and second counters 3030 , 3032 are arranged to be stopped to allow the first and second counter output signals to settle. It is to be appreciated that stopping the first and second clock signals of the first and second counters 3030 , 3032 means that the associated clock signal goes to 0 level at some condition, e.g. when a signal goes from low level to high level. Only when the first and second counter output signals have settled, the outputs of the first and second counters 3030 , 3032 are then sampled.
  • FIGS. 6 a and 6 b Detailed timing diagrams of the digital error correction method 700 are shown in FIGS. 6 a and 6 b .
  • FIGS. 6 a and 6 b respectively show that when V out ⁇ 0> is sampled as 1, cnt0 (i.e. the first counter output signal) is then used, and when V out ⁇ 0> is sampled as 0 instead, cnt1 (i.e. the second counter output signal) is used.
  • cnt0 i.e. the first counter output signal
  • cnt1 i.e. the second counter output signal
  • the cnt_out_sample signal is the same sampling signal generated by the control signal generator 3064 .
  • a minimum pulse width T pulse is required as depicted in FIG. 6 a .
  • This pulse width is the minimum high time of counter clock signal for the first counter 3030 to toggle, and the required value of T pulse may be obtained through simulations performed under different PVT conditions. But in this instance, a programmable delay was used to generate the required T pulse purely for purpose of experimental investigations.
  • the disclosed digital error correction method 700 is much more simplified on the timing requirements. More importantly, counter delay and metastability do not play any role in determining the T pulse requirement, or affect circuit performance. Hence, the disclosed digital error correction method 700 is beneficially more robust against PVT variations.
  • FIG. 7 shows a flow diagram of the proposed digital error correction method 700 (in which implementation is via a counter output selection and compensation algorithm).
  • selection of the first and second counter output signals to be used by the data sampler 3034 is based on values of frac ⁇ 0> and frac ⁇ N>, in which frac ⁇ 0> and frac ⁇ N> are the first and last SA-DFF outputs respectively. If frac ⁇ 0> is 0, the second counter 3032 (CNT1) is selected; otherwise if the value of if frac ⁇ 0> is 1 instead, the first counter 3030 (CNT0) is selected.
  • the start_code is a predefined value associated with each inverter 3024 in the ring oscillator 3022 .
  • a different inverter 3024 is (randomly) selected for presetting, its corresponding start_code is then used for calculating the binary code in the digital signal generated by the digital error correction module 304 .
  • the start_code is determined by the N-bit preset_address (of the addressing signal), in which the start_code is to be subtracted from the first output signal (i.e. frac).
  • step 412 may broadly include: determining if the phase signal generated by the first inverter 3024 has a value of 0 or 1, wherein if the phase signal generated by the first inverter 3024 has a value of 0, the third output signal is selected for processing by the digital error correction module 304 , or if the phase signal generated by the first inverter 3024 has a value of 1, the second output signal is selected for processing by the digital error correction module 304 , in which the second output signal is further processed using both a value of the phase signal generated by the last inverter 3024 and a predefined value associated with a corresponding inverter 3024 randomly selected to be preset at each conversion cycle of the ring oscillator 3022 . It is to be appreciated that the predefined value is further associated with the identification.
  • FIG. 8 illustrates a concept 800 directed at random presetting of different inverters 3024 of the ring oscillator 3022 in the TDC 300 of FIG. 3 at different conversion cycles.
  • an inverter 3024 is selected to be preset (i.e. to stop electrical operation of the said inverter 3024 , which has an effect of causing the ring oscillator 3022 to stop oscillation)
  • both its input and output are at high.
  • the preset signal is de-asserted, output of the selected inverter 3024 is discharged to low and an oscillation starts.
  • the TDC conversion starts accordingly.
  • the preset signal goes high and the ring oscillator 3022 stops oscillation.
  • each inverter stage in the ring oscillator 3022 has different delay (inherently), thereby resulting in TDC non-linearity. So to improve the non-linearity performance of the TDC 300 , it is herein proposed to preset a different random inverter 3024 (of the ring oscillator 3022 ) each time. This is achieved by generating the identification (e.g. device address) of an inverter 3024 through a random process using the pseudo-random code generator 3062 . Theoretically, each output of the inverter 3024 has the same probability of hitting the same TDC output code. This is equivalent to imposing an averaging effect of inverter cell mismatch. Accordingly, FIG.
  • FIG. 9 depicts graphical comparison 900 of measured TDC differential non-linearity (DNL) results obtained from a conventional method for presetting a fixed inverter (of a ring oscillator), and the proposed method for presetting different random inverters (of a ring oscillator). It can clearly be seen from FIG. 9 that the proposed method effectively reduces TDC non-linearity.
  • DNL differential non-linearity
  • the proposed TDC 300 is purposefully devised to have high resolution, large dynamic range, and also only requires a small IC area for actual circuit implementation.
  • the TDC 300 is also configured to use the digital error correction method 700 to resolve the counter miscounting problem and provide an error free output (generated by the digital error correction module 304 ).
  • the digital error correction method 700 is configured to deliberately stop the clocks of the first and second counters 3030 , 3032 , when a stop signal is received by the TDC 300 . In this manner, outputs of the first and second counters 3030 , 3032 do not change until reset, and so outputs of the first and second counters 3030 , 3032 can be sampled when the outputs have settled.
  • the said TDC 300 can be electrically stopped when the ring phase and counter output are read out properly, thus resulting in low power operation.
  • Each inverter 3042 in the ring oscillator 3022 has a same probability to be preset, regardless of the input to the TDC 300 .
  • the TDC linearity of the TDC 300 is improved due to the averaging effect.
  • the digital control module 306 may also be included as part of the TDC 300 of FIG. 3 .
  • the N-bit preset_address may also be predefined as a fixed value, instead of being randomly selected using the pseudo-random code generator 3062 . That is, a user of the TDC 300 may provide the fixed value for the N-bit preset_address to determine which inverter 3024 to be preset. Particularly, a same inverter 3024 is arranged to be preset at every conversion cycle under this variation. Accordingly, the pseudo-random code generator 3062 is thus switched off in this instance, and not in use operatively. This also means that the start_code will change accordingly, due to change in the N-bit preset_address. In one example, the start_code may be arranged to take on a zero value.
  • FIG. 10 depicts timing diagrams of the TDC 300 of FIG. 3 , when configured to be operated using a varying preset_address scheme. It may be observed that the rate of change of varying the N-bit preset_address is also programmable, i.e. two examples are shown in FIG. 10 . Other rates of change are possible too, such as varying in every 4 cycles or 8 cycles.
  • FIG. 11 depicts timing diagrams of the TDC 300 of FIG. 3 , when configured to be operated using a fixed preset_address scheme. It may be seen that the N-bit preset_address is arranged to be of a fixed value for every conversion cycle.
  • the N-bit preset_address need not be set to 0 in every case. Indeed, the N-bit preset_address may take on a value from the range 0 to N ⁇ 1 (i.e. 0 ⁇ preset_address ⁇ N ⁇ 1), where N is a number of inverters 3024 arranged in the ring oscillator 3022 .

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